jtag/vdebug: add support for DAP6

This change implements the support for the ARM Debug Interface v6.
The DAP-level interface properly selects the DP Banks and AP address.
Sample ARM configuration DAP and JTAG scripts have been updated.

Change-Id: I7df87ef764bca587697c778810443649a7f46c2b
Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8067
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

9 files changed, 136 insertions, 68 deletions

diff --git a/tcl/board/vd_a53x2_dap.cfg b/tcl/board/vd_a53x2_dap.cfg
index 4cf5594..bcf8b44 100644
--- a/tcl/board/vd_a53x2_dap.cfg
+++ b/tcl/board/vd_a53x2_dap.cfg
@@ -4,10 +4,13 @@
 
 source [find interface/vdebug.cfg]
 
-set _CORES 2
-set _CHIPNAME a53
-set _MEMSTART 0x00000000
-set _MEMSIZE 0x1000000
+set CORES 2
+set CHIPNAME a53
+set ACCESSPORT 0
+set MEMSTART 0x00000000
+set MEMSIZE 0x1000000
+set DBGBASE {0x80810000 0x80910000}
+set CTIBASE {0x80820000 0x80920000}
 
 # vdebug select transport
 transport select dapdirect_swd
@@ -19,11 +22,9 @@ adapter srst delay 5
 # BFM hierarchical path and input clk period
 vdebug bfm_path tbench.u_vd_swdp_bfm 10ns
 
-# DMA Memories to access backdoor (up to 4)
-vdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE
+# DMA Memories to access backdoor (up to 20)
+vdebug mem_path tbench.u_memory.mem_array $MEMSTART $MEMSIZE
 
-source [find target/swj-dp.tcl]
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
 
 source [find target/vd_aarch64.cfg]
diff --git a/tcl/board/vd_a53x2_jtag.cfg b/tcl/board/vd_a53x2_jtag.cfg
index a5e8d24..0c3eebd 100644
--- a/tcl/board/vd_a53x2_jtag.cfg
+++ b/tcl/board/vd_a53x2_jtag.cfg
@@ -4,11 +4,14 @@
 
 source [find interface/vdebug.cfg]
 
-set _CORES 2
-set _CHIPNAME a53
-set _MEMSTART 0x00000000
-set _MEMSIZE 0x1000000
-set _CPUTAPID 0x5ba00477
+set CORES 2
+set CHIPNAME a53
+set ACCESSPORT 0
+set MEMSTART 0x00000000
+set MEMSIZE 0x1000000
+set DBGBASE {0x80810000 0x80910000}
+set CTIBASE {0x80820000 0x80920000}
+set CPUTAPID 0x5ba00477
 
 # vdebug select transport
 transport select jtag
@@ -21,11 +24,10 @@ adapter srst delay 5
 # BFM hierarchical path and input clk period
 vdebug bfm_path tbench.u_vd_jtag_bfm 10ns
 
-# DMA Memories to access backdoor (up to 4)
-vdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+# DMA Memories to access backdoor (up to 20)
+vdebug mem_path tbench.u_memory.mem_array $MEMSTART $MEMSIZE
 
+jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
 jtag arp_init-reset
 
 source [find target/vd_aarch64.cfg]
diff --git a/tcl/board/vd_a75x4_dap.cfg b/tcl/board/vd_a75x4_dap.cfg
new file mode 100644
index 0000000..5c2a2ef
--- /dev/null
+++ b/tcl/board/vd_a75x4_dap.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm Cortex A53x2 through DAP
+
+source [find interface/vdebug.cfg]
+
+set CORES 4
+set CHIPNAME a75
+set ACCESSPORT 0x00040000
+set MEMSTART 0x00000000
+set MEMSIZE 0x1000000
+set DBGBASE {0x01010000 0x01110000 0x01210000 0x01310000}
+set CTIBASE {0x01020000 0x01120000 0x01220000 0x01320000}
+
+# vdebug select transport
+transport select dapdirect_swd
+
+# JTAG reset config, frequency and reset delay
+adapter speed 200000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_dap6_bfm 2250ps
+
+# DMA Memories to access backdoor (up to 20)
+#vdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE
+
+swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+
+source [find target/vd_aarch64.cfg]
diff --git a/tcl/board/vd_a75x4_jtag.cfg b/tcl/board/vd_a75x4_jtag.cfg
new file mode 100644
index 0000000..c94a719
--- /dev/null
+++ b/tcl/board/vd_a75x4_jtag.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Arm Cortex A53x2 through DAP
+
+source [find interface/vdebug.cfg]
+
+set CORES 4
+set CHIPNAME a75
+set ACCESSPORT 0x00040000
+set MEMSTART 0x00000000
+set MEMSIZE 0x1000000
+set DBGBASE {0x01010000 0x01110000 0x01210000 0x01310000}
+set CTIBASE {0x01020000 0x01120000 0x01220000 0x01320000}
+set CPUTAPID 0x4ba06477
+
+# vdebug select transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 1500000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path tbench.u_vd_jtag_bfm 333ps
+
+jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
+jtag arp_init-reset
+
+source [find target/vd_aarch64.cfg]
diff --git a/tcl/board/vd_m4_dap.cfg b/tcl/board/vd_m4_dap.cfg
index 691b623..5d3605a 100644
--- a/tcl/board/vd_m4_dap.cfg
+++ b/tcl/board/vd_m4_dap.cfg
@@ -4,9 +4,9 @@
 
 source [find interface/vdebug.cfg]
 
-set _CHIPNAME m4
-set _MEMSTART 0x00000000
-set _MEMSIZE 0x10000
+set CHIPNAME m4
+set MEMSTART 0x00000000
+set MEMSIZE 0x10000
 
 # vdebug select transport
 transport select dapdirect_swd
@@ -16,11 +16,9 @@ adapter srst delay 5
 # BFM hierarchical path and input clk period
 vdebug bfm_path tbench.u_vd_swdp_bfm 20ns
 
-# DMA Memories to access backdoor (up to 4)
-vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $_MEMSTART $_MEMSIZE
+# DMA Memories to access backdoor (up to 20)
+vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $MEMSTART $MEMSIZE
 
-source [find target/swj-dp.tcl]
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
+swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
 
 source [find target/vd_cortex_m.cfg]
diff --git a/tcl/board/vd_m4_jtag.cfg b/tcl/board/vd_m4_jtag.cfg
index 4c795eb..3b32e17 100644
--- a/tcl/board/vd_m4_jtag.cfg
+++ b/tcl/board/vd_m4_jtag.cfg
@@ -4,10 +4,10 @@
 
 source [find interface/vdebug.cfg]
 
-set _CHIPNAME m4
-set _MEMSTART 0x00000000
-set _MEMSIZE 0x10000
-set _CPUTAPID 0x4ba00477
+set CHIPNAME m4
+set MEMSTART 0x00000000
+set MEMSIZE 0x10000
+set CPUTAPID 0x4ba00477
 
 # vdebug select transport
 transport select jtag
@@ -20,11 +20,10 @@ adapter srst delay 5
 # BFM hierarchical path and input clk period
 vdebug bfm_path tbench.u_vd_jtag_bfm 20ns
 
-# DMA Memories to access backdoor (up to 4)
-vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $_MEMSTART $_MEMSIZE
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+# DMA Memories to access backdoor (up to 20)
+vdebug mem_path tbench.u_mcu.u_sys.u_rom.rom $MEMSTART $MEMSIZE
 
+jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
 jtag arp_init-reset
 
 source [find target/vd_cortex_m.cfg]
diff --git a/tcl/board/vd_m7_jtag.cfg b/tcl/board/vd_m7_jtag.cfg
index 880ef9b..9a89584 100644
--- a/tcl/board/vd_m7_jtag.cfg
+++ b/tcl/board/vd_m7_jtag.cfg
@@ -4,10 +4,10 @@
 
 source [find interface/vdebug.cfg]
 
-set _CHIPNAME m7
-set _MEMSTART 0x00000000
-set _MEMSIZE 0x100000
-set _CPUTAPID 0x0ba02477
+set CHIPNAME m7
+set MEMSTART 0x00000000
+set MEMSIZE 0x100000
+set CPUTAPID 0x0ba02477
 
 # vdebug select JTAG transport
 transport select jtag
@@ -20,11 +20,10 @@ adapter srst delay 5
 # BFM hierarchical path and input clk period
 vdebug bfm_path tbench.u_vd_jtag_bfm 10ns
 
-# DMA Memories to access backdoor (up to 4)
-vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+# DMA Memories to access backdoor (up to 20)
+vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $MEMSTART $MEMSIZE
 
+jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
 jtag arp_init-reset
 
 source [find target/vd_cortex_m.cfg]
diff --git a/tcl/target/vd_aarch64.cfg b/tcl/target/vd_aarch64.cfg
index 619134a..177416b 100644
--- a/tcl/target/vd_aarch64.cfg
+++ b/tcl/target/vd_aarch64.cfg
@@ -2,36 +2,44 @@
 # Cadence virtual debug interface
 # Arm v8 64b Cortex A
 
-if {![info exists _CORES]} {
-	set _CORES 1
+if {![info exists CORES]} {
+	set CORES 1
 }
-if {![info exists _CHIPNAME]} {
-	set _CHIPNAME aarch64
+if {![info exists CHIPNAME]} {
+	set CHIPNAME aarch64
+}
+if {[info exists ACCESSPORT]} {
+	set _APNUM "-ap-num $ACCESSPORT"
+	if { $ACCESSPORT > 0xff } {
+		set _DAP6 "-adiv6"
+	} else {
+		set _DAP6 "-adiv5"
+	}
+} else {
+	set _APNUM ""
 }
-set _TARGETNAME $_CHIPNAME.cpu
-set _CTINAME $_CHIPNAME.cti
 
-set DBGBASE {0x80810000 0x80910000}
-set CTIBASE {0x80820000 0x80920000}
+set _TARGETNAME $CHIPNAME.cpu
+set _CTINAME $CHIPNAME.cti
+set _DAPNAME $CHIPNAME.dap
 
-dap create $_CHIPNAME.dap -chain-position $_TARGETNAME
-$_CHIPNAME.dap apsel 1
+dap create $_DAPNAME $_DAP6 -chain-position $_TARGETNAME
 
-for { set _core 0 } { $_core < $_CORES } { incr _core } \
+for { set _core 0 } { $_core < $CORES } { incr _core } \
 {
-	cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 -baseaddr [lindex $CTIBASE $_core]
-	set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
-	-dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core"
+	set _cmd "cti create $_CTINAME.$_core -dap $_DAPNAME $_APNUM -baseaddr [lindex $CTIBASE $_core]"
+	eval $_cmd
+	set _cmd "target create $_TARGETNAME.$_core aarch64 -dap $_DAPNAME $_APNUM -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core"
 	if { $_core != 0 } {
 		# non-boot core examination may fail
-		set _command "$_command -defer-examine"
-		set _smp_command "$_smp_command $_TARGETNAME.$_core"
+		set _cmd "$_cmd -defer-examine"
+		set _smp_cmd "$_smp_cmd $_TARGETNAME.$_core"
 	} else {
-		set _smp_command "target smp $_TARGETNAME.$_core"
+		set _smp_cmd "target smp $_TARGETNAME.$_core"
 	}
-	eval $_command
+	eval $_cmd
 }
-eval $_smp_command
+eval $_smp_cmd
 
-# default target is core 0
-targets $_TARGETNAME.0
+set _TARGETCUR $_TARGETNAME.0
+targets $_TARGETCUR
diff --git a/tcl/target/vd_cortex_m.cfg b/tcl/target/vd_cortex_m.cfg
index 4d7b0df..7db9d3a 100644
--- a/tcl/target/vd_cortex_m.cfg
+++ b/tcl/target/vd_cortex_m.cfg
@@ -2,11 +2,12 @@
 # Cadence virtual debug interface
 # ARM Cortex M
 
-if {![info exists _CHIPNAME]} {
-	set _CHIPNAME cortex_m
+if {![info exists CHIPNAME]} {
+	set CHIPNAME cortex_m
 }
-set _TARGETNAME $_CHIPNAME.cpu
+set _TARGETNAME $CHIPNAME.cpu
+set _DAPNAME $CHIPNAME.dap
 
-dap create $_CHIPNAME.dap -chain-position $_TARGETNAME
+dap create $_DAPNAME -chain-position $_TARGETNAME
 
-target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+target create $_TARGETNAME cortex_m -dap $_DAPNAME