tcl/target: add Allwinner V3s SoC support

Change-Id: I2459d2b137050985b7301047f9651951d72d9e9e
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/4427
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

1 files changed, 71 insertions, 0 deletions

diff --git a/tcl/target/allwinner_v3s.cfg b/tcl/target/allwinner_v3s.cfg
new file mode 100644
index 0000000..32fd188
--- /dev/null
+++ b/tcl/target/allwinner_v3s.cfg
@@ -0,0 +1,71 @@
+# This is the config for an Allwinner V3/V3s (sun8iw8).
+#
+# Notes:
+# - Single core ARM Cortex-A7 with a maximum frequency of 1.2 GHz.
+# - Thumb-2 Technology
+# - Support NEON Advanced SIMD(Single Instruction Multiple Data)instruction
+#   for acceleration of media and signal processing functions
+# - Support Large Physical Address Extensions(LPAE)
+# - VFPv4 Floating Point Unit
+# - 32KB L1 Instruction cache and 32KB L1 Data cache
+# - 128KB L2 cache
+# - has some integrated DDR2 RAM.
+#
+# Pins related for debug and bootstrap:
+#   JTAG
+# JTAG_TMS	PF0, SDC0_D1
+# JTAG_TDI	PF1, SDC0_D0
+# JTAG_TDO	PF3, SDC0_CMD
+# JTAG_TCK	PF5, SDC0_D2
+#   UART
+# None of UART ports seems to be enabled by ROM.
+# UART0_TX	PF2, SDC0_CLK		Per default disabled
+# UART0_RX	PF4, SDC0_D3 		Per default disabled
+# UART1_TX	PE21			Per default disabled
+# UART1_RX	PE22	 		Per default disabled
+# UART2_TX	PB0			Per default disabled
+# UART2_RX	PB1	 		Per default disabled
+#
+# JTAG is enabled by default after power on on listed JTAG_* pins. So far the
+# boot sequence is:
+# Time		Action
+# 0000ms	Power ON
+# 0200ms	JTAG enabled
+# 0220ms	JTAG pins switched to SD mode
+#
+# The time frame of 20ms can be not enough to init and halt the CPU. In this
+# case I would recommend to set: "adapter_khz 15000"
+# To get more or less precise timings, the board should provide reset pin,
+# or some bench power supply with remote function. In my case I used
+# EEZ H24005 with this command to power on and halt the target:
+# "exec  echo "*TRG" > /dev/ttyACM0; sleep 220; reset halt"
+# After this it is possible to enable JTAG mode again from boot loader or OS.
+# Following DAPs are available:
+# dap[0]->MEM-AP AHB
+# dap[1]->MEM-AP APB->CA7[0]
+#
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME v3s
+}
+
+if { [info exists DAP_TAPID] } {
+        set _DAP_TAPID $DAP_TAPID
+} else {
+        set _DAP_TAPID 0x5ba00477
+}
+
+# No NRST or SRST is present on the SoC. Boards may provide
+# some sort of Power cycle reset for complete board or SoC.
+# For this case we provide srst_pulls_trst so the board config
+# only needs to set srst_only.
+reset_config none srst_pulls_trst
+
+jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+# Add Cortex A7 core
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap