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author | Tomas Vanek <vanekt@fbl.cz> | 2017-10-27 21:43:25 +0200 |
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committer | Tomas Vanek <vanekt@fbl.cz> | 2019-02-05 17:45:18 +0000 |
commit | deaf3d264123391d8fe5c4cccbf8fb8852e1be23 (patch) | |
tree | 321b1363c50f907a1aa1e81e5d1e2e046f6c0848 /tcl/target | |
parent | 346ce2f13f48f36550b2a1a3862801496e20c81b (diff) | |
download | riscv-openocd-deaf3d264123391d8fe5c4cccbf8fb8852e1be23.zip riscv-openocd-deaf3d264123391d8fe5c4cccbf8fb8852e1be23.tar.gz riscv-openocd-deaf3d264123391d8fe5c4cccbf8fb8852e1be23.tar.bz2 |
flash/nor: flash driver and cfg for SAM E54, E53, E51 and D51
The new Microchip (former Atmel) series powered by Cortex-M4 looks
very similar to older M0+ powered SAM D2x at the first sight.
Unfortunately the new series differs a lot in important details.
NVMCTRL has different register addresses, moved important bits
and even changed binary command set. An universal driver for all SAM D/E
would be very complicated. That's why a new driver was derived.
Tested on Microchip SAM E54 Xplained Pro kit (board cfg included).
Adjusted for the restructured dap support.
Checked by valgrind and clang static analyzer.
Change-Id: I26c67047a552076f4b207b9b89285a53d69b4ca4
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4272
Tested-by: jenkins
Reviewed-by: Andres Vahter <andres.vahter@gmail.com>
Diffstat (limited to 'tcl/target')
-rw-r--r-- | tcl/target/atsame5x.cfg | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/tcl/target/atsame5x.cfg b/tcl/target/atsame5x.cfg new file mode 100644 index 0000000..61949cf --- /dev/null +++ b/tcl/target/atsame5x.cfg @@ -0,0 +1,75 @@ +# +# Microchip (former Atmel) SAM E54, E53, E51 and D51 devices +# with a Cortex-M4 core +# + +# +# Devices only support SWD transports. +# +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME atsame5 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# By default use 32kB (the smallest RAM size is 128kB) +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x8000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4ba00477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# SAM DSU will hold the CPU in reset if TCK is low when RESET_N +# deasserts +# +# dsu_reset_deassert configures whether we want to run or halt out of reset, +# then instruct the DSU to let us out of reset. +$_TARGETNAME configure -event reset-deassert-post { + atsame5 dsu_reset_deassert +} + +# SRST (wired to RESET_N) resets debug circuitry +# srst_pulls_trst is not configured here to avoid an error raised in reset halt +reset_config srst_gates_jtag + +# Do not use a reset button with other SWD adapter than Atmel's EDBG. +# DSU usually locks MCU in reset state until you issue a reset command +# in OpenOCD. + +# SAM E5x/D51 runs at SYSCLK = 48 MHz from RC oscillator after reset. +# Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works +# without problem at clock speed over 5000 khz. Atmel recommends +# adapter speed less than 10 * CPU clock. +adapter_khz 2000 + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME atsame5 0x00000000 0 1 1 $_TARGETNAME |