diff options
| author | Nishanth Menon <nm@ti.com> | 2023-09-13 17:57:29 -0500 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2023-10-07 14:46:01 +0000 |
| commit | d14fef8495e6d0247ea2929053d27b5c561ac1d0 (patch) | |
| tree | 0df79edfa5e98f4bbeab6b0669a6155e9033a2fb /tcl/target | |
| parent | 7abb93aad4039f88427e1179660c0ee68146e6d4 (diff) | |
| download | riscv-openocd-d14fef8495e6d0247ea2929053d27b5c561ac1d0.zip riscv-openocd-d14fef8495e6d0247ea2929053d27b5c561ac1d0.tar.gz riscv-openocd-d14fef8495e6d0247ea2929053d27b5c561ac1d0.tar.bz2 | |
tcl/target/ti_k3: Introduce RTOS array variable to set various CPU RTOSes
The Texas Instruments' K3 devices are a mix of AMP and SMP systems.
The operating systems used on these processors can vary dramatically
as well. Introduce a RTOS array variable, which is keyed off the cpu
to identify which RTOS is used on that CPU. This can be "auto" or
"hwthread" in case of SMP debug etc.
For example:
AM625 with an general purpose M4F running Zephyr and 4 A53s running SMP
Linux could be invoked by:
openocd -c 'set V8_SMP_DEBUG 1' -c 'set RTOS(am625.cpu.gp_mcu) Zephyr' \
-c "set RTOS(am625.cpu.a53.0) hwthread" -f board/ti_am625evm.cfg
Change-Id: Ib5e59fa2583b3115e5799658afcdd0ee91935e82
Reported-by: Dubravko Srsan <dubravko.srsan@dolotron.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7898
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'tcl/target')
| -rw-r--r-- | tcl/target/ti_k3.cfg | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg index bd7496e..090f082 100644 --- a/tcl/target/ti_k3.cfg +++ b/tcl/target/ti_k3.cfg @@ -248,6 +248,13 @@ switch $_soc { } } +proc _get_rtos_type_for_cpu { target_name } { + if { [info exists ::RTOS($target_name)] } { + return $::RTOS($target_name) + } + return none +} + set _CHIPNAME $_soc swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version @@ -260,7 +267,10 @@ set _CTINAME $_CHIPNAME.cti # sysctrl is always present cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0] -target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine + +target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine \ + -rtos [_get_rtos_type_for_cpu $_TARGETNAME.sysctrl] + $_TARGETNAME.sysctrl configure -event reset-assert { } proc sysctrl_up {} { @@ -304,7 +314,8 @@ for { set _core 0 } { $_core < $_armv8_cores } { incr _core } { -baseaddr [lindex $ARMV8_CTIBASE $_core] target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap -coreid $_core \ - -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine + -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine \ + -rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_armv8_cpu_name.$_core] set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core" @@ -350,7 +361,8 @@ for { set _core 0 } { $_core < $_r5_cores } { incr _core } { # inactive core examination will fail - wait till startup of additional core target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \ - -dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine + -dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine \ + -rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_r5_name] $_TARGETNAME.$_r5_name configure -event gdb-attach { _cpu_no_smp_up @@ -368,7 +380,8 @@ proc r5_up { args } { if { $_gp_mcu_cores != 0 } { cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0] - target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine + target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine \ + -rtos [_get_rtos_type_for_cpu $_TARGETNAME.gp_mcu] $_TARGETNAME.gp_mcu configure -event reset-assert { } proc gp_mcu_up {} { |