diff options
| author | Tim Newsome <tim@sifive.com> | 2023-03-16 17:52:48 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2023-03-16 18:02:35 -0700 |
| commit | 868ebdd89ca75a73bffe335395aa1ed522dda660 (patch) | |
| tree | 95ead6f4982b85a6cc90d5832712523a8ee7b77a /tcl/target | |
| parent | 3387015af01f18cc350c4764fbd533068ed15f3d (diff) | |
| parent | 1293ddd65713d6551775b67169387622ada477c1 (diff) | |
| download | riscv-openocd-868ebdd89ca75a73bffe335395aa1ed522dda660.zip riscv-openocd-868ebdd89ca75a73bffe335395aa1ed522dda660.tar.gz riscv-openocd-868ebdd89ca75a73bffe335395aa1ed522dda660.tar.bz2 | |
Merge commit '1293ddd65713d6551775b67169387622ada477c1' into from_upstream
This includes
https://sourceforge.net/p/openocd/mailman/message/37710818/, which
should fix #814.
Conflicts:
.travis.yml
contrib/loaders/flash/stm32/stm32f1x.S
contrib/loaders/flash/stm32/stm32f2x.S
doc/openocd.texi
src/rtos/FreeRTOS.c
src/server/gdb_server.c
src/target/riscv/riscv-013.c
src/target/riscv/riscv.c
src/target/riscv/riscv.h
src/target/riscv/riscv_semihosting.c
tcl/target/esp_common.cfg
tcl/target/gd32vf103.cfg
tools/scripts/checkpatch.pl
Change-Id: I1986c13298ca0dafbe3aecaf1b0b35626525e4eb
Diffstat (limited to 'tcl/target')
287 files changed, 2497 insertions, 40 deletions
diff --git a/tcl/target/1986Be1T.cfg b/tcl/target/1986Be1T.cfg index b7c9d63..a3172cc 100644 --- a/tcl/target/1986Be1T.cfg +++ b/tcl/target/1986Be1T.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # 1986ВЕ1Т # http://milandr.ru/index.php?mact=Products,cntnt01,details,0&cntnt01productid=236&cntnt01returnid=68 diff --git a/tcl/target/K1879x61R.cfg b/tcl/target/K1879x61R.cfg index 0a8467f..8dd330d 100644 --- a/tcl/target/K1879x61R.cfg +++ b/tcl/target/K1879x61R.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # СБИС К1879ХБ1Я # http://www.module.ru/catalog/micro/mikroshema_dekodera_cifrovogo_televizionnogo_signala_sbis_k1879hb1ya/ diff --git a/tcl/target/adsp-sc58x.cfg b/tcl/target/adsp-sc58x.cfg index 6073bb2..3dcfc91 100644 --- a/tcl/target/adsp-sc58x.cfg +++ b/tcl/target/adsp-sc58x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Analog Devices ADSP-SC58x (ARM Cortex-A5 plus one or two SHARC+ DSPs) # diff --git a/tcl/target/aduc702x.cfg b/tcl/target/aduc702x.cfg index 9c756be..c903710 100644 --- a/tcl/target/aduc702x.cfg +++ b/tcl/target/aduc702x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { diff --git a/tcl/target/aducm360.cfg b/tcl/target/aducm360.cfg index b381728..5cfb483 100644 --- a/tcl/target/aducm360.cfg +++ b/tcl/target/aducm360.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # This file was created using as references the stm32f1x.cfg and aduc702x.cfg # diff --git a/tcl/target/allwinner_v3s.cfg b/tcl/target/allwinner_v3s.cfg index d8d78bd..437bd95 100644 --- a/tcl/target/allwinner_v3s.cfg +++ b/tcl/target/allwinner_v3s.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # This is the config for an Allwinner V3/V3s (sun8iw8). # # Notes: diff --git a/tcl/target/alphascale_asm9260t.cfg b/tcl/target/alphascale_asm9260t.cfg index 7892ea2..735555e 100644 --- a/tcl/target/alphascale_asm9260t.cfg +++ b/tcl/target/alphascale_asm9260t.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + if { [info exists CHIPNAME] } { set _CHIPNAME $_CHIPNAME } else { diff --git a/tcl/target/altera_fpgasoc.cfg b/tcl/target/altera_fpgasoc.cfg index 0fc8d67..a98b346 100644 --- a/tcl/target/altera_fpgasoc.cfg +++ b/tcl/target/altera_fpgasoc.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Altera cyclone V SoC family, 5Cxxx # diff --git a/tcl/target/altera_fpgasoc_arria10.cfg b/tcl/target/altera_fpgasoc_arria10.cfg index c9c5ab6..fe58379 100644 --- a/tcl/target/altera_fpgasoc_arria10.cfg +++ b/tcl/target/altera_fpgasoc_arria10.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Intel (Altera) Arria10 FPGA SoC if { [info exists CHIPNAME] } { diff --git a/tcl/target/am335x.cfg b/tcl/target/am335x.cfg index cb3e06c..208ebf5 100644 --- a/tcl/target/am335x.cfg +++ b/tcl/target/am335x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + source [find target/icepick.cfg] if { [info exists CHIPNAME] } { diff --git a/tcl/target/am437x.cfg b/tcl/target/am437x.cfg index e954fd2..5350927 100644 --- a/tcl/target/am437x.cfg +++ b/tcl/target/am437x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + source [find target/icepick.cfg] source [find mem_helper.tcl] diff --git a/tcl/target/amdm37x.cfg b/tcl/target/amdm37x.cfg index 3db24b4..d9adae9 100644 --- a/tcl/target/amdm37x.cfg +++ b/tcl/target/amdm37x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Copyright (C) 2010-2011 by Karl Kurbjun # Copyright (C) 2009-2011 by Øyvind Harboe diff --git a/tcl/target/ampere_emag.cfg b/tcl/target/ampere_emag.cfg index 2e828de..0b0bd9e 100644 --- a/tcl/target/ampere_emag.cfg +++ b/tcl/target/ampere_emag.cfg @@ -1,22 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # OpenOCD Target Configuration for eMAG ARMv8 Processor # # Copyright (c) 2019-2021, Ampere Computing LLC # -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; -# -# # # Configure defaults for target diff --git a/tcl/target/ampere_qs_mq.cfg b/tcl/target/ampere_qs_mq.cfg new file mode 100644 index 0000000..0e83766 --- /dev/null +++ b/tcl/target/ampere_qs_mq.cfg @@ -0,0 +1,333 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# OpenOCD Target Configuration for Ampere Altra ("Quicksilver") and +# Ampere Altra Max ("Mystique") processors +# +# Copyright (c) 2019-2022, Ampere Computing LLC + +# Command Line Argument Description +# +# SPLITSMP +# Only used for dual socket systems. Do not use for a single socket setup. +# Option pertains to the ARMv8 target core naming in a dual socket setup. +# If specified, name all ARMv8 cores per socket as individual SMP sessions. +# If not specified, name ARMv8 cores from both sockets as one SMP session. +# This option is used in conjunction with the SMP_STR board file option. +# Syntax: -c "set SPLITSMP {}" +# +# PHYS_IDX +# Enable OpenOCD ARMv8 core target physical indexing. +# If not specified, defaults to OpenOCD ARMv8 core target logical indexing. +# Syntax: -c "set PHYS_IDX {}" +# +# CHIPNAME +# Specifies the name of the chip. +# Will typically be either qs, qs0, qs1, mq, mq0 or mq1. +# If not specified, defaults to qs. +# Syntax: -c "set CHIPNAME {qs}" +# +# SYSNAME +# Specifies the name of the system. +# Will typically be either qs or mq. +# If not specified, defaults to qs. +# Syntax: -c "set SYSNAME {qs}" +# +# Life-Cycle State (LCS) +# If not specified, defaults to "Secure LCS". +# LCS=0, "Secure LCS" +# LCS=1, "Chip Manufacturing LCS" +# Syntax: -c "set LCS {0}" +# Syntax: -c "set LCS {1}" +# +# CORELIST +# Specify available physical cores by number. +# Example syntax to connect to physical cores 16 and 17. +# Syntax: -c "set CORELIST {16 17}" +# +# COREMASK_LO +# Specify available physical cores 0-63 by mask. +# Example syntax to connect to physical cores 16 and 17. +# Syntax: -c "set COREMASK_LO {0x0000000000030000}" +# +# COREMASK_HI +# Specify available physical cores 64 and above by mask. +# Example syntax to connect to physical cores 94 and 95. +# Syntax: -c "set COREMASK_HI {0x00000000C0000000}" +# +# ARMV8_TAPID +# Can override the ARMV8 TAPID default value if necessary. +# Experimental Use. Most users will not use this option. +# Syntax: -c "set ARMV8_TAPID {0x3BA06477}" +# +# SMPMPRO_TAPID +# Can override the SMPMPRO TAPID default value if necessary. +# Experimental Use. Most users will not use this option. +# Syntax: -c "set SMPMPRO_TAPID {0x4BA00477}" +# +# +# Board File Argument Description +# These optional arguments are defined in the board file and +# referenced by the target file. See the corresponding board +# files for examples of their use. +# +# SMP_STR +# This option is used primarily for a dual socket system and it is not +# recommended for a single socket setup. This option configures whether +# the SMP ARMv8 core grouping is maintained at the board or target cfg level. +# Specify the option if the SMP core grouping is defined at the board level. +# Do not specify if the SMP core grouping is defined at the chip level. +# If not specified, defaults to SMP core grouping defined per socket. +# If specified, "SMP_STR=target smp", the SMP core grouping is maintained +# at the board cfg level. +# Used in conjunction with the SPLITSMP option to group two chips into +# a single SMP configuration or maintain as two separate SMP sessions. +# +# CORE_INDEX_OFFSET +# Specifies the starting logical core index value. +# Used for dual-socket systems. +# For socket #0, set to 0. +# For socket #1, set the starting logical core based from +# the last logical core on socket #0. +# If not specified, defaults to 0. +# + +# +# Configure defaults for target. +# Can be overridden in board configuration file. +# + +if { [info exists SMP_STR] } { + # SMP configured at the dual socket board level + set _SMP_STR $SMP_STR +} else { + # SMP configured at the single socket target level + set _SMP_STR "target smp" +} + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME qs +} + +if { [info exists SYSNAME] } { + set _SYSNAME $SYSNAME +} else { + set _SYSNAME qs +} + +if { [info exists CORE_INDEX_OFFSET] } { + set _CORE_INDEX_OFFSET $CORE_INDEX_OFFSET +} else { + set _CORE_INDEX_OFFSET 0 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists ARMV8_TAPID] } { + set _ARMV8_TAPID $ARMV8_TAPID +} else { + if { [info exists MQ_ENABLE] } { + # Configure for Mystique + set _ARMV8_TAPID 0x3BA06477 + set _MAX_CORE 128 + } else { + # Configure for Quicksilver + set _ARMV8_TAPID 0x2BA06477 + set _MAX_CORE 80 + } +} + +if { [info exists SMPMPRO_TAPID] } { + set _SMPMPRO_TAPID $SMPMPRO_TAPID +} else { + set _SMPMPRO_TAPID 0x4BA00477 +} + +if { [info exists CORELIST] } { + set _CORELIST $CORELIST +} else { + if { [info exists COREMASK_LO] } { + set _COREMASK_LO $COREMASK_LO + } else { + set _COREMASK_LO 0x0 + } + + if { [info exists COREMASK_HI] } { + set _COREMASK_HI $COREMASK_HI + } else { + set _COREMASK_HI 0x0 + } + + set _CORELIST {} + + set _MASK 0x1 + for {set i 0} {$i < 64} {incr i} { + if { [expr {$_COREMASK_LO & $_MASK}] != 0x0 } { + set _CORELIST "$_CORELIST $i" + } + set _MASK [expr {$_MASK << 0x1}] + } + + set _MASK 0x1 + for {} {$i < $_MAX_CORE} {incr i} { + if { [expr {$_COREMASK_HI & $_MASK}] != 0x0 } { + set _CORELIST "$_CORELIST $i" + } + set _MASK [expr {$_MASK << 0x1}] + } +} + +# +# Definition of target names +# +set _TARGETNAME_PMPRO pmpro +set _TARGETNAME_SMPRO smpro +set _TARGETNAME_ARMV8 armv8 + +# +# Configure JTAG TAPs - TAP chain declaration order is important +# + +jtag newtap $_CHIPNAME pmpro.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_SMPMPRO_TAPID +set _TAPNAME_PMPRO $_CHIPNAME.$_TARGETNAME_PMPRO.tap + +jtag newtap $_CHIPNAME smpro.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_SMPMPRO_TAPID +set _TAPNAME_SMPRO $_CHIPNAME.$_TARGETNAME_SMPRO.tap + +jtag newtap $_CHIPNAME armv8.tap -irlen 4 -ircapture 0x1 -irmask 0x3 -expected-id $_ARMV8_TAPID +set _TAPNAME_ARMV8 $_CHIPNAME.$_TARGETNAME_ARMV8.tap + +set _DAPNAME_PMPRO $_CHIPNAME.$_TARGETNAME_PMPRO.dap +set _DAPNAME_SMPRO $_CHIPNAME.$_TARGETNAME_SMPRO.dap +set _DAPNAME_ARMV8 $_CHIPNAME.$_TARGETNAME_ARMV8.dap + +set _AP_PMPRO_AHB 0 +set _AP_SMPRO_AHB 0 +set _AP_ARMV8_APB 0x00010000 +set _AP_ARMV8_AXI 0x00020000 + +# +# Configure JTAG DAPs +# + +dap create $_DAPNAME_PMPRO -chain-position $_TAPNAME_PMPRO -adiv5 +dap create $_DAPNAME_SMPRO -chain-position $_TAPNAME_SMPRO -adiv5 +dap create $_DAPNAME_ARMV8 -chain-position $_TAPNAME_ARMV8 -adiv6 + +if { [info exists LCS] && [expr {"$LCS"!="0"}] } { + # + # Create the DAP AHB-AP MEM-AP target for the PMPRO CPU + # + + target create $_CHIPNAME.$_TARGETNAME_PMPRO.ahb mem_ap -endian $_ENDIAN -dap $_DAPNAME_PMPRO -ap-num $_AP_PMPRO_AHB + + # + # Configure target PMPRO CPU + # + + target create $_CHIPNAME.$_TARGETNAME_PMPRO cortex_m -endian $_ENDIAN -dap $_DAPNAME_PMPRO -ap-num $_AP_PMPRO_AHB + + # + # Create the DAP AHB-AP MEM-AP target for the SMPRO CPU + # + + target create $_CHIPNAME.$_TARGETNAME_SMPRO.ahb mem_ap -endian $_ENDIAN -dap $_DAPNAME_SMPRO -ap-num $_AP_SMPRO_AHB + + # + # Configure target SMPRO CPU + # + + target create $_CHIPNAME.$_TARGETNAME_SMPRO cortex_m -endian $_ENDIAN -dap $_DAPNAME_SMPRO -ap-num $_AP_SMPRO_AHB +} + +# Create the DAP APB-AP MEM-AP target for the ARMV8 cores +target create $_CHIPNAME.$_TARGETNAME_ARMV8.apb mem_ap -endian $_ENDIAN -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB + +# Create the DAP AXI-AP MEM-AP target for the ARMV8 cores +target create $_CHIPNAME.$_TARGETNAME_ARMV8.axi mem_ap -endian $_ENDIAN -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_AXI + +# Set CSW register value default correctly for AXI accessible device memory: +# Select the correct Access Port Number +$_DAPNAME_ARMV8 apsel $_AP_ARMV8_AXI +# First set the CSW to OpenOCD's internal default +$_DAPNAME_ARMV8 apcsw default +# Set Domain[1:0]=b'11 (CSW[14:13]=b'11) +# Set Cache[3:0]=b'0000 (CSW[27:24]=b'0000) +# Porter Cfg registers require secure access, AxPROT[1] (CSW[29]) must be b'0'. +# Set AxPROT[2:0]=b'000 (CSW[30:28]=b'000) for an Unpriveleged, Secure, Data access. +$_DAPNAME_ARMV8 apcsw 0x00006000 0x7F006000 + +# +# Configure target CPUs +# + +set logical_index $_CORE_INDEX_OFFSET + +foreach physical_index $_CORELIST { + if { [info exists PHYS_IDX] } { + set logical_index [expr {$physical_index + $_CORE_INDEX_OFFSET}] + } + + # Format a string to reference which CPU target to use + if { [info exists SPLITSMP] } { + eval "set _TARGETNAME $_CHIPNAME.${_TARGETNAME_ARMV8}_$logical_index" + } else { + eval "set _TARGETNAME $_SYSNAME.${_TARGETNAME_ARMV8}_$logical_index" + } + + # Create and configure Cross Trigger Interface (CTI) - required for halt and resume + set _CTINAME $_TARGETNAME.cti + set _offset [expr {(0x00100000 * $physical_index) + (0x00200000 * ($physical_index>>1))}] + cti create $_CTINAME -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB -baseaddr [expr {0xA0220000 + $_offset}] + + # Create the target + target create $_TARGETNAME aarch64 -endian $_ENDIAN \ + -dap $_DAPNAME_ARMV8 -ap-num $_AP_ARMV8_APB -dbgbase [expr {0xA0210000 + $_offset}] \ + -rtos hwthread -cti $_CTINAME -coreid $logical_index + + # Build string used to enable SMP mode for the ARMv8 CPU cores + set _SMP_STR "$_SMP_STR $_TARGETNAME" + + # Clear CTI output/input enables that are not configured by OpenOCD for aarch64 + $_TARGETNAME configure -event reset-init [subst { + $_CTINAME write INEN0 0x00000000 + $_CTINAME write INEN1 0x00000000 + $_CTINAME write INEN2 0x00000000 + $_CTINAME write INEN3 0x00000000 + $_CTINAME write INEN4 0x00000000 + $_CTINAME write INEN5 0x00000000 + $_CTINAME write INEN6 0x00000000 + $_CTINAME write INEN7 0x00000000 + $_CTINAME write INEN8 0x00000000 + + $_CTINAME write OUTEN0 0x00000000 + $_CTINAME write OUTEN1 0x00000000 + $_CTINAME write OUTEN2 0x00000000 + $_CTINAME write OUTEN3 0x00000000 + $_CTINAME write OUTEN4 0x00000000 + $_CTINAME write OUTEN5 0x00000000 + $_CTINAME write OUTEN6 0x00000000 + $_CTINAME write OUTEN7 0x00000000 + $_CTINAME write OUTEN8 0x00000000 + }] + + incr logical_index +} + +if { [info exists SMP_STR] } { + # Return updated SMP configuration string back to board level + set SMP_STR $_SMP_STR +} else { + # For single socket per SMP configuration, evaluate the string + eval $_SMP_STR +} + +if { [info exists CORE_INDEX_OFFSET] } { + # For multi-socket, return total number of cores back to board level + set CORE_INDEX_OFFSET $logical_index +} diff --git a/tcl/target/ar71xx.cfg b/tcl/target/ar71xx.cfg index 57833f4..792b68f 100644 --- a/tcl/target/ar71xx.cfg +++ b/tcl/target/ar71xx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Atheros AR71xx MIPS 24Kc SoC. # tested on PB44 refererence board diff --git a/tcl/target/arm_corelink_sse200.cfg b/tcl/target/arm_corelink_sse200.cfg index ca30649..7327d05 100644 --- a/tcl/target/arm_corelink_sse200.cfg +++ b/tcl/target/arm_corelink_sse200.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Configuration script for Arm CoreLink SSE-200 Subsystem based IoT SoCs. # diff --git a/tcl/target/armada370.cfg b/tcl/target/armada370.cfg index 7165274..ccf4b36 100644 --- a/tcl/target/armada370.cfg +++ b/tcl/target/armada370.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # armada370 -- support for the Marvell Armada/370 CPU family # diff --git a/tcl/target/at32ap7000.cfg b/tcl/target/at32ap7000.cfg index 8573aa1..bbae247 100644 --- a/tcl/target/at32ap7000.cfg +++ b/tcl/target/at32ap7000.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Atmel AT32AP7000 # # This is the only core in the now-inactive high end AVR32 product line, diff --git a/tcl/target/at91r40008.cfg b/tcl/target/at91r40008.cfg index 912bd0e..66d32ae 100644 --- a/tcl/target/at91r40008.cfg +++ b/tcl/target/at91r40008.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # AT91R40008 target configuration file # TRST is tied to SRST on the AT91X40 family. diff --git a/tcl/target/at91rm9200.cfg b/tcl/target/at91rm9200.cfg index 3d9a8d9..1bc1287 100644 --- a/tcl/target/at91rm9200.cfg +++ b/tcl/target/at91rm9200.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Atmel AT91rm9200 # http://atmel.com/products/at91/ diff --git a/tcl/target/at91sam3XXX.cfg b/tcl/target/at91sam3XXX.cfg index 7d01ccd..ba1c3c5 100644 --- a/tcl/target/at91sam3XXX.cfg +++ b/tcl/target/at91sam3XXX.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for ATMEL sam3, a Cortex-M3 chip # # at91sam3u4e diff --git a/tcl/target/at91sam3ax_4x.cfg b/tcl/target/at91sam3ax_4x.cfg index 78ca79f..4e0cf79 100644 --- a/tcl/target/at91sam3ax_4x.cfg +++ b/tcl/target/at91sam3ax_4x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # common stuff source [find target/at91sam3ax_xx.cfg] diff --git a/tcl/target/at91sam3ax_8x.cfg b/tcl/target/at91sam3ax_8x.cfg index 2bb66fb..46d580d 100644 --- a/tcl/target/at91sam3ax_8x.cfg +++ b/tcl/target/at91sam3ax_8x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # common stuff source [find target/at91sam3ax_xx.cfg] diff --git a/tcl/target/at91sam3ax_xx.cfg b/tcl/target/at91sam3ax_xx.cfg index 5e01d66..7837f69 100644 --- a/tcl/target/at91sam3ax_xx.cfg +++ b/tcl/target/at91sam3ax_xx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for ATMEL sam3, a Cortex-M3 chip # # at91sam3A4C diff --git a/tcl/target/at91sam3nXX.cfg b/tcl/target/at91sam3nXX.cfg index 3450c26..9b20373 100644 --- a/tcl/target/at91sam3nXX.cfg +++ b/tcl/target/at91sam3nXX.cfg @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later # # Configuration for Atmel's SAM3N series diff --git a/tcl/target/at91sam3sXX.cfg b/tcl/target/at91sam3sXX.cfg index 09146bd..a2afda2 100644 --- a/tcl/target/at91sam3sXX.cfg +++ b/tcl/target/at91sam3sXX.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for ATMEL sam3, a Cortex-M3 chip # # at91sam3s4c diff --git a/tcl/target/at91sam3u1c.cfg b/tcl/target/at91sam3u1c.cfg index dc5c82c..b26662b 100644 --- a/tcl/target/at91sam3u1c.cfg +++ b/tcl/target/at91sam3u1c.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # common stuff source [find target/at91sam3uxx.cfg] diff --git a/tcl/target/at91sam3u1e.cfg b/tcl/target/at91sam3u1e.cfg index dc5c82c..b26662b 100644 --- a/tcl/target/at91sam3u1e.cfg +++ b/tcl/target/at91sam3u1e.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # common stuff source [find target/at91sam3uxx.cfg] diff --git a/tcl/target/at91sam3u2c.cfg b/tcl/target/at91sam3u2c.cfg index dc5c82c..b26662b 100644 --- a/tcl/target/at91sam3u2c.cfg +++ b/tcl/target/at91sam3u2c.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # common stuff source [find target/at91sam3uxx.cfg] diff --git a/tcl/target/at91sam3u2e.cfg b/tcl/target/at91sam3u2e.cfg index dc5c82c..b26662b 100644 --- a/tcl/target/at91sam3u2e.cfg +++ b/tcl/target/at91sam3u2e.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # common stuff source [find target/at91sam3uxx.cfg] diff --git a/tcl/target/at91sam3u4c.cfg b/tcl/target/at91sam3u4c.cfg index 14af008..fb1eeaa 100644 --- a/tcl/target/at91sam3u4c.cfg +++ b/tcl/target/at91sam3u4c.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # common stuff source [find target/at91sam3uxx.cfg] diff --git a/tcl/target/at91sam3u4e.cfg b/tcl/target/at91sam3u4e.cfg index fbe2dd9..1c75f82 100644 --- a/tcl/target/at91sam3u4e.cfg +++ b/tcl/target/at91sam3u4e.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # common stuff source [find target/at91sam3uxx.cfg] diff --git a/tcl/target/at91sam3uxx.cfg b/tcl/target/at91sam3uxx.cfg index 5b1748b..f084b9b 100644 --- a/tcl/target/at91sam3uxx.cfg +++ b/tcl/target/at91sam3uxx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for ATMEL sam3, a Cortex-M3 chip # # at91sam3u4e diff --git a/tcl/target/at91sam4XXX.cfg b/tcl/target/at91sam4XXX.cfg index ebb7eed..9c30ddf 100644 --- a/tcl/target/at91sam4XXX.cfg +++ b/tcl/target/at91sam4XXX.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # script for ATMEL sam4, a Cortex-M4 chip # diff --git a/tcl/target/at91sam4c32x.cfg b/tcl/target/at91sam4c32x.cfg index 5344e0c..ddcdd12 100644 --- a/tcl/target/at91sam4c32x.cfg +++ b/tcl/target/at91sam4c32x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for ATMEL sam4c32, a Cortex-M4 chip # diff --git a/tcl/target/at91sam4cXXX.cfg b/tcl/target/at91sam4cXXX.cfg index 3f10c61..a0206ad 100644 --- a/tcl/target/at91sam4cXXX.cfg +++ b/tcl/target/at91sam4cXXX.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for ATMEL sam4c, a Cortex-M4 chip # diff --git a/tcl/target/at91sam4lXX.cfg b/tcl/target/at91sam4lXX.cfg index b73babc..0910e30 100644 --- a/tcl/target/at91sam4lXX.cfg +++ b/tcl/target/at91sam4lXX.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for ATMEL sam4l, a Cortex-M4 chip # diff --git a/tcl/target/at91sam4sXX.cfg b/tcl/target/at91sam4sXX.cfg index 8883e23..2ceca00 100644 --- a/tcl/target/at91sam4sXX.cfg +++ b/tcl/target/at91sam4sXX.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for ATMEL sam4, a Cortex-M4 chip # diff --git a/tcl/target/at91sam4sd32x.cfg b/tcl/target/at91sam4sd32x.cfg index 077b1f5..24e25e3 100644 --- a/tcl/target/at91sam4sd32x.cfg +++ b/tcl/target/at91sam4sd32x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for ATMEL sam4sd32, a Cortex-M4 chip # diff --git a/tcl/target/at91sam7a2.cfg b/tcl/target/at91sam7a2.cfg index f7a0de2..f8090c7 100644 --- a/tcl/target/at91sam7a2.cfg +++ b/tcl/target/at91sam7a2.cfg @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME diff --git a/tcl/target/at91sam7se512.cfg b/tcl/target/at91sam7se512.cfg index 61b4781..2972494 100644 --- a/tcl/target/at91sam7se512.cfg +++ b/tcl/target/at91sam7se512.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # ATMEL sam7se512 # Example: the "Elektor Internet Radio" - EIR # http://www.ethernut.de/en/hardware/eir/index.html diff --git a/tcl/target/at91sam7sx.cfg b/tcl/target/at91sam7sx.cfg index a563ac0..fee4e9a 100644 --- a/tcl/target/at91sam7sx.cfg +++ b/tcl/target/at91sam7sx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + #use combined on interfaces or targets that can't set TRST/SRST separately reset_config srst_only srst_pulls_trst diff --git a/tcl/target/at91sam7x256.cfg b/tcl/target/at91sam7x256.cfg index e1a2435..2ebbf22 100644 --- a/tcl/target/at91sam7x256.cfg +++ b/tcl/target/at91sam7x256.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + #use combined on interfaces or targets that can't set TRST/SRST separately reset_config srst_only srst_pulls_trst diff --git a/tcl/target/at91sam7x512.cfg b/tcl/target/at91sam7x512.cfg index 6910e85..ccdcfa7 100644 --- a/tcl/target/at91sam7x512.cfg +++ b/tcl/target/at91sam7x512.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + #use combined on interfaces or targets that can't set TRST/SRST separately reset_config srst_only srst_pulls_trst diff --git a/tcl/target/at91sam9.cfg b/tcl/target/at91sam9.cfg index e0ea316..bc90d37 100644 --- a/tcl/target/at91sam9.cfg +++ b/tcl/target/at91sam9.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + ###################################### # Target: Atmel AT91SAM9 ###################################### diff --git a/tcl/target/at91sam9260.cfg b/tcl/target/at91sam9260.cfg index c5a07fd..3f74d96 100644 --- a/tcl/target/at91sam9260.cfg +++ b/tcl/target/at91sam9260.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + ###################################### # Target: Atmel AT91SAM9260 ###################################### diff --git a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg index 3e4b7d7..47117e9 100644 --- a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg +++ b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + ###################################### # Target: Atmel AT91SAM9260 ###################################### diff --git a/tcl/target/at91sam9261.cfg b/tcl/target/at91sam9261.cfg index 3ad1411..07456b2 100644 --- a/tcl/target/at91sam9261.cfg +++ b/tcl/target/at91sam9261.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + ###################################### # Target: Atmel AT91SAM9261 ###################################### diff --git a/tcl/target/at91sam9263.cfg b/tcl/target/at91sam9263.cfg index d2ee113..3e2585c 100644 --- a/tcl/target/at91sam9263.cfg +++ b/tcl/target/at91sam9263.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + ###################################### # Target: Atmel AT91SAM9263 ###################################### diff --git a/tcl/target/at91sam9g10.cfg b/tcl/target/at91sam9g10.cfg index b49f3d9..6836773 100644 --- a/tcl/target/at91sam9g10.cfg +++ b/tcl/target/at91sam9g10.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + ###################################### # Target: Atmel AT91SAM9G10 ###################################### diff --git a/tcl/target/at91sam9g20.cfg b/tcl/target/at91sam9g20.cfg index 6e45df2..4fc2048 100644 --- a/tcl/target/at91sam9g20.cfg +++ b/tcl/target/at91sam9g20.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + ###################################### # Target: Atmel AT91SAM9G20 ###################################### diff --git a/tcl/target/at91sam9g45.cfg b/tcl/target/at91sam9g45.cfg index 7323679..5e6e818 100644 --- a/tcl/target/at91sam9g45.cfg +++ b/tcl/target/at91sam9g45.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + ###################################### # Target: Atmel AT91SAM9G45 ###################################### diff --git a/tcl/target/at91sam9rl.cfg b/tcl/target/at91sam9rl.cfg index db05229..b253427 100644 --- a/tcl/target/at91sam9rl.cfg +++ b/tcl/target/at91sam9rl.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + ###################################### # Target: Atmel AT91SAM9RL ###################################### diff --git a/tcl/target/at91samdXX.cfg b/tcl/target/at91samdXX.cfg index 9a396fa..5132109 100644 --- a/tcl/target/at91samdXX.cfg +++ b/tcl/target/at91samdXX.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # script for Atmel SAMD, SAMR, SAML or SAMC, a Cortex-M0 chip # diff --git a/tcl/target/at91samg5x.cfg b/tcl/target/at91samg5x.cfg index 57274c0..cbe25f6 100644 --- a/tcl/target/at91samg5x.cfg +++ b/tcl/target/at91samg5x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for the ATMEL samg5x Cortex-M4F chip family # diff --git a/tcl/target/atheros_ar2313.cfg b/tcl/target/atheros_ar2313.cfg index 0966c6c..aa962b4 100644 --- a/tcl/target/atheros_ar2313.cfg +++ b/tcl/target/atheros_ar2313.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + if { [info exists CHIPNAME] } { set _CHIPNAME $_CHIPNAME } else { diff --git a/tcl/target/atheros_ar2315.cfg b/tcl/target/atheros_ar2315.cfg index 92ad376..3836763 100644 --- a/tcl/target/atheros_ar2315.cfg +++ b/tcl/target/atheros_ar2315.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + if { [info exists CHIPNAME] } { set _CHIPNAME $_CHIPNAME } else { diff --git a/tcl/target/atheros_ar9331.cfg b/tcl/target/atheros_ar9331.cfg index 6ab238c..931ac10 100644 --- a/tcl/target/atheros_ar9331.cfg +++ b/tcl/target/atheros_ar9331.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # The Atheros AR9331 is a highly integrated and cost effective # IEEE 802.11n 1x1 2.4 GHz System- on-a-Chip (SoC) for wireless # local area network (WLAN) AP and router platforms. diff --git a/tcl/target/atheros_ar9344.cfg b/tcl/target/atheros_ar9344.cfg index b698f25..d22bb5f 100644 --- a/tcl/target/atheros_ar9344.cfg +++ b/tcl/target/atheros_ar9344.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + if { [info exists CHIPNAME] } { set _CHIPNAME $_CHIPNAME } else { diff --git a/tcl/target/atmega128.cfg b/tcl/target/atmega128.cfg index 07161d5..c946919 100644 --- a/tcl/target/atmega128.cfg +++ b/tcl/target/atmega128.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # for avr set _CHIPNAME avr diff --git a/tcl/target/atmega128rfa1.cfg b/tcl/target/atmega128rfa1.cfg index cda439d..96a83fe 100644 --- a/tcl/target/atmega128rfa1.cfg +++ b/tcl/target/atmega128rfa1.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + set _CHIPNAME avr set _ENDIAN little diff --git a/tcl/target/atsame5x.cfg b/tcl/target/atsame5x.cfg index 351a2ca..5093d41 100644 --- a/tcl/target/atsame5x.cfg +++ b/tcl/target/atsame5x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Microchip (former Atmel) SAM E54, E53, E51 and D51 devices # with a Cortex-M4 core diff --git a/tcl/target/atsaml1x.cfg b/tcl/target/atsaml1x.cfg index 3486746..5a1b8f8 100644 --- a/tcl/target/atsaml1x.cfg +++ b/tcl/target/atsaml1x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Microchip (formerly Atmel) SAM L1x target # diff --git a/tcl/target/atsamv.cfg b/tcl/target/atsamv.cfg index fdd8354..7e9f6c5 100644 --- a/tcl/target/atsamv.cfg +++ b/tcl/target/atsamv.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # ATMEL SAMV, SAMS, and SAME chips are Cortex-M7 parts # The chips are very similar; the SAMV series just has # more peripherals and seems like the "flagship" of the diff --git a/tcl/target/avr32.cfg b/tcl/target/avr32.cfg index 8295f5e..e16d114 100644 --- a/tcl/target/avr32.cfg +++ b/tcl/target/avr32.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + set _CHIPNAME avr32 set _ENDIAN big diff --git a/tcl/target/bcm281xx.cfg b/tcl/target/bcm281xx.cfg index 0715d82..a70a9c5 100644 --- a/tcl/target/bcm281xx.cfg +++ b/tcl/target/bcm281xx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # BCM281xx if { [info exists CHIPNAME] } { diff --git a/tcl/target/bcm4706.cfg b/tcl/target/bcm4706.cfg index 10b32c7..e5d8d19 100644 --- a/tcl/target/bcm4706.cfg +++ b/tcl/target/bcm4706.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + set _CHIPNAME bcm4706 set _CPUID 0x1008c17f diff --git a/tcl/target/bcm4718.cfg b/tcl/target/bcm4718.cfg index 8193914..cc21a5e 100644 --- a/tcl/target/bcm4718.cfg +++ b/tcl/target/bcm4718.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + set _CHIPNAME bcm4718 set _LVTAPID 0x1471617f set _CPUID 0x0008c17f diff --git a/tcl/target/bcm47xx.cfg b/tcl/target/bcm47xx.cfg index 0132bb8..b5365e0 100644 --- a/tcl/target/bcm47xx.cfg +++ b/tcl/target/bcm47xx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + echo "Forcing reset_config to none to prevent OpenOCD from pulling SRST after the switch from LV is already performed" reset_config none diff --git a/tcl/target/bcm5352e.cfg b/tcl/target/bcm5352e.cfg index 3f0495a..084ce04 100644 --- a/tcl/target/bcm5352e.cfg +++ b/tcl/target/bcm5352e.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + set _CHIPNAME bcm5352e set _CPUID 0x0535217f diff --git a/tcl/target/bcm6348.cfg b/tcl/target/bcm6348.cfg index a9be559..b9d4448 100644 --- a/tcl/target/bcm6348.cfg +++ b/tcl/target/bcm6348.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + set _CHIPNAME bcm6348 set _CPUID 0x0634817f diff --git a/tcl/target/bluefield.cfg b/tcl/target/bluefield.cfg index dcebb2f..30ed527 100644 --- a/tcl/target/bluefield.cfg +++ b/tcl/target/bluefield.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # BlueField SoC Target set _CHIPNAME bluefield diff --git a/tcl/target/bluenrg-x.cfg b/tcl/target/bluenrg-x.cfg index 1eba376..afa1b51 100644 --- a/tcl/target/bluenrg-x.cfg +++ b/tcl/target/bluenrg-x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # bluenrg-1/2 and bluenrg-lp devices support only SWD transports. # diff --git a/tcl/target/c100.cfg b/tcl/target/c100.cfg index 5b4354e..c268ba3 100644 --- a/tcl/target/c100.cfg +++ b/tcl/target/c100.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # c100 config. # This is ARM1136 dual core # this script only configures one core (that is used to run Linux) diff --git a/tcl/target/c100config.tcl b/tcl/target/c100config.tcl index e937219..2545fa7 100644 --- a/tcl/target/c100config.tcl +++ b/tcl/target/c100config.tcl @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later # board(-config) specific parameters file. diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl index ecd7edf..d1d3f25 100644 --- a/tcl/target/c100helper.tcl +++ b/tcl/target/c100helper.tcl @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later proc helpC100 {} { echo "List of useful functions for C100 processor:" diff --git a/tcl/target/c100regs.tcl b/tcl/target/c100regs.tcl index 9304808..7be8939 100644 --- a/tcl/target/c100regs.tcl +++ b/tcl/target/c100regs.tcl @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Note that I basically converted # u-boot/include/asm-arm/arch/comcerto_100.h # defines diff --git a/tcl/target/cc2538.cfg b/tcl/target/cc2538.cfg index 8d232f4..e4fb02a 100644 --- a/tcl/target/cc2538.cfg +++ b/tcl/target/cc2538.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Config for Texas Instruments low power RF SoC CC2538 # http://www.ti.com/lit/pdf/swru319 diff --git a/tcl/target/cs351x.cfg b/tcl/target/cs351x.cfg index 8fabda6..e67540a 100644 --- a/tcl/target/cs351x.cfg +++ b/tcl/target/cs351x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg index 5ca54ae..54afb64 100644 --- a/tcl/target/davinci.cfg +++ b/tcl/target/davinci.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Utility code for DaVinci-family chips # diff --git a/tcl/target/dragonite.cfg b/tcl/target/dragonite.cfg index b9d73a2..249de25 100644 --- a/tcl/target/dragonite.cfg +++ b/tcl/target/dragonite.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + ###################################### # Target: Marvell Dragonite CPU core ###################################### diff --git a/tcl/target/dsp56321.cfg b/tcl/target/dsp56321.cfg index 78ecb3b..fac0ccc 100644 --- a/tcl/target/dsp56321.cfg +++ b/tcl/target/dsp56321.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Script for freescale DSP56321 # diff --git a/tcl/target/dsp568013.cfg b/tcl/target/dsp568013.cfg index 67d4419..5cf5c02 100644 --- a/tcl/target/dsp568013.cfg +++ b/tcl/target/dsp568013.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Script for freescale DSP568013 if { [info exists CHIPNAME] } { diff --git a/tcl/target/dsp568037.cfg b/tcl/target/dsp568037.cfg index fc57bd4..5d86811 100644 --- a/tcl/target/dsp568037.cfg +++ b/tcl/target/dsp568037.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Script for freescale DSP568037 if { [info exists CHIPNAME] } { diff --git a/tcl/target/efm32.cfg b/tcl/target/efm32.cfg index d2e4eb3..2187c0a 100644 --- a/tcl/target/efm32.cfg +++ b/tcl/target/efm32.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Silicon Labs (formerly Energy Micro) EFM32 target # diff --git a/tcl/target/em357.cfg b/tcl/target/em357.cfg index f39f3f4..ddefa28 100644 --- a/tcl/target/em357.cfg +++ b/tcl/target/em357.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Target configuration for the Silicon Labs EM357 chips # diff --git a/tcl/target/em358.cfg b/tcl/target/em358.cfg index 92e65a4..63f4088 100644 --- a/tcl/target/em358.cfg +++ b/tcl/target/em358.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Target configuration for the Silicon Labs EM358 chips # diff --git a/tcl/target/epc9301.cfg b/tcl/target/epc9301.cfg index 252bbab..41021d5 100644 --- a/tcl/target/epc9301.cfg +++ b/tcl/target/epc9301.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Cirrus Logic EP9301 processor on an Olimex CS-E9301 board. if { [info exists CHIPNAME] } { diff --git a/tcl/target/esi32xx.cfg b/tcl/target/esi32xx.cfg index 6be84ab..a8b0823 100644 --- a/tcl/target/esi32xx.cfg +++ b/tcl/target/esi32xx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # EnSilica eSi-32xx SoC (eSi-RISC Family) # http://www.ensilica.com/risc-ip/ diff --git a/tcl/target/esp32.cfg b/tcl/target/esp32.cfg new file mode 100644 index 0000000..f4c13aa --- /dev/null +++ b/tcl/target/esp32.cfg @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# The ESP32 only supports JTAG. +transport select jtag + +# Source the ESP common configuration file +source [find target/esp_common.cfg] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME esp32 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x120034e5 +} + +if { [info exists ESP32_ONLYCPU] } { + set _ONLYCPU $ESP32_ONLYCPU +} else { + set _ONLYCPU 2 +} + +if { [info exists ESP32_FLASH_VOLTAGE] } { + set _FLASH_VOLTAGE $ESP32_FLASH_VOLTAGE +} else { + set _FLASH_VOLTAGE 3.3 +} + +set _CPU0NAME cpu0 +set _CPU1NAME cpu1 +set _TARGETNAME_0 $_CHIPNAME.$_CPU0NAME +set _TARGETNAME_1 $_CHIPNAME.$_CPU1NAME + +jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 -expected-id $_CPUTAPID +if { $_ONLYCPU != 1 } { + jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -expected-id $_CPUTAPID +} else { + jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -disable -expected-id $_CPUTAPID +} + +# PRO-CPU +target create $_TARGETNAME_0 $_CHIPNAME -endian little -chain-position $_TARGETNAME_0 -coreid 0 +# APP-CPU +if { $_ONLYCPU != 1 } { + target create $_TARGETNAME_1 $_CHIPNAME -endian little -chain-position $_TARGETNAME_1 -coreid 1 + target smp $_TARGETNAME_0 $_TARGETNAME_1 +} + +$_TARGETNAME_0 esp32 flashbootstrap $_FLASH_VOLTAGE +$_TARGETNAME_0 xtensa maskisr on +$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut +$_TARGETNAME_0 configure -event reset-assert-post { soft_reset_halt } + +$_TARGETNAME_0 configure -event gdb-attach { + $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut + # necessary to auto-probe flash bank when GDB is connected + halt 1000 +} + +if { $_ONLYCPU != 1 } { + $_TARGETNAME_1 configure -event gdb-attach { + $_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut + # necessary to auto-probe flash bank when GDB is connected + halt 1000 + } + $_TARGETNAME_1 configure -event reset-assert-post { soft_reset_halt } +} + +$_TARGETNAME_0 configure -event examine-end { + # Need to enable to set 'semihosting_basedir' + arm semihosting enable + arm semihosting_resexit enable + if { [info exists _SEMIHOST_BASEDIR] } { + if { $_SEMIHOST_BASEDIR != "" } { + arm semihosting_basedir $_SEMIHOST_BASEDIR + } + } +} + +if { $_ONLYCPU != 1 } { + $_TARGETNAME_1 configure -event examine-end { + # Need to enable to set 'semihosting_basedir' + arm semihosting enable + arm semihosting_resexit enable + if { [info exists _SEMIHOST_BASEDIR] } { + if { $_SEMIHOST_BASEDIR != "" } { + arm semihosting_basedir $_SEMIHOST_BASEDIR + } + } + } +} + +gdb_breakpoint_override hard + +source [find target/xtensa-core-esp32.cfg] diff --git a/tcl/target/esp32s2.cfg b/tcl/target/esp32s2.cfg index ab64c31..e478a6d 100644 --- a/tcl/target/esp32s2.cfg +++ b/tcl/target/esp32s2.cfg @@ -3,6 +3,13 @@ # The ESP32-S2 only supports JTAG. transport select jtag +set CPU_MAX_ADDRESS 0xFFFFFFFF +source [find bitsbytes.tcl] +source [find memory.tcl] +source [find mmr_helpers.tcl] +# Source the ESP common configuration file +source [find target/esp_common.cfg] + if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { @@ -21,10 +28,53 @@ set _TAPNAME $_CHIPNAME.$_CPUNAME jtag newtap $_CHIPNAME $_CPUNAME -irlen 5 -expected-id $_CPUTAPID +proc esp32s2_memprot_is_enabled { } { + # IRAM0, DPORT_PMS_PRO_IRAM0_0_REG + if { [get_mmr_bit 0x3f4c1010 0] != 0 } { + return 1 + } + # DRAM0, DPORT_PMS_PRO_DRAM0_0_REG + if { [get_mmr_bit 0x3f4c1028 0] != 0 } { + return 1 + } + # PERI1, DPORT_PMS_PRO_DPORT_0_REG + if { [get_mmr_bit 0x3f4c103c 0] != 0 } { + return 1 + } + # PERI2, DPORT_PMS_PRO_AHB_0_REG + if { [get_mmr_bit 0x3f4c105c 0] != 0 } { + return 1 + } + return 0 +} + target create $_TARGETNAME esp32s2 -endian little -chain-position $_TAPNAME +$_TARGETNAME configure -event gdb-attach { + # necessary to auto-probe flash bank when GDB is connected and generate proper memory map + halt 1000 + if { [esp32s2_memprot_is_enabled] } { + # 'reset halt' to disable memory protection and allow flasher to work correctly + echo "Memory protection is enabled. Reset target to disable it..." + reset halt + } +} + xtensa maskisr on +$_TARGETNAME configure -event examine-end { + # Need to enable to set 'semihosting_basedir' + arm semihosting enable + arm semihosting_resexit enable + if { [info exists _SEMIHOST_BASEDIR] } { + if { $_SEMIHOST_BASEDIR != "" } { + arm semihosting_basedir $_SEMIHOST_BASEDIR + } + } +} + $_TARGETNAME configure -event reset-assert-post { soft_reset_halt } gdb_breakpoint_override hard + +source [find target/xtensa-core-esp32s2.cfg] diff --git a/tcl/target/esp32s3.cfg b/tcl/target/esp32s3.cfg new file mode 100644 index 0000000..42b2199 --- /dev/null +++ b/tcl/target/esp32s3.cfg @@ -0,0 +1,154 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# The ESP32-S3 only supports JTAG. +transport select jtag + +set CPU_MAX_ADDRESS 0xFFFFFFFF +source [find bitsbytes.tcl] +source [find memory.tcl] +source [find mmr_helpers.tcl] +# Source the ESP common configuration file +source [find target/esp_common.cfg] + + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME esp32s3 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x120034e5 +} + +if { [info exists ESP32_S3_ONLYCPU] } { + set _ONLYCPU $ESP32_S3_ONLYCPU +} else { + set _ONLYCPU 2 +} + +set _CPU0NAME cpu0 +set _CPU1NAME cpu1 +set _TARGETNAME_0 $_CHIPNAME.$_CPU0NAME +set _TARGETNAME_1 $_CHIPNAME.$_CPU1NAME + +jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 -expected-id $_CPUTAPID +if { $_ONLYCPU != 1 } { + jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -expected-id $_CPUTAPID +} else { + jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -disable -expected-id $_CPUTAPID +} + +proc esp32s3_memprot_is_enabled { } { + # SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG + if { [get_mmr_bit 0x600C10C0 0] != 0 } { + return 1 + } + # SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG + if { [get_mmr_bit 0x600C1124 0] != 0 } { + return 1 + } + # SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG + if { [get_mmr_bit 0x600C11D0 0] != 0 } { + return 1 + } + # IRAM0, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG + if { [get_mmr_bit 0x600C10D8 0] != 0 } { + return 1 + } + # DRAM0, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG + if { [get_mmr_bit 0x600C10FC 0] != 0 } { + return 1 + } + # SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG + if { [get_mmr_bit 0x600C10E4 0] != 0 } { + return 1 + } + # SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG + if { [get_mmr_bit 0x600C10F0 0] != 0 } { + return 1 + } + # SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG + if { [get_mmr_bit 0x600C1104 0] != 0 } { + return 1 + } + # SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG + if { [get_mmr_bit 0x600C1114 0] != 0 } { + return 1 + } + # SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG + if { [get_mmr_bit 0x600C119C 0] != 0 } { + return 1 + } + # SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG + if { [get_mmr_bit 0x600C1248 0] != 0 } { + return 1 + } + return 0 +} + +# PRO-CPU +target create $_TARGETNAME_0 $_CHIPNAME -endian little -chain-position $_TARGETNAME_0 -coreid 0 +# APP-CPU +if { $_ONLYCPU != 1 } { + target create $_TARGETNAME_1 $_CHIPNAME -endian little -chain-position $_TARGETNAME_1 -coreid 1 + target smp $_TARGETNAME_0 $_TARGETNAME_1 +} + +$_TARGETNAME_0 xtensa maskisr on +$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut +$_TARGETNAME_0 configure -event examine-end { + # Need to enable to set 'semihosting_basedir' + arm semihosting enable + arm semihosting_resexit enable + if { [info exists _SEMIHOST_BASEDIR] } { + if { $_SEMIHOST_BASEDIR != "" } { + arm semihosting_basedir $_SEMIHOST_BASEDIR + } + } +} + +if { $_ONLYCPU != 1 } { + $_TARGETNAME_1 configure -event examine-end { + # Need to enable to set 'semihosting_basedir' + arm semihosting enable + arm semihosting_resexit enable + if { [info exists _SEMIHOST_BASEDIR] } { + if { $_SEMIHOST_BASEDIR != "" } { + arm semihosting_basedir $_SEMIHOST_BASEDIR + } + } + } +} + +$_TARGETNAME_0 configure -event gdb-attach { + $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut + # necessary to auto-probe flash bank when GDB is connected and generate proper memory map + halt 1000 + if { [esp32s3_memprot_is_enabled] } { + # 'reset halt' to disable memory protection and allow flasher to work correctly + echo "Memory protection is enabled. Reset target to disable it..." + reset halt + } +} +$_TARGETNAME_0 configure -event reset-assert-post { soft_reset_halt } + +if { $_ONLYCPU != 1 } { + $_TARGETNAME_1 configure -event gdb-attach { + $_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut + # necessary to auto-probe flash bank when GDB is connected + halt 1000 + if { [esp32s3_memprot_is_enabled] } { + # 'reset halt' to disable memory protection and allow flasher to work correctly + echo "Memory protection is enabled. Reset target to disable it..." + reset halt + } + } + $_TARGETNAME_1 configure -event reset-assert-post { soft_reset_halt } +} + +gdb_breakpoint_override hard + +source [find target/xtensa-core-esp32s3.cfg] diff --git a/tcl/target/exynos5250.cfg b/tcl/target/exynos5250.cfg index d3aaa98..a565022 100644 --- a/tcl/target/exynos5250.cfg +++ b/tcl/target/exynos5250.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Samsung Exynos 5250 - dual-core ARM Cortex-A15 # diff --git a/tcl/target/faux.cfg b/tcl/target/faux.cfg index d3891cd..71cb8b7 100644 --- a/tcl/target/faux.cfg +++ b/tcl/target/faux.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + #Script for faux target - used for testing if { [info exists CHIPNAME] } { diff --git a/tcl/target/feroceon.cfg b/tcl/target/feroceon.cfg index d4f710e..593569d 100644 --- a/tcl/target/feroceon.cfg +++ b/tcl/target/feroceon.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + ###################################### # Target: Marvell Feroceon CPU core ###################################### diff --git a/tcl/target/fm3.cfg b/tcl/target/fm3.cfg index 544cff9..0caf629 100644 --- a/tcl/target/fm3.cfg +++ b/tcl/target/fm3.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # MB9BF506 # Fujitsu Cortex-M3 with 512kB Flash and 64kB RAM diff --git a/tcl/target/fm4.cfg b/tcl/target/fm4.cfg index bfe7115..4318f2e 100644 --- a/tcl/target/fm4.cfg +++ b/tcl/target/fm4.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Spansion FM4 (ARM Cortex-M4) # diff --git a/tcl/target/fm4_mb9bf.cfg b/tcl/target/fm4_mb9bf.cfg index ca4e5f9..4bc579c 100644 --- a/tcl/target/fm4_mb9bf.cfg +++ b/tcl/target/fm4_mb9bf.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Spansion FM4 MB9BFxxx (ARM Cortex-M4) # diff --git a/tcl/target/fm4_s6e2cc.cfg b/tcl/target/fm4_s6e2cc.cfg index c6f835d..7417d38 100644 --- a/tcl/target/fm4_s6e2cc.cfg +++ b/tcl/target/fm4_s6e2cc.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Spansion FM4 S6E2CC (ARM Cortex-M4) # diff --git a/tcl/target/gd32vf103.cfg b/tcl/target/gd32vf103.cfg index b00e5e9..6262697 100644 --- a/tcl/target/gd32vf103.cfg +++ b/tcl/target/gd32vf103.cfg @@ -1,4 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# GigaDevice GD32VF103 target +# +# https://www.gigadevice.com/products/microcontrollers/gd32/risc-v/ +# + adapter speed 1000 +source [find mem_helper.tcl] + transport select jtag reset_config srst_nogate diff --git a/tcl/target/gp326xxxa.cfg b/tcl/target/gp326xxxa.cfg index df42c44..447460b 100644 --- a/tcl/target/gp326xxxa.cfg +++ b/tcl/target/gp326xxxa.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Support for General Plus GP326XXXA chips # diff --git a/tcl/target/hi3798.cfg b/tcl/target/hi3798.cfg index 7b19218..4373962 100644 --- a/tcl/target/hi3798.cfg +++ b/tcl/target/hi3798.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Hisilicon Hi3798 Target if { [info exists CHIPNAME] } { diff --git a/tcl/target/hi6220.cfg b/tcl/target/hi6220.cfg index ddeeaad..f5f7fc9 100644 --- a/tcl/target/hi6220.cfg +++ b/tcl/target/hi6220.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Hisilicon Hi6220 Target if { [info exists CHIPNAME] } { diff --git a/tcl/target/hilscher_netx10.cfg b/tcl/target/hilscher_netx10.cfg index 668de8f..054cac8 100644 --- a/tcl/target/hilscher_netx10.cfg +++ b/tcl/target/hilscher_netx10.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + ################################################################################ # Author: Michael Trensch (MTrensch@googlemail.com) ################################################################################ diff --git a/tcl/target/hilscher_netx50.cfg b/tcl/target/hilscher_netx50.cfg index c6510c6..e8ba015 100644 --- a/tcl/target/hilscher_netx50.cfg +++ b/tcl/target/hilscher_netx50.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + ################################################################################ # Author: Michael Trensch (MTrensch@googlemail.com) ################################################################################ diff --git a/tcl/target/hilscher_netx500.cfg b/tcl/target/hilscher_netx500.cfg index 131bef2..d838a6b 100644 --- a/tcl/target/hilscher_netx500.cfg +++ b/tcl/target/hilscher_netx500.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + #Hilscher netX 500 CPU if { [info exists CHIPNAME] } { diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg index cc824ad..5509532 100644 --- a/tcl/target/icepick.cfg +++ b/tcl/target/icepick.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Copyright (C) 2011 by Karl Kurbjun # Copyright (C) 2009 by David Brownell diff --git a/tcl/target/imx.cfg b/tcl/target/imx.cfg index e2bee7a..d76f60e 100644 --- a/tcl/target/imx.cfg +++ b/tcl/target/imx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # utility fn's for Freescale i.MX series global TARGETNAME diff --git a/tcl/target/imx21.cfg b/tcl/target/imx21.cfg index 2d9ce39..7c9cca3 100644 --- a/tcl/target/imx21.cfg +++ b/tcl/target/imx21.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + #use combined on interfaces or targets that can't set TRST/SRST separately # # Hmmm.... should srst_pulls_trst be used here like i.MX27??? diff --git a/tcl/target/imx25.cfg b/tcl/target/imx25.cfg index bc91278..ed94cc0 100644 --- a/tcl/target/imx25.cfg +++ b/tcl/target/imx25.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # imx25 config # diff --git a/tcl/target/imx27.cfg b/tcl/target/imx27.cfg index e5a5035..c79d85e 100644 --- a/tcl/target/imx27.cfg +++ b/tcl/target/imx27.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # page 3-34 of "MCIMC27 Multimedia Applications Processor Reference Manual, Rev 0.3" # SRST pulls TRST # diff --git a/tcl/target/imx28.cfg b/tcl/target/imx28.cfg index 1fea3fa..d52fc4e 100644 --- a/tcl/target/imx28.cfg +++ b/tcl/target/imx28.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # i.MX28 config file. # based off of the imx21.cfg file. diff --git a/tcl/target/imx31.cfg b/tcl/target/imx31.cfg index d850657..10e9fef 100644 --- a/tcl/target/imx31.cfg +++ b/tcl/target/imx31.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # imx31 config # diff --git a/tcl/target/imx35.cfg b/tcl/target/imx35.cfg index 21495c2..fa173bb 100644 --- a/tcl/target/imx35.cfg +++ b/tcl/target/imx35.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # imx35 config # diff --git a/tcl/target/imx51.cfg b/tcl/target/imx51.cfg index 22af284..fc3dfa9 100644 --- a/tcl/target/imx51.cfg +++ b/tcl/target/imx51.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Freescale i.MX51 if { [info exists CHIPNAME] } { diff --git a/tcl/target/imx53.cfg b/tcl/target/imx53.cfg index 84a85ba..855a6ae 100644 --- a/tcl/target/imx53.cfg +++ b/tcl/target/imx53.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Freescale i.MX53 if { [info exists CHIPNAME] } { diff --git a/tcl/target/imx6.cfg b/tcl/target/imx6.cfg index 2945334..c9b6acf 100644 --- a/tcl/target/imx6.cfg +++ b/tcl/target/imx6.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Freescale i.MX6 series # diff --git a/tcl/target/imx6sx.cfg b/tcl/target/imx6sx.cfg index d3fae8a..3d4240a 100644 --- a/tcl/target/imx6sx.cfg +++ b/tcl/target/imx6sx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Freescale i.MX6SoloX # diff --git a/tcl/target/imx6ul.cfg b/tcl/target/imx6ul.cfg index f42aa63..354745e 100644 --- a/tcl/target/imx6ul.cfg +++ b/tcl/target/imx6ul.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Freescale i.MX6UltraLite series: 6UL 6ULL 6ULZ # diff --git a/tcl/target/imx7.cfg b/tcl/target/imx7.cfg index ea23deb..bd9e3dd 100644 --- a/tcl/target/imx7.cfg +++ b/tcl/target/imx7.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { diff --git a/tcl/target/imx7ulp.cfg b/tcl/target/imx7ulp.cfg index 879fcf8..1467f7c 100644 --- a/tcl/target/imx7ulp.cfg +++ b/tcl/target/imx7ulp.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # NXP i.MX7ULP: Cortex-A7 + Cortex-M4 # diff --git a/tcl/target/imx8m.cfg b/tcl/target/imx8m.cfg index 9a8bfec..6938090 100644 --- a/tcl/target/imx8m.cfg +++ b/tcl/target/imx8m.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # configuration file for NXP i.MX8M family of SoCs # @@ -38,13 +40,14 @@ for { set _core 0 } { $_core < $_cores } { incr _core } { -baseaddr [lindex $CTIBASE $_core] set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \ - -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core" + -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core" if { $_core != 0 } { # non-boot core examination may fail set _command "$_command -defer-examine" set _smp_command "$_smp_command $_TARGETNAME.$_core" } else { + set _command "$_command -rtos hwthread" set _smp_command "target smp $_TARGETNAME.$_core" } diff --git a/tcl/target/imx8qm.cfg b/tcl/target/imx8qm.cfg index 08cb813..33f9ca1 100644 --- a/tcl/target/imx8qm.cfg +++ b/tcl/target/imx8qm.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # NXP i.MX8QuadMax # diff --git a/tcl/target/infineon/tle987x.cfg b/tcl/target/infineon/tle987x.cfg index 84cc238..ac3db6c 100644 --- a/tcl/target/infineon/tle987x.cfg +++ b/tcl/target/infineon/tle987x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Infineon TLE987x family (Arm Cortex-M3 @ up to 40 MHz) # diff --git a/tcl/target/is5114.cfg b/tcl/target/is5114.cfg index 1a06b09..d0b1d92 100644 --- a/tcl/target/is5114.cfg +++ b/tcl/target/is5114.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for Insilica IS-5114 # AKA: Atmel AT76C114 - an ARM946 chip # ATMEL sold his product line to Insilica... diff --git a/tcl/target/ixp42x.cfg b/tcl/target/ixp42x.cfg index ee10b21..5c8e903 100644 --- a/tcl/target/ixp42x.cfg +++ b/tcl/target/ixp42x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + #xscale ixp42x CPU if { [info exists CHIPNAME] } { diff --git a/tcl/target/k1921vk01t.cfg b/tcl/target/k1921vk01t.cfg index 926f3c7..a9500ef 100644 --- a/tcl/target/k1921vk01t.cfg +++ b/tcl/target/k1921vk01t.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # K1921VK01T # http://niiet.ru/chips/nis?id=354 diff --git a/tcl/target/k40.cfg b/tcl/target/k40.cfg index 9811611..33e8235 100644 --- a/tcl/target/k40.cfg +++ b/tcl/target/k40.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Freescale Kinetis K40 devices # diff --git a/tcl/target/k60.cfg b/tcl/target/k60.cfg index b9c5e3a..3b89102 100644 --- a/tcl/target/k60.cfg +++ b/tcl/target/k60.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Freescale Kinetis K60 devices # diff --git a/tcl/target/ke0x.cfg b/tcl/target/ke0x.cfg index b92721f..b357767 100644 --- a/tcl/target/ke0x.cfg +++ b/tcl/target/ke0x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Freescale Kinetis KE0x and KEAx series devices # diff --git a/tcl/target/ke1xf.cfg b/tcl/target/ke1xf.cfg index b1200ce..86a1f3b 100644 --- a/tcl/target/ke1xf.cfg +++ b/tcl/target/ke1xf.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # NXP (Freescale) Kinetis KE1xF devices # diff --git a/tcl/target/ke1xz.cfg b/tcl/target/ke1xz.cfg index 6a3f509..9e91542 100644 --- a/tcl/target/ke1xz.cfg +++ b/tcl/target/ke1xz.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # NXP (Freescale) Kinetis KE1xZ devices # diff --git a/tcl/target/kl25.cfg b/tcl/target/kl25.cfg index 0e716e3..916edf6 100644 --- a/tcl/target/kl25.cfg +++ b/tcl/target/kl25.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Freescale Kinetis KL25 devices # diff --git a/tcl/target/kl46.cfg b/tcl/target/kl46.cfg index 70ea273..bf6b244 100644 --- a/tcl/target/kl46.cfg +++ b/tcl/target/kl46.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Freescale Kinetis KL46 devices # diff --git a/tcl/target/klx.cfg b/tcl/target/klx.cfg index 84f6535..cd236b3 100644 --- a/tcl/target/klx.cfg +++ b/tcl/target/klx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # NXP (former Freescale) Kinetis KL series devices # Also used for Cortex-M0+ equipped members of KVx and KE1xZ series diff --git a/tcl/target/ks869x.cfg b/tcl/target/ks869x.cfg index 78cc402..06e710b 100644 --- a/tcl/target/ks869x.cfg +++ b/tcl/target/ks869x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # ARM920T CPU if { [info exists CHIPNAME] } { diff --git a/tcl/target/kx.cfg b/tcl/target/kx.cfg index 9fda4ed..c87116b 100644 --- a/tcl/target/kx.cfg +++ b/tcl/target/kx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # NXP (former Freescale) Kinetis Kx series devices # Also used for Cortex-M4 equipped members of KVx and KE1xF series diff --git a/tcl/target/lpc11xx.cfg b/tcl/target/lpc11xx.cfg index 7a65c1f..d288e2a 100644 --- a/tcl/target/lpc11xx.cfg +++ b/tcl/target/lpc11xx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # NXP LPC11xx Cortex-M0 with at least 1kB SRAM set CHIPNAME lpc11xx set CHIPSERIES lpc1100 diff --git a/tcl/target/lpc12xx.cfg b/tcl/target/lpc12xx.cfg index a37c6fe..ace5e06 100644 --- a/tcl/target/lpc12xx.cfg +++ b/tcl/target/lpc12xx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # NXP LPC12xx Cortex-M0 with at least 4kB SRAM set CHIPNAME lpc12xx set CHIPSERIES lpc1200 diff --git a/tcl/target/lpc13xx.cfg b/tcl/target/lpc13xx.cfg index 3d128c9..5ac29d3 100644 --- a/tcl/target/lpc13xx.cfg +++ b/tcl/target/lpc13xx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # NXP LPC13xx Cortex-M3 with at least 4kB SRAM set CHIPNAME lpc13xx set CHIPSERIES lpc1300 diff --git a/tcl/target/lpc17xx.cfg b/tcl/target/lpc17xx.cfg index dccf880..35d8bad 100644 --- a/tcl/target/lpc17xx.cfg +++ b/tcl/target/lpc17xx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # NXP LPC17xx Cortex-M3 with at least 8kB SRAM set CHIPNAME lpc17xx set CHIPSERIES lpc1700 diff --git a/tcl/target/lpc1850.cfg b/tcl/target/lpc1850.cfg index 481dc8a..6dd1ab7 100644 --- a/tcl/target/lpc1850.cfg +++ b/tcl/target/lpc1850.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + source [find target/swj-dp.tcl] adapter speed 500 diff --git a/tcl/target/lpc1xxx.cfg b/tcl/target/lpc1xxx.cfg index 946d1ce..70d26d2 100644 --- a/tcl/target/lpc1xxx.cfg +++ b/tcl/target/lpc1xxx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Main file for NXP LPC1xxx/LPC40xx series Cortex-M0/0+/3/4F parts # # !!!!!! diff --git a/tcl/target/lpc2103.cfg b/tcl/target/lpc2103.cfg index 131b9ef..c49b0e5 100644 --- a/tcl/target/lpc2103.cfg +++ b/tcl/target/lpc2103.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # NXP LPC2103 ARM7TDMI-S with 32kB flash and 8kB SRAM, clocked with 12MHz crystal source [find target/lpc2xxx.cfg] diff --git a/tcl/target/lpc2124.cfg b/tcl/target/lpc2124.cfg index ddbde22..053ebeb 100644 --- a/tcl/target/lpc2124.cfg +++ b/tcl/target/lpc2124.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # NXP LPC2124 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal source [find target/lpc2xxx.cfg] diff --git a/tcl/target/lpc2129.cfg b/tcl/target/lpc2129.cfg index a1c3fe7..88ee20f 100644 --- a/tcl/target/lpc2129.cfg +++ b/tcl/target/lpc2129.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # NXP LPC2129 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal source [find target/lpc2xxx.cfg] diff --git a/tcl/target/lpc2148.cfg b/tcl/target/lpc2148.cfg index 503a682..fda622f 100644 --- a/tcl/target/lpc2148.cfg +++ b/tcl/target/lpc2148.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # NXP LPC2148 ARM7TDMI-S with 512kB flash (12kB used by bootloader) and 40kB SRAM (8kB for USB DMA), clocked with 12MHz crystal source [find target/lpc2xxx.cfg] diff --git a/tcl/target/lpc2294.cfg b/tcl/target/lpc2294.cfg index 1320cda..7537a65 100644 --- a/tcl/target/lpc2294.cfg +++ b/tcl/target/lpc2294.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # NXP LPC2294 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal source [find target/lpc2xxx.cfg] diff --git a/tcl/target/lpc2378.cfg b/tcl/target/lpc2378.cfg index 235456a..59e41c9 100644 --- a/tcl/target/lpc2378.cfg +++ b/tcl/target/lpc2378.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # NXP LPC2378 ARM7TDMI-S with 512kB flash (8kB used by bootloader) and 56kB SRAM (16kB for ETH, 8kB for DMA), clocked with 4MHz internal oscillator source [find target/lpc2xxx.cfg] diff --git a/tcl/target/lpc2460.cfg b/tcl/target/lpc2460.cfg index c229f6d..59b6466 100644 --- a/tcl/target/lpc2460.cfg +++ b/tcl/target/lpc2460.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # NXP LPC2460 ARM7TDMI-S with 98kB SRAM (16kB for ETH, 16kB for DMA, 2kB for RTC), clocked with 4MHz internal oscillator source [find target/lpc2xxx.cfg] diff --git a/tcl/target/lpc2478.cfg b/tcl/target/lpc2478.cfg index 36b5c46..e4fd49d 100644 --- a/tcl/target/lpc2478.cfg +++ b/tcl/target/lpc2478.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # NXP LPC2478 ARM7TDMI-S with 512kB flash (8kB used by bootloader) and 98kB SRAM (16kB for ETH, 16kB for DMA, 2kB for RTC), clocked with 4MHz internal oscillator source [find target/lpc2xxx.cfg] diff --git a/tcl/target/lpc2900.cfg b/tcl/target/lpc2900.cfg index 523bc21..67e3c92 100644 --- a/tcl/target/lpc2900.cfg +++ b/tcl/target/lpc2900.cfg @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME diff --git a/tcl/target/lpc2xxx.cfg b/tcl/target/lpc2xxx.cfg index f947c1b..bc5e600 100644 --- a/tcl/target/lpc2xxx.cfg +++ b/tcl/target/lpc2xxx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Common setup for the LPC2xxx parts # parameters: diff --git a/tcl/target/lpc3131.cfg b/tcl/target/lpc3131.cfg index 89bbf02..09d698a 100644 --- a/tcl/target/lpc3131.cfg +++ b/tcl/target/lpc3131.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + ###################################### # Target: NXP lpc3131 ###################################### diff --git a/tcl/target/lpc3250.cfg b/tcl/target/lpc3250.cfg index 14bb0f6..244d981 100644 --- a/tcl/target/lpc3250.cfg +++ b/tcl/target/lpc3250.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # lpc3250 config # diff --git a/tcl/target/lpc40xx.cfg b/tcl/target/lpc40xx.cfg index 606cda5..f0be5a1 100644 --- a/tcl/target/lpc40xx.cfg +++ b/tcl/target/lpc40xx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # NXP LPC40xx Cortex-M4F with at least 16kB SRAM set CHIPNAME lpc40xx set CHIPSERIES lpc4000 diff --git a/tcl/target/lpc4350.cfg b/tcl/target/lpc4350.cfg index 0c6d0ff..453306a 100644 --- a/tcl/target/lpc4350.cfg +++ b/tcl/target/lpc4350.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + source [find target/swj-dp.tcl] adapter speed 500 diff --git a/tcl/target/lpc4357.cfg b/tcl/target/lpc4357.cfg index 1a15ad6..f783505 100644 --- a/tcl/target/lpc4357.cfg +++ b/tcl/target/lpc4357.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # NXP LPC4357 # diff --git a/tcl/target/lpc4370.cfg b/tcl/target/lpc4370.cfg index 9db2b9e..fe9e76b 100644 --- a/tcl/target/lpc4370.cfg +++ b/tcl/target/lpc4370.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # NXP LPC4370 - 1x ARM Cortex-M4 + 2x ARM Cortex-M0 @ up to 204 MHz each # diff --git a/tcl/target/lpc84x.cfg b/tcl/target/lpc84x.cfg index cb36698..af26f27 100644 --- a/tcl/target/lpc84x.cfg +++ b/tcl/target/lpc84x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # NXP LPC84x Cortex-M0+ with at least 8kB SRAM if { ![info exists CHIPNAME] } { set CHIPNAME lpc84x diff --git a/tcl/target/lpc8nxx.cfg b/tcl/target/lpc8nxx.cfg index 4db78cb..859e99b 100644 --- a/tcl/target/lpc8nxx.cfg +++ b/tcl/target/lpc8nxx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # NXP LPC8Nxx NHS31xx Cortex-M0+ with 8kB SRAM # Copyright (C) 2018 by Jean-Christian de Rivaz # Based on NXP proposal https://community.nxp.com/message/1011149 diff --git a/tcl/target/lpc8xx.cfg b/tcl/target/lpc8xx.cfg index e0e210b..4c54a2a 100644 --- a/tcl/target/lpc8xx.cfg +++ b/tcl/target/lpc8xx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # NXP LPC8xx Cortex-M0+ with at least 1kB SRAM if { ![info exists CHIPNAME] } { set CHIPNAME lpc8xx diff --git a/tcl/target/ls1012a.cfg b/tcl/target/ls1012a.cfg index e1bd168..7333ea8 100644 --- a/tcl/target/ls1012a.cfg +++ b/tcl/target/ls1012a.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # NXP LS1012A # diff --git a/tcl/target/marvell/88f3710.cfg b/tcl/target/marvell/88f3710.cfg index 6e35f29..dcc4516 100644 --- a/tcl/target/marvell/88f3710.cfg +++ b/tcl/target/marvell/88f3710.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Marvell Armada 3710 set CORES 1 diff --git a/tcl/target/marvell/88f3720.cfg b/tcl/target/marvell/88f3720.cfg index 799d614..7c29378 100644 --- a/tcl/target/marvell/88f3720.cfg +++ b/tcl/target/marvell/88f3720.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Marvell Armada 3720 set CORES 2 diff --git a/tcl/target/marvell/88f37x0.cfg b/tcl/target/marvell/88f37x0.cfg index 5c3dd73..d80f4ef 100644 --- a/tcl/target/marvell/88f37x0.cfg +++ b/tcl/target/marvell/88f37x0.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Main file for Marvell Armada 3700 series targets # # !!!!!! diff --git a/tcl/target/max32620.cfg b/tcl/target/max32620.cfg index 6187bb9..9f0f492 100644 --- a/tcl/target/max32620.cfg +++ b/tcl/target/max32620.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Maxim Integrated MAX32620 OpenOCD target configuration file # www.maximintegrated.com diff --git a/tcl/target/max32625.cfg b/tcl/target/max32625.cfg index 159b360..35e1c3b 100644 --- a/tcl/target/max32625.cfg +++ b/tcl/target/max32625.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Maxim Integrated MAX32625 OpenOCD target configuration file # www.maximintegrated.com diff --git a/tcl/target/max3263x.cfg b/tcl/target/max3263x.cfg index fc7d11f..52a5a77 100644 --- a/tcl/target/max3263x.cfg +++ b/tcl/target/max3263x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Maxim Integrated MAX3263X OpenOCD target configuration file # www.maximintegrated.com diff --git a/tcl/target/mc13224v.cfg b/tcl/target/mc13224v.cfg index f756dd9..29e4d9d 100644 --- a/tcl/target/mc13224v.cfg +++ b/tcl/target/mc13224v.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + source [find bitsbytes.tcl] source [find cpu/arm/arm7tdmi.tcl] source [find memory.tcl] diff --git a/tcl/target/mdr32f9q2i.cfg b/tcl/target/mdr32f9q2i.cfg index 820d2dd..6e958c6 100644 --- a/tcl/target/mdr32f9q2i.cfg +++ b/tcl/target/mdr32f9q2i.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # MDR32F9Q2I (1986ВЕ92У) # http://milandr.ru/index.php?mact=Products,cntnt01,details,0&cntnt01productid=57&cntnt01returnid=68 diff --git a/tcl/target/nds32v2.cfg b/tcl/target/nds32v2.cfg index bbf6b3a..07814b7 100644 --- a/tcl/target/nds32v2.cfg +++ b/tcl/target/nds32v2.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Andes Core # diff --git a/tcl/target/nds32v3.cfg b/tcl/target/nds32v3.cfg index 0c267cd..0fd1369 100644 --- a/tcl/target/nds32v3.cfg +++ b/tcl/target/nds32v3.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Andes Core # diff --git a/tcl/target/nds32v3m.cfg b/tcl/target/nds32v3m.cfg index 169e3d1..29a2478 100644 --- a/tcl/target/nds32v3m.cfg +++ b/tcl/target/nds32v3m.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Andes Core # diff --git a/tcl/target/ngultra.cfg b/tcl/target/ngultra.cfg new file mode 100644 index 0000000..956fdbb --- /dev/null +++ b/tcl/target/ngultra.cfg @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright (C) 2022 by NanoXplore, France - all rights reserved +# +# configuration file for NG-Ultra SoC from NanoXplore. +# NG-Ultra is a quad-core Cortex-R52 SoC + an FPGA. +# +transport select jtag +adapter speed 10000 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME NGULTRA +} + +if { [info exists CHIPCORES] } { + set _cores $CHIPCORES +} else { + set _cores 4 +} + +set DBGBASE {0x88210000 0x88310000 0x88410000 0x88510000} +set CTIBASE {0x88220000 0x88320000 0x88420000 0x88520000} + +# Coresight access to the SoC +jtag newtap $_CHIPNAME.coresight cpu -irlen 4 -expected-id 0x6BA00477 + +# Misc TAP devices +jtag newtap $_CHIPNAME.soc cpu -irlen 7 -expected-id 0xFAAA0555 +jtag newtap $_CHIPNAME.pmb unknown1 -irlen 5 -expected-id 0xBA20A005 +jtag newtap $_CHIPNAME.fpga fpga -irlen 4 -ignore-version -ignore-bypass + +# Create the Coresight DAP +dap create $_CHIPNAME.coresight.dap -chain-position $_CHIPNAME.coresight.cpu + +for { set _core 0 } { $_core < $_cores } { incr _core } { + cti create cti.$_core -dap $_CHIPNAME.coresight.dap -ap-num 0 \ + -baseaddr [lindex $CTIBASE $_core] +# Cores are armv8-r but works with aarch64 (since armv8-r not directly supported by openocd yet). + if { $_core == 0} { + target create core.$_core aarch64 -dap $_CHIPNAME.coresight.dap \ + -ap-num 0 -dbgbase [lindex $DBGBASE $_core] -cti cti.$_core + } else { + target create core.$_core aarch64 -dap $_CHIPNAME.coresight.dap \ + -ap-num 0 -dbgbase [lindex $DBGBASE $_core] -cti cti.$_core -defer-examine + } +} + +# Create direct APB and AXI interfaces +target create APB mem_ap -dap $_CHIPNAME.coresight.dap -ap-num 0 +target create AXI mem_ap -dap $_CHIPNAME.coresight.dap -ap-num 1 diff --git a/tcl/target/nhs31xx.cfg b/tcl/target/nhs31xx.cfg index 964be7b..7e4bc4c 100644 --- a/tcl/target/nhs31xx.cfg +++ b/tcl/target/nhs31xx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # NXP NHS31xx Cortex-M0+ with 8kB SRAM set CHIPNAME nhs31xx diff --git a/tcl/target/nrf51.cfg b/tcl/target/nrf51.cfg index d51a50e..48c2715 100644 --- a/tcl/target/nrf51.cfg +++ b/tcl/target/nrf51.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # script for Nordic nRF51 series, a Cortex-M0 chip # diff --git a/tcl/target/nrf52.cfg b/tcl/target/nrf52.cfg index d0c52fd..2539be0 100644 --- a/tcl/target/nrf52.cfg +++ b/tcl/target/nrf52.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Nordic nRF52 series: ARM Cortex-M4 @ 64 MHz # diff --git a/tcl/target/nuc910.cfg b/tcl/target/nuc910.cfg index 29cd29f..31a3ac6 100644 --- a/tcl/target/nuc910.cfg +++ b/tcl/target/nuc910.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Nuvoton nuc910 (previously W90P910) based soc # diff --git a/tcl/target/numicro.cfg b/tcl/target/numicro.cfg index 73022df..29077f3 100644 --- a/tcl/target/numicro.cfg +++ b/tcl/target/numicro.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for Nuvoton MuMicro Cortex-M0 Series # Adapt based on what transport is active. diff --git a/tcl/target/omap2420.cfg b/tcl/target/omap2420.cfg index 7968ad1..3e31baf 100644 --- a/tcl/target/omap2420.cfg +++ b/tcl/target/omap2420.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Texas Instruments OMAP 2420 # http://www.ti.com/omap # as seen in Nokia N8x0 tablets diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg index dcf7c51..bd8b111 100644 --- a/tcl/target/omap3530.cfg +++ b/tcl/target/omap3530.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # TI OMAP3530 # http://focus.ti.com/docs/prod/folders/print/omap3530.html # Other OMAP3 chips remove DSP and/or the OpenGL support diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg index 5b9e23c..a448550 100644 --- a/tcl/target/omap4430.cfg +++ b/tcl/target/omap4430.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # OMAP4430 if { [info exists CHIPNAME] } { diff --git a/tcl/target/omap4460.cfg b/tcl/target/omap4460.cfg index fb76e13..bbc824b 100644 --- a/tcl/target/omap4460.cfg +++ b/tcl/target/omap4460.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # OMAP4460 if { [info exists CHIPNAME] } { diff --git a/tcl/target/omap5912.cfg b/tcl/target/omap5912.cfg index 2f9338b..783f460 100644 --- a/tcl/target/omap5912.cfg +++ b/tcl/target/omap5912.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # TI OMAP5912 dual core processor # http://focus.ti.com/docs/prod/folders/print/omap5912.html diff --git a/tcl/target/omapl138.cfg b/tcl/target/omapl138.cfg index 30cf23c..2d670b9 100644 --- a/tcl/target/omapl138.cfg +++ b/tcl/target/omapl138.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Texas Instruments DaVinci family: OMAPL138 # diff --git a/tcl/target/or1k.cfg b/tcl/target/or1k.cfg index f85c2ee..ddd4fa2 100644 --- a/tcl/target/or1k.cfg +++ b/tcl/target/or1k.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + set _ENDIAN big if { [info exists CHIPNAME] } { diff --git a/tcl/target/pic32mx.cfg b/tcl/target/pic32mx.cfg index f15924f..df68e80 100644 --- a/tcl/target/pic32mx.cfg +++ b/tcl/target/pic32mx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { diff --git a/tcl/target/psoc4.cfg b/tcl/target/psoc4.cfg index 40f2fca..baa2c83 100644 --- a/tcl/target/psoc4.cfg +++ b/tcl/target/psoc4.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for Cypress PSoC 4 devices # diff --git a/tcl/target/psoc5lp.cfg b/tcl/target/psoc5lp.cfg index c90fd42..fe44174 100644 --- a/tcl/target/psoc5lp.cfg +++ b/tcl/target/psoc5lp.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Cypress PSoC 5LP # diff --git a/tcl/target/psoc6.cfg b/tcl/target/psoc6.cfg index bf63fd5..d69515c 100644 --- a/tcl/target/psoc6.cfg +++ b/tcl/target/psoc6.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Configuration script for Cypress PSoC6 family of microcontrollers (CY8C6xxx) # PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg index 73518bf..14ee13c 100644 --- a/tcl/target/pxa255.cfg +++ b/tcl/target/pxa255.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # PXA255 chip ... originally from Intel, PXA line was sold to Marvell. # This chip is now at end-of-life. Final orders have been taken. diff --git a/tcl/target/pxa270.cfg b/tcl/target/pxa270.cfg index bd904b5..3121e96 100644 --- a/tcl/target/pxa270.cfg +++ b/tcl/target/pxa270.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + #Marvell/Intel PXA270 Script if { [info exists CHIPNAME] } { diff --git a/tcl/target/pxa3xx.cfg b/tcl/target/pxa3xx.cfg index 1a4539c..d670c84 100644 --- a/tcl/target/pxa3xx.cfg +++ b/tcl/target/pxa3xx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Marvell PXA3xx if { [info exists CHIPNAME] } { diff --git a/tcl/target/qualcomm_qca4531.cfg b/tcl/target/qualcomm_qca4531.cfg index 0b046b8..be0c8fa 100644 --- a/tcl/target/qualcomm_qca4531.cfg +++ b/tcl/target/qualcomm_qca4531.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # The QCA4531 is a two stream (2x2) 802.11b/g/n single-band programmable # Wi-Fi System-on-Chip (SoC) for the Internet of Things (IoT). # diff --git a/tcl/target/quark_d20xx.cfg b/tcl/target/quark_d20xx.cfg index 7d718c2..ca8f440 100644 --- a/tcl/target/quark_d20xx.cfg +++ b/tcl/target/quark_d20xx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + if { [info exists CPUTAPID] } { set _CPUTAPID $CPUTAPID } else { diff --git a/tcl/target/quark_x10xx.cfg b/tcl/target/quark_x10xx.cfg index a5bbfb4..6463f21 100644 --- a/tcl/target/quark_x10xx.cfg +++ b/tcl/target/quark_x10xx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { diff --git a/tcl/target/readme.txt b/tcl/target/readme.txt index 91bb2d5..deec5b5 100644 --- a/tcl/target/readme.txt +++ b/tcl/target/readme.txt @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + Prerequisites: The users of OpenOCD as well as computer programs interacting with OpenOCD are expecting that certain commands do the same thing across all the targets. diff --git a/tcl/target/renesas_r7s72100.cfg b/tcl/target/renesas_r7s72100.cfg index 5220b3c..dc9a1d8 100644 --- a/tcl/target/renesas_r7s72100.cfg +++ b/tcl/target/renesas_r7s72100.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Renesas RZ/A1H # https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rza/rza1h.html diff --git a/tcl/target/renesas_rcar_gen2.cfg b/tcl/target/renesas_rcar_gen2.cfg index e51b372..31ba156 100644 --- a/tcl/target/renesas_rcar_gen2.cfg +++ b/tcl/target/renesas_rcar_gen2.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Renesas R-Car Generation 2 SOCs # - There are a combination of Cortex-A15s and Cortex-A7s for each Gen2 SOC # - Each SOC can boot through any of the, up to 2, core types that it has diff --git a/tcl/target/renesas_rcar_gen3.cfg b/tcl/target/renesas_rcar_gen3.cfg index 334d255..3e44983 100644 --- a/tcl/target/renesas_rcar_gen3.cfg +++ b/tcl/target/renesas_rcar_gen3.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Renesas R-Car Generation 3 SOCs # - There are a combination of Cortex-A57s, Cortex-A53s, and Cortex-R7 for each Gen3 SOC # - Each SOC can boot through any of the, up to 3, core types that it has diff --git a/tcl/target/renesas_rcar_reset_common.cfg b/tcl/target/renesas_rcar_reset_common.cfg index 3e4579b..987f0c8 100644 --- a/tcl/target/renesas_rcar_reset_common.cfg +++ b/tcl/target/renesas_rcar_reset_common.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Renesas R-Car Gen2 Evaluation Board common settings reset_config trst_and_srst srst_nogate diff --git a/tcl/target/renesas_s7g2.cfg b/tcl/target/renesas_s7g2.cfg index b4be88f..fa9c579 100644 --- a/tcl/target/renesas_s7g2.cfg +++ b/tcl/target/renesas_s7g2.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Renesas Synergy S7 G2 w/ ARM Cortex-M4 @ 240 MHz # diff --git a/tcl/target/rk3308.cfg b/tcl/target/rk3308.cfg index 7f957da..b6086f1 100644 --- a/tcl/target/rk3308.cfg +++ b/tcl/target/rk3308.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Rockchip RK3308 Target # https://rockchip.fr/RK3308%20datasheet%20V1.5.pdf # https://dl.radxa.com/rockpis/docs/hw/datasheets/Rockchip%20RK3308TRM%20V1.1%20Part1-20180810.pdf diff --git a/tcl/target/rsl10.cfg b/tcl/target/rsl10.cfg new file mode 100644 index 0000000..f4692cc --- /dev/null +++ b/tcl/target/rsl10.cfg @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# +# RSL10: ARM Cortex-M3 +# + +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME rsl10 +} + +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x8000 +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x2ba01477 +} + +swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x200000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# TODO: configure reset +# reset_config srst_only srst_nogate connect_assert_srst + +$_TARGETNAME configure -event examine-fail rsl10_lock_warning + +proc rsl10_check_connection {} { + set target [target current] + set dap [$target cget -dap] + + set IDR [$dap apreg 0 0xfc] + if {$IDR != 0x24770011} { + echo "Error: Cannot access RSL10 AP, maybe connection problem!" + return 1 + } + return 0 +} + +proc rsl10_lock_warning {} { + if {[rsl10_check_connection]} {return} + + poll off + echo "****** WARNING ******" + echo "RSL10 device probably has lock engaged." + echo "Debug access is denied." + echo "Use 'rsl10 unlock key1 key2 key3 key4' to erase and unlock the device." + echo "****** ....... ******" + echo "" +} + +flash bank $_CHIPNAME.main rsl10 0x00100000 0x60000 0 0 $_TARGETNAME +flash bank $_CHIPNAME.nvr1 rsl10 0x00080000 0x800 0 0 $_TARGETNAME +flash bank $_CHIPNAME.nvr2 rsl10 0x00080800 0x800 0 0 $_TARGETNAME +flash bank $_CHIPNAME.nvr3 rsl10 0x00081000 0x800 0 0 $_TARGETNAME + +# TODO: implement flashing for nvr4 +# flash bank $_CHIPNAME.nvr4 rsl10 0x00081800 0x400 0 0 $_TARGETNAME diff --git a/tcl/target/samsung_s3c2410.cfg b/tcl/target/samsung_s3c2410.cfg index 017c104..5a04871 100644 --- a/tcl/target/samsung_s3c2410.cfg +++ b/tcl/target/samsung_s3c2410.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Found on the 'TinCanTools' Hammer board. if { [info exists CHIPNAME] } { diff --git a/tcl/target/samsung_s3c2440.cfg b/tcl/target/samsung_s3c2440.cfg index a97659b..d976a8e 100644 --- a/tcl/target/samsung_s3c2440.cfg +++ b/tcl/target/samsung_s3c2440.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Target configuration for the Samsung 2440 system on chip # Tested on a S3C2440 Evaluation board by keesj # Processor : ARM920Tid(wb) rev 0 (v4l) diff --git a/tcl/target/samsung_s3c2450.cfg b/tcl/target/samsung_s3c2450.cfg index 2482557..801e1bc 100644 --- a/tcl/target/samsung_s3c2450.cfg +++ b/tcl/target/samsung_s3c2450.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Target configuration for the Samsung 2450 system on chip # Processor : ARM926ejs (wb) rev 0 (v4l) # Info: JTAG tap: s3c2450.cpu tap/device found: 0x07926F0F diff --git a/tcl/target/samsung_s3c4510.cfg b/tcl/target/samsung_s3c4510.cfg index 8bc5da5..45bed2f 100644 --- a/tcl/target/samsung_s3c4510.cfg +++ b/tcl/target/samsung_s3c4510.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { diff --git a/tcl/target/samsung_s3c6410.cfg b/tcl/target/samsung_s3c6410.cfg index 9f7c2cd..c157458 100644 --- a/tcl/target/samsung_s3c6410.cfg +++ b/tcl/target/samsung_s3c6410.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # -*- tcl -*- # Target configuration for the Samsung s3c6410 system on chip # Tested on a SMDK6410 diff --git a/tcl/target/sharp_lh79532.cfg b/tcl/target/sharp_lh79532.cfg index a464839..af6ceab 100644 --- a/tcl/target/sharp_lh79532.cfg +++ b/tcl/target/sharp_lh79532.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + reset_config srst_only srst_pulls_trst if { [info exists CHIPNAME] } { diff --git a/tcl/target/sim3x.cfg b/tcl/target/sim3x.cfg index 3d3fc5c..e6bea70 100644 --- a/tcl/target/sim3x.cfg +++ b/tcl/target/sim3x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Silicon Laboratories SiM3x Cortex-M3 # diff --git a/tcl/target/smp8634.cfg b/tcl/target/smp8634.cfg index e95f633..0e609d8 100644 --- a/tcl/target/smp8634.cfg +++ b/tcl/target/smp8634.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for Sigma Designs SMP8634 (eventually even SMP8635) if { [info exists CHIPNAME] } { diff --git a/tcl/target/snps_em_sk_fpga.cfg b/tcl/target/snps_em_sk_fpga.cfg index d09561f..62f4dec 100644 --- a/tcl/target/snps_em_sk_fpga.cfg +++ b/tcl/target/snps_em_sk_fpga.cfg @@ -1,8 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Copyright (C) 2014-2015,2020 Synopsys, Inc. # Anton Kolesov <anton.kolesov@synopsys.com> # Didin Evgeniy <didin@synopsys.com> -# -# SPDX-License-Identifier: GPL-2.0-or-later # # Xilinx Spartan-6 XC6SLX45 FPGA on EM Starter Kit v1. diff --git a/tcl/target/snps_hsdk.cfg b/tcl/target/snps_hsdk.cfg index 372b406..b4f3684 100644 --- a/tcl/target/snps_hsdk.cfg +++ b/tcl/target/snps_hsdk.cfg @@ -1,8 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Copyright (C) 2019,2020 Synopsys, Inc. # Anton Kolesov <anton.kolesov@synopsys.com> # Didin Evgeniy <didin@synopsys.com> -# -# SPDX-License-Identifier: GPL-2.0-or-later # # HS Development Kit SoC. diff --git a/tcl/target/spear3xx.cfg b/tcl/target/spear3xx.cfg index a86a3c4..1261cd4 100644 --- a/tcl/target/spear3xx.cfg +++ b/tcl/target/spear3xx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Target configuration for the ST SPEAr3xx family of system on chip # Supported SPEAr300, SPEAr310, SPEAr320 # http://www.st.com/spear diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg index 4865e29..3cd91eb 100644 --- a/tcl/target/stellaris.cfg +++ b/tcl/target/stellaris.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # TI/Luminary Stellaris LM3S chip family # Some devices have errata in returning their device class. diff --git a/tcl/target/stm32f0x.cfg b/tcl/target/stm32f0x.cfg index b20d036..5b8954e 100644 --- a/tcl/target/stm32f0x.cfg +++ b/tcl/target/stm32f0x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for stm32f0x family # diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg index 3e85fb2..53e81a5 100644 --- a/tcl/target/stm32f1x.cfg +++ b/tcl/target/stm32f1x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for stm32f1x family # @@ -81,9 +83,16 @@ $_TARGETNAME configure -event examine-end { mmw 0xE0042004 0x00000307 0 } -$_TARGETNAME configure -event trace-config { +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync # change this value accordingly to configure trace pins # assignment mmw 0xE0042004 0x00000020 0 } + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/tcl/target/stm32f2x.cfg b/tcl/target/stm32f2x.cfg index d790feb..f475826 100644 --- a/tcl/target/stm32f2x.cfg +++ b/tcl/target/stm32f2x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for stm32f2x family # @@ -81,9 +83,16 @@ $_TARGETNAME configure -event examine-end { mmw 0xE0042008 0x00001800 0 } -$_TARGETNAME configure -event trace-config { +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync # change this value accordingly to configure trace pins # assignment mmw 0xE0042004 0x00000020 0 } + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg index e3f1a34..4ecc7ed 100644 --- a/tcl/target/stm32f3x.cfg +++ b/tcl/target/stm32f3x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for stm32f3x family # @@ -101,9 +103,16 @@ $_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end } $_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start } $_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init } -$_TARGETNAME configure -event trace-config { +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync # change this value accordingly to configure trace pins # assignment mmw 0xe0042004 0x00000020 0 } + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg index aa2816e..35d8275 100644 --- a/tcl/target/stm32f4x.cfg +++ b/tcl/target/stm32f4x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for stm32f4x family # @@ -38,8 +40,6 @@ if { [info exists CPUTAPID] } { swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 - if {[using_jtag]} { jtag newtap $_CHIPNAME bs -irlen 5 } @@ -91,24 +91,30 @@ $_TARGETNAME configure -event examine-end { mmw 0xE0042008 0x00001800 0 } -proc proc_post_enable {_chipname} { +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} { targets $_chipname.cpu if { [$_chipname.tpiu cget -protocol] eq "sync" } { switch [$_chipname.tpiu cget -port-width] { 1 { + # Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0 mmw 0xE0042004 0x00000060 0x000000c0 mmw 0x40021020 0x00000000 0x0000ff00 mmw 0x40021000 0x000000a0 0x000000f0 mmw 0x40021008 0x000000f0 0x00000000 } 2 { + # Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0 mmw 0xE0042004 0x000000a0 0x000000c0 mmw 0x40021020 0x00000000 0x000fff00 mmw 0x40021000 0x000002a0 0x000003f0 mmw 0x40021008 0x000003f0 0x00000000 } 4 { + # Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0 mmw 0xE0042004 0x000000e0 0x000000c0 mmw 0x40021020 0x00000000 0x0fffff00 mmw 0x40021000 0x00002aa0 0x00003ff0 @@ -116,11 +122,12 @@ proc proc_post_enable {_chipname} { } } } else { + # Set TRACE_IOEN; TRACE_MODE to async mmw 0xE0042004 0x00000020 0x000000c0 } } -$_CHIPNAME.tpiu configure -event post-enable "proc_post_enable $_CHIPNAME" +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME" $_TARGETNAME configure -event reset-init { # Configure PLL to boost clock to HSI x 4 (64 MHz) diff --git a/tcl/target/stm32f7x.cfg b/tcl/target/stm32f7x.cfg index 91ab289..3782b9a 100644 --- a/tcl/target/stm32f7x.cfg +++ b/tcl/target/stm32f7x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for stm32f7x family # @@ -107,13 +109,20 @@ $_TARGETNAME configure -event examine-end { mmw 0xE0042008 0x00001800 0 } -$_TARGETNAME configure -event trace-config { +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync # change this value accordingly to configure trace pins # assignment mmw 0xE0042004 0x00000020 0 } +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" + $_TARGETNAME configure -event reset-init { # If the HSE was previously enabled and the external clock source # disappeared, RCC_CR.HSERDY can get stuck at 1 and the PLL cannot be diff --git a/tcl/target/stm32g0x.cfg b/tcl/target/stm32g0x.cfg index 7df5306..b6d9a22 100644 --- a/tcl/target/stm32g0x.cfg +++ b/tcl/target/stm32g0x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for stm32g0x family # diff --git a/tcl/target/stm32g4x.cfg b/tcl/target/stm32g4x.cfg index 360447b..39ed1e3 100644 --- a/tcl/target/stm32g4x.cfg +++ b/tcl/target/stm32g4x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for stm32g4x family # @@ -95,9 +97,16 @@ $_TARGETNAME configure -event examine-end { mmw 0xE0042008 0x00001800 0 } -$_TARGETNAME configure -event trace-config { +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync # change this value accordingly to configure trace pins # assignment mmw 0xE0042004 0x00000020 0 } + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg index ca685c2..5aae938 100644 --- a/tcl/target/stm32h7x.cfg +++ b/tcl/target/stm32h7x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for stm32h7x family # diff --git a/tcl/target/stm32h7x_dual_bank.cfg b/tcl/target/stm32h7x_dual_bank.cfg index a88d70d..41a4773 100644 --- a/tcl/target/stm32h7x_dual_bank.cfg +++ b/tcl/target/stm32h7x_dual_bank.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for stm32h7x family (dual flash bank) # STM32H7xxxI 2Mo have a dual bank flash. diff --git a/tcl/target/stm32l0.cfg b/tcl/target/stm32l0.cfg index 7653d13..b4bdb18 100644 --- a/tcl/target/stm32l0.cfg +++ b/tcl/target/stm32l0.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # M0+ devices only have SW-DP, but swj-dp code works, just don't # set any jtag related features diff --git a/tcl/target/stm32l0_dual_bank.cfg b/tcl/target/stm32l0_dual_bank.cfg index f9f1a4e..ff3cb90 100644 --- a/tcl/target/stm32l0_dual_bank.cfg +++ b/tcl/target/stm32l0_dual_bank.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + source [find target/stm32l0.cfg] # Add the second flash bank. diff --git a/tcl/target/stm32l1.cfg b/tcl/target/stm32l1.cfg index a81d7c7..53d9076 100644 --- a/tcl/target/stm32l1.cfg +++ b/tcl/target/stm32l1.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # stm32l1 devices support both JTAG and SWD transports. # @@ -99,9 +101,16 @@ $_TARGETNAME configure -event examine-end { mmw 0xE0042008 0x00001800 0 } -$_TARGETNAME configure -event trace-config { +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync # change this value accordingly to configure trace pins # assignment mmw 0xE0042004 0x00000020 0 } + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/tcl/target/stm32l1x_dual_bank.cfg b/tcl/target/stm32l1x_dual_bank.cfg index a3f7413..deefdb4 100644 --- a/tcl/target/stm32l1x_dual_bank.cfg +++ b/tcl/target/stm32l1x_dual_bank.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + source [find target/stm32l1.cfg] # The stm32l1x 384kb have a dual bank flash. diff --git a/tcl/target/stm32l4x.cfg b/tcl/target/stm32l4x.cfg index 9bd7e37..9a69673 100644 --- a/tcl/target/stm32l4x.cfg +++ b/tcl/target/stm32l4x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for stm32l4x family # @@ -38,8 +40,6 @@ if { [info exists CPUTAPID] } { swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 - if {[using_jtag]} { jtag newtap $_CHIPNAME bs -irlen 5 } @@ -101,24 +101,30 @@ $_TARGETNAME configure -event examine-end { mmw 0xE0042008 0x00001800 0 } -proc proc_post_enable {_chipname} { +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} { targets $_chipname.cpu if { [$_chipname.tpiu cget -protocol] eq "sync" } { switch [$_chipname.tpiu cget -port-width] { 1 { + # Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0 mmw 0xE0042004 0x00000060 0x000000c0 mmw 0x48001020 0x00000000 0x0000ff00 mmw 0x48001000 0x000000a0 0x000000f0 mmw 0x48001008 0x000000f0 0x00000000 } 2 { + # Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0 mmw 0xE0042004 0x000000a0 0x000000c0 mmw 0x48001020 0x00000000 0x000fff00 mmw 0x48001000 0x000002a0 0x000003f0 mmw 0x48001008 0x000003f0 0x00000000 } 4 { + # Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0 mmw 0xE0042004 0x000000e0 0x000000c0 mmw 0x48001020 0x00000000 0x0fffff00 mmw 0x48001000 0x00002aa0 0x00003ff0 @@ -126,11 +132,12 @@ proc proc_post_enable {_chipname} { } } } else { + # Set TRACE_IOEN; TRACE_MODE to async mmw 0xE0042004 0x00000020 0x000000c0 } } -$_CHIPNAME.tpiu configure -event post-enable "proc_post_enable $_CHIPNAME" +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME" $_TARGETNAME configure -event reset-init { # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz). diff --git a/tcl/target/stm32mp13x.cfg b/tcl/target/stm32mp13x.cfg index 0c464b4..bcf25c9 100644 --- a/tcl/target/stm32mp13x.cfg +++ b/tcl/target/stm32mp13x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # STMicroelectronics STM32MP13x (Single Cortex-A7) # http://www.st.com/stm32mp1 diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg index afd5d24..bcdda73 100644 --- a/tcl/target/stm32mp15x.cfg +++ b/tcl/target/stm32mp15x.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # STMicroelectronics STM32MP15x (Single/Dual Cortex-A7 plus Cortex-M4) # http://www.st.com/stm32mp1 diff --git a/tcl/target/stm32w108xx.cfg b/tcl/target/stm32w108xx.cfg index 0470bf6..e6a62e8 100644 --- a/tcl/target/stm32w108xx.cfg +++ b/tcl/target/stm32w108xx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Target configuration for the ST STM32W108xx chips # diff --git a/tcl/target/stm32wbx.cfg b/tcl/target/stm32wbx.cfg index 6467667..737b144 100644 --- a/tcl/target/stm32wbx.cfg +++ b/tcl/target/stm32wbx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for stm32wbx family # @@ -95,9 +97,16 @@ $_TARGETNAME configure -event examine-end { mmw 0xE004203C 0x00001800 0 } -$_TARGETNAME configure -event trace-config { +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync # change this value accordingly to configure trace pins # assignment mmw 0xE0042004 0x00000020 0 } + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/tcl/target/stm32wlx.cfg b/tcl/target/stm32wlx.cfg index 75f6f02..39c897f 100644 --- a/tcl/target/stm32wlx.cfg +++ b/tcl/target/stm32wlx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for stm32wlx family # @@ -117,9 +119,7 @@ $_CHIPNAME.cpu0 configure -event examine-end { } } -$_CHIPNAME.cpu0 configure -event trace-config { - # nothing to do -} +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 if {[set $_CHIPNAME.DUAL_CORE]} { target create $_CHIPNAME.cpu1 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1 diff --git a/tcl/target/stm32x5x_common.cfg b/tcl/target/stm32x5x_common.cfg index 276d0cc..c506e22 100644 --- a/tcl/target/stm32x5x_common.cfg +++ b/tcl/target/stm32x5x_common.cfg @@ -146,9 +146,16 @@ $_TARGETNAME configure -event gdb-flash-erase-start { $_TARGETNAME configure -work-area-phys $workarea_addr } -$_TARGETNAME configure -event trace-config { +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} { + targets $_targetname + # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync # change this value accordingly to configure trace pins # assignment mmw 0xE0044004 0x00000020 0 } + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME" diff --git a/tcl/target/stm32xl.cfg b/tcl/target/stm32xl.cfg index f72896d..ad68f3a 100644 --- a/tcl/target/stm32xl.cfg +++ b/tcl/target/stm32xl.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for stm32xl family (dual flash bank) source [find target/stm32f1x.cfg] diff --git a/tcl/target/stm8l.cfg b/tcl/target/stm8l.cfg index a06c4cb..583a2a4 100644 --- a/tcl/target/stm8l.cfg +++ b/tcl/target/stm8l.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for stm8l family # diff --git a/tcl/target/stm8l152.cfg b/tcl/target/stm8l152.cfg index 8545a5a..b716ce1 100644 --- a/tcl/target/stm8l152.cfg +++ b/tcl/target/stm8l152.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + #config script for STM8L152 set EEPROMSTART 0x1000 diff --git a/tcl/target/stm8s.cfg b/tcl/target/stm8s.cfg index 2dae655..01e50d0 100644 --- a/tcl/target/stm8s.cfg +++ b/tcl/target/stm8s.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for stm8s family # diff --git a/tcl/target/stm8s003.cfg b/tcl/target/stm8s003.cfg index 34997be..60f5c3c 100644 --- a/tcl/target/stm8s003.cfg +++ b/tcl/target/stm8s003.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + #config script for STM8S003 set FLASHEND 0x9FFF diff --git a/tcl/target/stm8s103.cfg b/tcl/target/stm8s103.cfg index 714acf4..41350cb 100644 --- a/tcl/target/stm8s103.cfg +++ b/tcl/target/stm8s103.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + #config script for STM8S103 set FLASHEND 0x9FFF diff --git a/tcl/target/stm8s105.cfg b/tcl/target/stm8s105.cfg index 820bcf7..6af491e 100644 --- a/tcl/target/stm8s105.cfg +++ b/tcl/target/stm8s105.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + #config script for STM8S105 proc stm8_reset_rop {} { diff --git a/tcl/target/str710.cfg b/tcl/target/str710.cfg index 29faaaa..ff89717 100644 --- a/tcl/target/str710.cfg +++ b/tcl/target/str710.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + #start slow, speed up after reset adapter speed 10 diff --git a/tcl/target/str730.cfg b/tcl/target/str730.cfg index e9e2f26..57681f9 100644 --- a/tcl/target/str730.cfg +++ b/tcl/target/str730.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + #STR730 CPU adapter speed 3000 diff --git a/tcl/target/str750.cfg b/tcl/target/str750.cfg index 335d5ad..5af7b74 100644 --- a/tcl/target/str750.cfg +++ b/tcl/target/str750.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + #STR750 CPU if { [info exists CHIPNAME] } { diff --git a/tcl/target/str912.cfg b/tcl/target/str912.cfg index 7426276..3167b40 100644 --- a/tcl/target/str912.cfg +++ b/tcl/target/str912.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # script for str9 if { [info exists CHIPNAME] } { diff --git a/tcl/target/swj-dp.tcl b/tcl/target/swj-dp.tcl index 3fb0263..f2b233f 100644 --- a/tcl/target/swj-dp.tcl +++ b/tcl/target/swj-dp.tcl @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # ARM Debug Interface V5 (ADI_V5) utility # ... Mostly for SWJ-DP (not SW-DP or JTAG-DP, since # SW-DP and JTAG-DP targets don't need to switch based diff --git a/tcl/target/swm050.cfg b/tcl/target/swm050.cfg index e6f2ecb..6cc5f6d 100644 --- a/tcl/target/swm050.cfg +++ b/tcl/target/swm050.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Synwit SWM050 source [find target/swj-dp.tcl] diff --git a/tcl/target/test_reset_syntax_error.cfg b/tcl/target/test_reset_syntax_error.cfg index cb4e46f..7ef5914 100644 --- a/tcl/target/test_reset_syntax_error.cfg +++ b/tcl/target/test_reset_syntax_error.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Test script to check that syntax error in reset # script is reported properly. diff --git a/tcl/target/test_syntax_error.cfg b/tcl/target/test_syntax_error.cfg index d4f92fa..2d5da7f 100644 --- a/tcl/target/test_syntax_error.cfg +++ b/tcl/target/test_syntax_error.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # This script tests a syntax error in the startup # config script diff --git a/tcl/target/ti-ar7.cfg b/tcl/target/ti-ar7.cfg index 19d8c6f..28b6cf7 100644 --- a/tcl/target/ti-ar7.cfg +++ b/tcl/target/ti-ar7.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Texas Instruments AR7 SOC - used in many adsl modems. # http://www.linux-mips.org/wiki/AR7 diff --git a/tcl/target/ti-cjtag.cfg b/tcl/target/ti-cjtag.cfg index 7114b2a..d5e13e2 100644 --- a/tcl/target/ti-cjtag.cfg +++ b/tcl/target/ti-cjtag.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # A start sequence to change from cJTAG to 4-pin JTAG # This is needed for CC2538 and CC26xx to be able to communicate through JTAG # Read section 6.3 in http://www.ti.com/lit/pdf/swru319 for more information. diff --git a/tcl/target/ti_calypso.cfg b/tcl/target/ti_calypso.cfg index 52a84fb..9083336 100644 --- a/tcl/target/ti_calypso.cfg +++ b/tcl/target/ti_calypso.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # TI Calypso (lite) G2 C035 Digital Base Band chip # diff --git a/tcl/target/ti_cc13x0.cfg b/tcl/target/ti_cc13x0.cfg index 6ea9bd8..f1c43a6 100644 --- a/tcl/target/ti_cc13x0.cfg +++ b/tcl/target/ti_cc13x0.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Texas Instruments CC13x0 - ARM Cortex-M3 # diff --git a/tcl/target/ti_cc13x2.cfg b/tcl/target/ti_cc13x2.cfg index 280eef4..c850816 100644 --- a/tcl/target/ti_cc13x2.cfg +++ b/tcl/target/ti_cc13x2.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Texas Instruments CC13x2 - ARM Cortex-M4 # diff --git a/tcl/target/ti_cc26x0.cfg b/tcl/target/ti_cc26x0.cfg index f95d7b2..b9ccf31 100644 --- a/tcl/target/ti_cc26x0.cfg +++ b/tcl/target/ti_cc26x0.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Texas Instruments CC26x0 - ARM Cortex-M3 # diff --git a/tcl/target/ti_cc26x2.cfg b/tcl/target/ti_cc26x2.cfg index ecee3fa..62c91c3 100644 --- a/tcl/target/ti_cc26x2.cfg +++ b/tcl/target/ti_cc26x2.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Texas Instruments CC26x2 - ARM Cortex-M4 # diff --git a/tcl/target/ti_cc3220sf.cfg b/tcl/target/ti_cc3220sf.cfg index c0a7b56..cf43363 100644 --- a/tcl/target/ti_cc3220sf.cfg +++ b/tcl/target/ti_cc3220sf.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Texas Instruments CC3220SF - ARM Cortex-M4 # diff --git a/tcl/target/ti_cc32xx.cfg b/tcl/target/ti_cc32xx.cfg index e3e3ebc..9eb03eb 100644 --- a/tcl/target/ti_cc32xx.cfg +++ b/tcl/target/ti_cc32xx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Texas Instruments CC32xx - ARM Cortex-M4 # diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg index 19fb0b6..4292373 100644 --- a/tcl/target/ti_dm355.cfg +++ b/tcl/target/ti_dm355.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Texas Instruments DaVinci family: TMS320DM355 # diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg index f71a77a..e19efd7 100644 --- a/tcl/target/ti_dm365.cfg +++ b/tcl/target/ti_dm365.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Texas Instruments DaVinci family: TMS320DM365 # diff --git a/tcl/target/ti_dm6446.cfg b/tcl/target/ti_dm6446.cfg index ccc650a..8938234 100644 --- a/tcl/target/ti_dm6446.cfg +++ b/tcl/target/ti_dm6446.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Texas Instruments DaVinci family: TMS320DM6446 # diff --git a/tcl/target/ti_msp432.cfg b/tcl/target/ti_msp432.cfg index 77f81da..8a90b98 100644 --- a/tcl/target/ti_msp432.cfg +++ b/tcl/target/ti_msp432.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Texas Instruments MSP432 - ARM Cortex-M4F @ up to 48 MHz # diff --git a/tcl/target/ti_rm4x.cfg b/tcl/target/ti_rm4x.cfg index 85c3e81..715aa5b 100644 --- a/tcl/target/ti_rm4x.cfg +++ b/tcl/target/ti_rm4x.cfg @@ -1 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + source [find target/ti_tms570.cfg] diff --git a/tcl/target/ti_tms570.cfg b/tcl/target/ti_tms570.cfg index d06ff97..213fb09 100644 --- a/tcl/target/ti_tms570.cfg +++ b/tcl/target/ti_tms570.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + adapter speed 1500 if { [info exists CHIPNAME] } { diff --git a/tcl/target/ti_tms570ls20xxx.cfg b/tcl/target/ti_tms570ls20xxx.cfg index ef45b7a..cc2bbd6 100644 --- a/tcl/target/ti_tms570ls20xxx.cfg +++ b/tcl/target/ti_tms570ls20xxx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # TMS570LS20216, TMS570LS20206, TMS570LS10216 # TMS570LS10206, TMS570LS10116, TMS570LS10106 set DAP_TAPID 0x0B7B302F diff --git a/tcl/target/ti_tms570ls3137.cfg b/tcl/target/ti_tms570ls3137.cfg index f291803..ebe2cfc 100644 --- a/tcl/target/ti_tms570ls3137.cfg +++ b/tcl/target/ti_tms570ls3137.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # TMS570LS3137 set DAP_TAPID 0x0B8A002F set JRC_TAPID 0x0B8A002F diff --git a/tcl/target/tmpa900.cfg b/tcl/target/tmpa900.cfg index 8e70700..b7ec689 100644 --- a/tcl/target/tmpa900.cfg +++ b/tcl/target/tmpa900.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + ###################################### # Target: Toshiba TMPA900 ###################################### diff --git a/tcl/target/tmpa910.cfg b/tcl/target/tmpa910.cfg index d933c0b..276d1ad 100644 --- a/tcl/target/tmpa910.cfg +++ b/tcl/target/tmpa910.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + ###################################### # Target: Toshiba TMPA910 ###################################### diff --git a/tcl/target/tnetc4401.cfg b/tcl/target/tnetc4401.cfg index 48f7545..6a24980 100644 --- a/tcl/target/tnetc4401.cfg +++ b/tcl/target/tnetc4401.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Texas Instruments (TI) TNETC4401, MIPS32 DOCSIS-tailored SoC (4Kc-based) # Used in Knovative KC-100 and Motorola Surfboard SB5120 cable modems. # Datasheet: https://brezn.muc.ccc.de/~mazzoo/DOCSIS/tnetc4401.pdf diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg index 5aee135..417fdd1 100644 --- a/tcl/target/u8500.cfg +++ b/tcl/target/u8500.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Copyright (C) ST-Ericsson SA 2011 # Author : michel.jaouen@stericsson.com # U8500 target diff --git a/tcl/target/vd_riscv.cfg b/tcl/target/vd_riscv.cfg index b42b25a..f08cb1a 100644 --- a/tcl/target/vd_riscv.cfg +++ b/tcl/target/vd_riscv.cfg @@ -14,5 +14,4 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid $_HARTID riscv set_reset_timeout_sec 120 riscv set_command_timeout_sec 120 -# prefer to use sba for system bus access -riscv set_prefer_sba on +riscv set_mem_access sysbus progbuf diff --git a/tcl/target/vd_xtensa_jtag.cfg b/tcl/target/vd_xtensa_jtag.cfg new file mode 100644 index 0000000..88f5bcc --- /dev/null +++ b/tcl/target/vd_xtensa_jtag.cfg @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# for Palladium emulation systems +# + +# TODO: Enable backdoor memory access +# set _MEMSTART 0x00000000 +# set _MEMSIZE 0x100000 + +# BFM hierarchical path and input clk period +vdebug bfm_path dut_top.JTAG 10ns +# DMA Memories to access backdoor (up to 4) +# vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE + +# Create Xtensa target first +source [find target/xtensa.cfg] + +# Configure Xtensa core parameters next +# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config" + +# register target +proc vdebug_examine_end {} { +# vdebug register_target +} + +# Default hooks +$_TARGETNAME configure -event examine-end { vdebug_examine_end } diff --git a/tcl/target/vybrid_vf6xx.cfg b/tcl/target/vybrid_vf6xx.cfg index c888d25..776c16b 100644 --- a/tcl/target/vybrid_vf6xx.cfg +++ b/tcl/target/vybrid_vf6xx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Freescale Vybrid VF610 # diff --git a/tcl/target/xilinx_zynqmp.cfg b/tcl/target/xilinx_zynqmp.cfg index 2df7a4f..8933729 100644 --- a/tcl/target/xilinx_zynqmp.cfg +++ b/tcl/target/xilinx_zynqmp.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # target configuration for # Xilinx ZynqMP (UltraScale+ / A53) diff --git a/tcl/target/xmc1xxx.cfg b/tcl/target/xmc1xxx.cfg index eb94d7b..cafd032 100644 --- a/tcl/target/xmc1xxx.cfg +++ b/tcl/target/xmc1xxx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Infineon XMC1100/XMC1200/XMC1300 family (ARM Cortex-M0 @ 32 MHz) # diff --git a/tcl/target/xmc4xxx.cfg b/tcl/target/xmc4xxx.cfg index 3020b28..0e28494 100644 --- a/tcl/target/xmc4xxx.cfg +++ b/tcl/target/xmc4xxx.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Infineon XMC4100/XMC4200/XMC4400/XMC4500 family (ARM Cortex-M4 @ 80-120 MHz) # diff --git a/tcl/target/xmos_xs1-xau8a-10_arm.cfg b/tcl/target/xmos_xs1-xau8a-10_arm.cfg index 3fc197a..60fe9ad 100644 --- a/tcl/target/xmos_xs1-xau8a-10_arm.cfg +++ b/tcl/target/xmos_xs1-xau8a-10_arm.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # XMOS xCORE-XA XS1-XAU8A-10: ARM Cortex-M3 @ 48 MHz # diff --git a/tcl/target/xtensa-core-esp32.cfg b/tcl/target/xtensa-core-esp32.cfg new file mode 100644 index 0000000..e7b5a20 --- /dev/null +++ b/tcl/target/xtensa-core-esp32.cfg @@ -0,0 +1,260 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# OpenOCD configuration file for Xtensa ESP32 target + +# Core definition and ABI +xtensa xtdef LX +xtensa xtopt arnum 64 +xtensa xtopt windowed 1 + +# Exception/Interrupt Options +xtensa xtopt exceptions 1 +xtensa xtopt hipriints 1 +xtensa xtopt intlevels 6 +xtensa xtopt excmlevel 3 + +# Cache Options +xtensa xtmem icache 4 0 1 +xtensa xtmem dcache 4 0 1 0 + +# Memory Options +xtensa xtmem irom 0x400D0000 0x330000 +xtensa xtmem irom 0x40000000 0x64F00 +xtensa xtmem iram 0x40070000 0x30000 +xtensa xtmem iram 0x400C0000 0x2000 +xtensa xtmem drom 0x3F400000 0x800000 +xtensa xtmem dram 0x3FFAE000 0x52000 +xtensa xtmem dram 0x3FF80000 0x2000 +xtensa xtmem dram 0x3F800000 0x400000 +xtensa xtmem dram 0x50000000 0x2000 +xtensa xtmem dram 0x3FF00000 0x71000 +xtensa xtmem dram 0x60000000 0x20000000 + +# Memory Protection/Translation Options + +# Debug Options +xtensa xtopt debuglevel 6 +xtensa xtopt ibreaknum 2 +xtensa xtopt dbreaknum 2 +xtensa xtopt tracemem 8192 +xtensa xtopt tracememrev 1 +xtensa xtopt perfcount 2 + +# Core Registers +# xtregfmt: Optionally specify "contiguous" vs. "sparse" GDB register map. +# Default setting is "sparse" and is used with xt-gdb. +# If contiguous, optional parameter specifies number of registers +# in "Read General Registers" (g-packet) requests. +# NOTE: For contiguous format, registers listed in GDB order. +# xtregs: Total number of Xtensa registers in the system +xtensa xtregs 205 +xtensa xtregfmt contiguous 105 +xtensa xtreg pc 0x0020 +xtensa xtreg ar0 0x0100 +xtensa xtreg ar1 0x0101 +xtensa xtreg ar2 0x0102 +xtensa xtreg ar3 0x0103 +xtensa xtreg ar4 0x0104 +xtensa xtreg ar5 0x0105 +xtensa xtreg ar6 0x0106 +xtensa xtreg ar7 0x0107 +xtensa xtreg ar8 0x0108 +xtensa xtreg ar9 0x0109 +xtensa xtreg ar10 0x010a +xtensa xtreg ar11 0x010b +xtensa xtreg ar12 0x010c +xtensa xtreg ar13 0x010d +xtensa xtreg ar14 0x010e +xtensa xtreg ar15 0x010f +xtensa xtreg ar16 0x0110 +xtensa xtreg ar17 0x0111 +xtensa xtreg ar18 0x0112 +xtensa xtreg ar19 0x0113 +xtensa xtreg ar20 0x0114 +xtensa xtreg ar21 0x0115 +xtensa xtreg ar22 0x0116 +xtensa xtreg ar23 0x0117 +xtensa xtreg ar24 0x0118 +xtensa xtreg ar25 0x0119 +xtensa xtreg ar26 0x011a +xtensa xtreg ar27 0x011b +xtensa xtreg ar28 0x011c +xtensa xtreg ar29 0x011d +xtensa xtreg ar30 0x011e +xtensa xtreg ar31 0x011f +xtensa xtreg ar32 0x0120 +xtensa xtreg ar33 0x0121 +xtensa xtreg ar34 0x0122 +xtensa xtreg ar35 0x0123 +xtensa xtreg ar36 0x0124 +xtensa xtreg ar37 0x0125 +xtensa xtreg ar38 0x0126 +xtensa xtreg ar39 0x0127 +xtensa xtreg ar40 0x0128 +xtensa xtreg ar41 0x0129 +xtensa xtreg ar42 0x012a +xtensa xtreg ar43 0x012b +xtensa xtreg ar44 0x012c +xtensa xtreg ar45 0x012d +xtensa xtreg ar46 0x012e +xtensa xtreg ar47 0x012f +xtensa xtreg ar48 0x0130 +xtensa xtreg ar49 0x0131 +xtensa xtreg ar50 0x0132 +xtensa xtreg ar51 0x0133 +xtensa xtreg ar52 0x0134 +xtensa xtreg ar53 0x0135 +xtensa xtreg ar54 0x0136 +xtensa xtreg ar55 0x0137 +xtensa xtreg ar56 0x0138 +xtensa xtreg ar57 0x0139 +xtensa xtreg ar58 0x013a +xtensa xtreg ar59 0x013b +xtensa xtreg ar60 0x013c +xtensa xtreg ar61 0x013d +xtensa xtreg ar62 0x013e +xtensa xtreg ar63 0x013f +xtensa xtreg lbeg 0x0200 +xtensa xtreg lend 0x0201 +xtensa xtreg lcount 0x0202 +xtensa xtreg sar 0x0203 +xtensa xtreg windowbase 0x0248 +xtensa xtreg windowstart 0x0249 +xtensa xtreg configid0 0x02b0 +xtensa xtreg configid1 0x02d0 +xtensa xtreg ps 0x02e6 +xtensa xtreg threadptr 0x03e7 + +# added by hand for esp32 +xtensa xtreg br 0x0204 +xtensa xtreg scompare1 0x020c +xtensa xtreg acclo 0x0210 +xtensa xtreg acchi 0x0211 +xtensa xtreg m0 0x0220 +xtensa xtreg m1 0x0221 +xtensa xtreg m2 0x0222 +xtensa xtreg m3 0x0223 +xtensa xtreg expstate 0x03e6 +xtensa xtreg f64r_lo 0x03ea +xtensa xtreg f64r_hi 0x03eb +xtensa xtreg f64s 0x03ec +xtensa xtreg f0 0x0030 +xtensa xtreg f1 0x0031 +xtensa xtreg f2 0x0032 +xtensa xtreg f3 0x0033 +xtensa xtreg f4 0x0034 +xtensa xtreg f5 0x0035 +xtensa xtreg f6 0x0036 +xtensa xtreg f7 0x0037 +xtensa xtreg f8 0x0038 +xtensa xtreg f9 0x0039 +xtensa xtreg f10 0x003a +xtensa xtreg f11 0x003b +xtensa xtreg f12 0x003c +xtensa xtreg f13 0x003d +xtensa xtreg f14 0x003e +xtensa xtreg f15 0x003f +xtensa xtreg fcr 0x03e8 +xtensa xtreg fsr 0x03e9 + +xtensa xtreg mmid 0x0259 +xtensa xtreg ibreakenable 0x0260 + +xtensa xtreg memctl 0x0261 +xtensa xtreg atomctl 0x0263 + +xtensa xtreg ddr 0x0268 +xtensa xtreg ibreaka0 0x0280 +xtensa xtreg ibreaka1 0x0281 +xtensa xtreg dbreaka0 0x0290 +xtensa xtreg dbreaka1 0x0291 +xtensa xtreg dbreakc0 0x02a0 +xtensa xtreg dbreakc1 0x02a1 +xtensa xtreg epc1 0x02b1 +xtensa xtreg epc2 0x02b2 +xtensa xtreg epc3 0x02b3 +xtensa xtreg epc4 0x02b4 +xtensa xtreg epc5 0x02b5 +xtensa xtreg epc6 0x02b6 +xtensa xtreg epc7 0x02b7 +xtensa xtreg depc 0x02c0 +xtensa xtreg eps2 0x02c2 +xtensa xtreg eps3 0x02c3 +xtensa xtreg eps4 0x02c4 +xtensa xtreg eps5 0x02c5 +xtensa xtreg eps6 0x02c6 +xtensa xtreg eps7 0x02c7 +xtensa xtreg excsave1 0x02d1 +xtensa xtreg excsave2 0x02d2 +xtensa xtreg excsave3 0x02d3 +xtensa xtreg excsave4 0x02d4 +xtensa xtreg excsave5 0x02d5 +xtensa xtreg excsave6 0x02d6 +xtensa xtreg excsave7 0x02d7 +xtensa xtreg cpenable 0x02e0 +xtensa xtreg interrupt 0x02e2 +xtensa xtreg intset 0x02e2 +xtensa xtreg intclear 0x02e3 +xtensa xtreg intenable 0x02e4 +xtensa xtreg vecbase 0x02e7 +xtensa xtreg exccause 0x02e8 +xtensa xtreg debugcause 0x02e9 +xtensa xtreg ccount 0x02ea +xtensa xtreg prid 0x02eb +xtensa xtreg icount 0x02ec +xtensa xtreg icountlevel 0x02ed +xtensa xtreg excvaddr 0x02ee +xtensa xtreg ccompare0 0x02f0 +xtensa xtreg ccompare1 0x02f1 +xtensa xtreg ccompare2 0x02f2 +xtensa xtreg misc0 0x02f4 +xtensa xtreg misc1 0x02f5 +xtensa xtreg misc2 0x02f6 +xtensa xtreg misc3 0x02f7 +xtensa xtreg a0 0x0000 +xtensa xtreg a1 0x0001 +xtensa xtreg a2 0x0002 +xtensa xtreg a3 0x0003 +xtensa xtreg a4 0x0004 +xtensa xtreg a5 0x0005 +xtensa xtreg a6 0x0006 +xtensa xtreg a7 0x0007 +xtensa xtreg a8 0x0008 +xtensa xtreg a9 0x0009 +xtensa xtreg a10 0x000a +xtensa xtreg a11 0x000b +xtensa xtreg a12 0x000c +xtensa xtreg a13 0x000d +xtensa xtreg a14 0x000e +xtensa xtreg a15 0x000f +xtensa xtreg pwrctl 0x2028 +xtensa xtreg pwrstat 0x2029 +xtensa xtreg eristat 0x202a +xtensa xtreg cs_itctrl 0x202b +xtensa xtreg cs_claimset 0x202c +xtensa xtreg cs_claimclr 0x202d +xtensa xtreg cs_lockaccess 0x202e +xtensa xtreg cs_lockstatus 0x202f +xtensa xtreg cs_authstatus 0x2030 +xtensa xtreg fault_info 0x203f +xtensa xtreg trax_id 0x2040 +xtensa xtreg trax_control 0x2041 +xtensa xtreg trax_status 0x2042 +xtensa xtreg trax_data 0x2043 +xtensa xtreg trax_address 0x2044 +xtensa xtreg trax_pctrigger 0x2045 +xtensa xtreg trax_pcmatch 0x2046 +xtensa xtreg trax_delay 0x2047 +xtensa xtreg trax_memstart 0x2048 +xtensa xtreg trax_memend 0x2049 +xtensa xtreg pmg 0x2057 +xtensa xtreg pmpc 0x2058 +xtensa xtreg pm0 0x2059 +xtensa xtreg pm1 0x205a +xtensa xtreg pmctrl0 0x2061 +xtensa xtreg pmctrl1 0x2062 +xtensa xtreg pmstat0 0x2069 +xtensa xtreg pmstat1 0x206a +xtensa xtreg ocdid 0x2071 +xtensa xtreg ocd_dcrclr 0x2072 +xtensa xtreg ocd_dcrset 0x2073 +xtensa xtreg ocd_dsr 0x2074 diff --git a/tcl/target/xtensa-core-esp32s2.cfg b/tcl/target/xtensa-core-esp32s2.cfg new file mode 100644 index 0000000..e590e51 --- /dev/null +++ b/tcl/target/xtensa-core-esp32s2.cfg @@ -0,0 +1,223 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# OpenOCD configuration file for Xtensa ESP32S2 target + +# Core definition and ABI +xtensa xtdef LX +xtensa xtopt arnum 64 +xtensa xtopt windowed 1 + +# Exception/Interrupt Options +xtensa xtopt exceptions 1 +xtensa xtopt hipriints 1 +xtensa xtopt intlevels 6 +xtensa xtopt excmlevel 3 + +# Cache Options +xtensa xtmem icache 4 0 1 +xtensa xtmem dcache 4 0 1 0 + +# Memory Options +xtensa xtmem irom 0x40080000 0x780000 +xtensa xtmem irom 0x40000000 0x20000 +xtensa xtmem iram 0x40020000 0x50000 +xtensa xtmem iram 0x40070000 0x2000 +xtensa xtmem drom 0x3F000000 0x400000 +xtensa xtmem drom 0x3F4D3FFC 0xAAC004 +xtensa xtmem dram 0x3FFB0000 0x50000 +xtensa xtmem dram 0x3FF9E000 0x2000 +xtensa xtmem dram 0x50000000 0x2000 +xtensa xtmem dram 0x3F500000 0xA80000 +xtensa xtmem dram 0x3F400000 0xD3FFC +xtensa xtmem dram 0x60000000 0x20000000 + +# Memory Protection/Translation Options + +# Debug Options +xtensa xtopt debuglevel 6 +xtensa xtopt ibreaknum 2 +xtensa xtopt dbreaknum 2 +xtensa xtopt tracemem 8192 +xtensa xtopt tracememrev 1 +xtensa xtopt perfcount 2 + +# Core Registers +# xtregfmt: Optionally specify "contiguous" vs. "sparse" GDB register map. +# Default setting is "sparse" and is used with xt-gdb. +# If contiguous, optional parameter specifies number of registers +# in "Read General Registers" (g-packet) requests. +# NOTE: For contiguous format, registers listed in GDB order. +# xtregs: Total number of Xtensa registers in the system +xtensa xtregs 171 +xtensa xtregfmt contiguous 72 +xtensa xtreg pc 0x0020 +xtensa xtreg ar0 0x0100 +xtensa xtreg ar1 0x0101 +xtensa xtreg ar2 0x0102 +xtensa xtreg ar3 0x0103 +xtensa xtreg ar4 0x0104 +xtensa xtreg ar5 0x0105 +xtensa xtreg ar6 0x0106 +xtensa xtreg ar7 0x0107 +xtensa xtreg ar8 0x0108 +xtensa xtreg ar9 0x0109 +xtensa xtreg ar10 0x010a +xtensa xtreg ar11 0x010b +xtensa xtreg ar12 0x010c +xtensa xtreg ar13 0x010d +xtensa xtreg ar14 0x010e +xtensa xtreg ar15 0x010f +xtensa xtreg ar16 0x0110 +xtensa xtreg ar17 0x0111 +xtensa xtreg ar18 0x0112 +xtensa xtreg ar19 0x0113 +xtensa xtreg ar20 0x0114 +xtensa xtreg ar21 0x0115 +xtensa xtreg ar22 0x0116 +xtensa xtreg ar23 0x0117 +xtensa xtreg ar24 0x0118 +xtensa xtreg ar25 0x0119 +xtensa xtreg ar26 0x011a +xtensa xtreg ar27 0x011b +xtensa xtreg ar28 0x011c +xtensa xtreg ar29 0x011d +xtensa xtreg ar30 0x011e +xtensa xtreg ar31 0x011f +xtensa xtreg ar32 0x0120 +xtensa xtreg ar33 0x0121 +xtensa xtreg ar34 0x0122 +xtensa xtreg ar35 0x0123 +xtensa xtreg ar36 0x0124 +xtensa xtreg ar37 0x0125 +xtensa xtreg ar38 0x0126 +xtensa xtreg ar39 0x0127 +xtensa xtreg ar40 0x0128 +xtensa xtreg ar41 0x0129 +xtensa xtreg ar42 0x012a +xtensa xtreg ar43 0x012b +xtensa xtreg ar44 0x012c +xtensa xtreg ar45 0x012d +xtensa xtreg ar46 0x012e +xtensa xtreg ar47 0x012f +xtensa xtreg ar48 0x0130 +xtensa xtreg ar49 0x0131 +xtensa xtreg ar50 0x0132 +xtensa xtreg ar51 0x0133 +xtensa xtreg ar52 0x0134 +xtensa xtreg ar53 0x0135 +xtensa xtreg ar54 0x0136 +xtensa xtreg ar55 0x0137 +xtensa xtreg ar56 0x0138 +xtensa xtreg ar57 0x0139 +xtensa xtreg ar58 0x013a +xtensa xtreg ar59 0x013b +xtensa xtreg ar60 0x013c +xtensa xtreg ar61 0x013d +xtensa xtreg ar62 0x013e +xtensa xtreg ar63 0x013f +xtensa xtreg sar 0x0203 +xtensa xtreg windowbase 0x0248 +xtensa xtreg windowstart 0x0249 +xtensa xtreg configid0 0x02b0 +xtensa xtreg configid1 0x02d0 +xtensa xtreg ps 0x02e6 +xtensa xtreg threadptr 0x03e7 +# gpio_out should be 0x0300? Hits an exception on wrover +xtensa xtreg gpio_out 0x0268 +xtensa xtreg mmid 0x0259 +xtensa xtreg ibreakenable 0x0260 +xtensa xtreg ddr 0x0268 +xtensa xtreg ibreaka0 0x0280 +xtensa xtreg ibreaka1 0x0281 +xtensa xtreg dbreaka0 0x0290 +xtensa xtreg dbreaka1 0x0291 +xtensa xtreg dbreakc0 0x02a0 +xtensa xtreg dbreakc1 0x02a1 +xtensa xtreg epc1 0x02b1 +xtensa xtreg epc2 0x02b2 +xtensa xtreg epc3 0x02b3 +xtensa xtreg epc4 0x02b4 +xtensa xtreg epc5 0x02b5 +xtensa xtreg epc6 0x02b6 +xtensa xtreg epc7 0x02b7 +xtensa xtreg depc 0x02c0 +xtensa xtreg eps2 0x02c2 +xtensa xtreg eps3 0x02c3 +xtensa xtreg eps4 0x02c4 +xtensa xtreg eps5 0x02c5 +xtensa xtreg eps6 0x02c6 +xtensa xtreg eps7 0x02c7 +xtensa xtreg excsave1 0x02d1 +xtensa xtreg excsave2 0x02d2 +xtensa xtreg excsave3 0x02d3 +xtensa xtreg excsave4 0x02d4 +xtensa xtreg excsave5 0x02d5 +xtensa xtreg excsave6 0x02d6 +xtensa xtreg excsave7 0x02d7 +xtensa xtreg cpenable 0x02e0 +xtensa xtreg interrupt 0x02e2 +xtensa xtreg intset 0x02e2 +xtensa xtreg intclear 0x02e3 +xtensa xtreg intenable 0x02e4 +xtensa xtreg vecbase 0x02e7 +xtensa xtreg exccause 0x02e8 +xtensa xtreg debugcause 0x02e9 +xtensa xtreg ccount 0x02ea +xtensa xtreg prid 0x02eb +xtensa xtreg icount 0x02ec +xtensa xtreg icountlevel 0x02ed +xtensa xtreg excvaddr 0x02ee +xtensa xtreg ccompare0 0x02f0 +xtensa xtreg ccompare1 0x02f1 +xtensa xtreg ccompare2 0x02f2 +xtensa xtreg misc0 0x02f4 +xtensa xtreg misc1 0x02f5 +xtensa xtreg misc2 0x02f6 +xtensa xtreg misc3 0x02f7 +xtensa xtreg a0 0x0000 +xtensa xtreg a1 0x0001 +xtensa xtreg a2 0x0002 +xtensa xtreg a3 0x0003 +xtensa xtreg a4 0x0004 +xtensa xtreg a5 0x0005 +xtensa xtreg a6 0x0006 +xtensa xtreg a7 0x0007 +xtensa xtreg a8 0x0008 +xtensa xtreg a9 0x0009 +xtensa xtreg a10 0x000a +xtensa xtreg a11 0x000b +xtensa xtreg a12 0x000c +xtensa xtreg a13 0x000d +xtensa xtreg a14 0x000e +xtensa xtreg a15 0x000f +xtensa xtreg pwrctl 0x2028 +xtensa xtreg pwrstat 0x2029 +xtensa xtreg eristat 0x202a +xtensa xtreg cs_itctrl 0x202b +xtensa xtreg cs_claimset 0x202c +xtensa xtreg cs_claimclr 0x202d +xtensa xtreg cs_lockaccess 0x202e +xtensa xtreg cs_lockstatus 0x202f +xtensa xtreg cs_authstatus 0x2030 +xtensa xtreg fault_info 0x203f +xtensa xtreg trax_id 0x2040 +xtensa xtreg trax_control 0x2041 +xtensa xtreg trax_status 0x2042 +xtensa xtreg trax_data 0x2043 +xtensa xtreg trax_address 0x2044 +xtensa xtreg trax_pctrigger 0x2045 +xtensa xtreg trax_pcmatch 0x2046 +xtensa xtreg trax_delay 0x2047 +xtensa xtreg trax_memstart 0x2048 +xtensa xtreg trax_memend 0x2049 +xtensa xtreg pmg 0x2057 +xtensa xtreg pmpc 0x2058 +xtensa xtreg pm0 0x2059 +xtensa xtreg pm1 0x205a +xtensa xtreg pmctrl0 0x2061 +xtensa xtreg pmctrl1 0x2062 +xtensa xtreg pmstat0 0x2069 +xtensa xtreg pmstat1 0x206a +xtensa xtreg ocdid 0x2071 +xtensa xtreg ocd_dcrclr 0x2072 +xtensa xtreg ocd_dcrset 0x2073 +xtensa xtreg ocd_dsr 0x2074 diff --git a/tcl/target/xtensa-core-esp32s3.cfg b/tcl/target/xtensa-core-esp32s3.cfg new file mode 100644 index 0000000..f5c1cb3 --- /dev/null +++ b/tcl/target/xtensa-core-esp32s3.cfg @@ -0,0 +1,297 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# OpenOCD configuration file for Xtensa ESP32S3 target + +# Core definition and ABI +xtensa xtdef LX +xtensa xtopt arnum 64 +xtensa xtopt windowed 1 + +# Exception/Interrupt Options +xtensa xtopt exceptions 1 +xtensa xtopt hipriints 1 +xtensa xtopt intlevels 6 +xtensa xtopt excmlevel 3 + +# Cache Options + +# Memory Options +xtensa xtmem irom 0x42000000 0x2000000 +xtensa xtmem irom 0x40000000 0x60000 +xtensa xtmem iram 0x40370000 0x70000 +xtensa xtmem iram 0x600FE000 0x2000 +xtensa xtmem drom 0x3C000000 0x1000000 +xtensa xtmem dram 0x3FC88000 0x78000 +xtensa xtmem dram 0x600FE000 0x2000 +xtensa xtmem dram 0x50000000 0x2000 +xtensa xtmem dram 0x60000000 0x10000000 + +# Memory Protection/Translation Options + +# Debug Options +xtensa xtopt debuglevel 6 +xtensa xtopt ibreaknum 2 +xtensa xtopt dbreaknum 2 +xtensa xtopt tracemem 16384 +xtensa xtopt tracememrev 1 +xtensa xtopt perfcount 2 + + +# Core Registers +# xtregfmt: Optionally specify "contiguous" vs. "sparse" GDB register map. +# Default setting is "sparse" and is used with xt-gdb. +# If contiguous, optional parameter specifies number of registers +# in "Read General Registers" (g-packet) requests. +# NOTE: For contiguous format, registers listed in GDB order. +# xtregs: Total number of Xtensa registers in the system +xtensa xtregs 244 +xtensa xtregfmt contiguous 128 +xtensa xtreg pc 0x0020 +xtensa xtreg ar0 0x0100 +xtensa xtreg ar1 0x0101 +xtensa xtreg ar2 0x0102 +xtensa xtreg ar3 0x0103 +xtensa xtreg ar4 0x0104 +xtensa xtreg ar5 0x0105 +xtensa xtreg ar6 0x0106 +xtensa xtreg ar7 0x0107 +xtensa xtreg ar8 0x0108 +xtensa xtreg ar9 0x0109 +xtensa xtreg ar10 0x010a +xtensa xtreg ar11 0x010b +xtensa xtreg ar12 0x010c +xtensa xtreg ar13 0x010d +xtensa xtreg ar14 0x010e +xtensa xtreg ar15 0x010f +xtensa xtreg ar16 0x0110 +xtensa xtreg ar17 0x0111 +xtensa xtreg ar18 0x0112 +xtensa xtreg ar19 0x0113 +xtensa xtreg ar20 0x0114 +xtensa xtreg ar21 0x0115 +xtensa xtreg ar22 0x0116 +xtensa xtreg ar23 0x0117 +xtensa xtreg ar24 0x0118 +xtensa xtreg ar25 0x0119 +xtensa xtreg ar26 0x011a +xtensa xtreg ar27 0x011b +xtensa xtreg ar28 0x011c +xtensa xtreg ar29 0x011d +xtensa xtreg ar30 0x011e +xtensa xtreg ar31 0x011f +xtensa xtreg ar32 0x0120 +xtensa xtreg ar33 0x0121 +xtensa xtreg ar34 0x0122 +xtensa xtreg ar35 0x0123 +xtensa xtreg ar36 0x0124 +xtensa xtreg ar37 0x0125 +xtensa xtreg ar38 0x0126 +xtensa xtreg ar39 0x0127 +xtensa xtreg ar40 0x0128 +xtensa xtreg ar41 0x0129 +xtensa xtreg ar42 0x012a +xtensa xtreg ar43 0x012b +xtensa xtreg ar44 0x012c +xtensa xtreg ar45 0x012d +xtensa xtreg ar46 0x012e +xtensa xtreg ar47 0x012f +xtensa xtreg ar48 0x0130 +xtensa xtreg ar49 0x0131 +xtensa xtreg ar50 0x0132 +xtensa xtreg ar51 0x0133 +xtensa xtreg ar52 0x0134 +xtensa xtreg ar53 0x0135 +xtensa xtreg ar54 0x0136 +xtensa xtreg ar55 0x0137 +xtensa xtreg ar56 0x0138 +xtensa xtreg ar57 0x0139 +xtensa xtreg ar58 0x013a +xtensa xtreg ar59 0x013b +xtensa xtreg ar60 0x013c +xtensa xtreg ar61 0x013d +xtensa xtreg ar62 0x013e +xtensa xtreg ar63 0x013f +xtensa xtreg lbeg 0x0200 +xtensa xtreg lend 0x0201 +xtensa xtreg lcount 0x0202 +xtensa xtreg sar 0x0203 +xtensa xtreg windowbase 0x0248 +xtensa xtreg windowstart 0x0249 +xtensa xtreg configid0 0x02b0 +xtensa xtreg configid1 0x02d0 +xtensa xtreg ps 0x02e6 +xtensa xtreg threadptr 0x03e7 +xtensa xtreg br 0x0204 +xtensa xtreg scompare1 0x020c +xtensa xtreg acclo 0x0210 +xtensa xtreg acchi 0x0211 +xtensa xtreg m0 0x0220 +xtensa xtreg m1 0x0221 +xtensa xtreg m2 0x0222 +xtensa xtreg m3 0x0223 + +# TODO: update gpioout address while testing on S3 HW +xtensa xtreg gpioout 0x02f4 + +xtensa xtreg f0 0x0030 +xtensa xtreg f1 0x0031 +xtensa xtreg f2 0x0032 +xtensa xtreg f3 0x0033 +xtensa xtreg f4 0x0034 +xtensa xtreg f5 0x0035 +xtensa xtreg f6 0x0036 +xtensa xtreg f7 0x0037 +xtensa xtreg f8 0x0038 +xtensa xtreg f9 0x0039 +xtensa xtreg f10 0x003a +xtensa xtreg f11 0x003b +xtensa xtreg f12 0x003c +xtensa xtreg f13 0x003d +xtensa xtreg f14 0x003e +xtensa xtreg f15 0x003f +xtensa xtreg fcr 0x03e8 +xtensa xtreg fsr 0x03e9 + +# TODO: update TIE state +xtensa xtreg accx_0 0x02f4 +xtensa xtreg accx_1 0x02f4 +xtensa xtreg qacc_h_0 0x02f4 +xtensa xtreg qacc_h_1 0x02f4 +xtensa xtreg qacc_h_2 0x02f4 +xtensa xtreg qacc_h_3 0x02f4 +xtensa xtreg qacc_h_4 0x02f4 +xtensa xtreg qacc_l_0 0x02f4 +xtensa xtreg qacc_l_1 0x02f4 +xtensa xtreg qacc_l_2 0x02f4 +xtensa xtreg qacc_l_3 0x02f4 +xtensa xtreg qacc_l_4 0x02f4 +xtensa xtreg sar_byte 0x02f4 +xtensa xtreg fft_bit_width 0x02f4 +xtensa xtreg ua_state_0 0x02f4 +xtensa xtreg ua_state_1 0x02f4 +xtensa xtreg ua_state_2 0x02f4 +xtensa xtreg ua_state_3 0x02f4 +xtensa xtreg q0 0x02f4 +xtensa xtreg q1 0x02f4 +xtensa xtreg q2 0x02f4 +xtensa xtreg q3 0x02f4 +xtensa xtreg q4 0x02f4 +xtensa xtreg q5 0x02f4 +xtensa xtreg q6 0x02f4 +xtensa xtreg q7 0x02f4 + +xtensa xtreg mmid 0x0259 +xtensa xtreg ibreakenable 0x0260 +xtensa xtreg memctl 0x0261 +xtensa xtreg atomctl 0x0263 +xtensa xtreg ddr 0x0268 +xtensa xtreg ibreaka0 0x0280 +xtensa xtreg ibreaka1 0x0281 +xtensa xtreg dbreaka0 0x0290 +xtensa xtreg dbreaka1 0x0291 +xtensa xtreg dbreakc0 0x02a0 +xtensa xtreg dbreakc1 0x02a1 +xtensa xtreg epc1 0x02b1 +xtensa xtreg epc2 0x02b2 +xtensa xtreg epc3 0x02b3 +xtensa xtreg epc4 0x02b4 +xtensa xtreg epc5 0x02b5 +xtensa xtreg epc6 0x02b6 +xtensa xtreg epc7 0x02b7 +xtensa xtreg depc 0x02c0 +xtensa xtreg eps2 0x02c2 +xtensa xtreg eps3 0x02c3 +xtensa xtreg eps4 0x02c4 +xtensa xtreg eps5 0x02c5 +xtensa xtreg eps6 0x02c6 +xtensa xtreg eps7 0x02c7 +xtensa xtreg excsave1 0x02d1 +xtensa xtreg excsave2 0x02d2 +xtensa xtreg excsave3 0x02d3 +xtensa xtreg excsave4 0x02d4 +xtensa xtreg excsave5 0x02d5 +xtensa xtreg excsave6 0x02d6 +xtensa xtreg excsave7 0x02d7 +xtensa xtreg cpenable 0x02e0 +xtensa xtreg interrupt 0x02e2 +xtensa xtreg intset 0x02e2 +xtensa xtreg intclear 0x02e3 +xtensa xtreg intenable 0x02e4 +xtensa xtreg vecbase 0x02e7 +xtensa xtreg exccause 0x02e8 +xtensa xtreg debugcause 0x02e9 +xtensa xtreg ccount 0x02ea +xtensa xtreg prid 0x02eb +xtensa xtreg icount 0x02ec +xtensa xtreg icountlevel 0x02ed +xtensa xtreg excvaddr 0x02ee +xtensa xtreg ccompare0 0x02f0 +xtensa xtreg ccompare1 0x02f1 +xtensa xtreg ccompare2 0x02f2 +xtensa xtreg misc0 0x02f4 +xtensa xtreg misc1 0x02f5 +xtensa xtreg misc2 0x02f6 +xtensa xtreg misc3 0x02f7 +xtensa xtreg pwrctl 0x2025 +xtensa xtreg pwrstat 0x2026 +xtensa xtreg eristat 0x2027 +xtensa xtreg cs_itctrl 0x2028 +xtensa xtreg cs_claimset 0x2029 +xtensa xtreg cs_claimclr 0x202a +xtensa xtreg cs_lockaccess 0x202b +xtensa xtreg cs_lockstatus 0x202c +xtensa xtreg cs_authstatus 0x202d +xtensa xtreg fault_info 0x203c +xtensa xtreg trax_id 0x203d +xtensa xtreg trax_control 0x203e +xtensa xtreg trax_status 0x203f +xtensa xtreg trax_data 0x2040 +xtensa xtreg trax_address 0x2041 +xtensa xtreg trax_pctrigger 0x2042 +xtensa xtreg trax_pcmatch 0x2043 +xtensa xtreg trax_delay 0x2044 +xtensa xtreg trax_memstart 0x2045 +xtensa xtreg trax_memend 0x2046 +xtensa xtreg pmg 0x2054 +xtensa xtreg pmpc 0x2055 +xtensa xtreg pm0 0x2056 +xtensa xtreg pm1 0x2057 +xtensa xtreg pmctrl0 0x2058 +xtensa xtreg pmctrl1 0x2059 +xtensa xtreg pmstat0 0x205a +xtensa xtreg pmstat1 0x205b +xtensa xtreg ocdid 0x205c +xtensa xtreg ocd_dcrclr 0x205d +xtensa xtreg ocd_dcrset 0x205e +xtensa xtreg ocd_dsr 0x205f +xtensa xtreg a0 0x0000 +xtensa xtreg a1 0x0001 +xtensa xtreg a2 0x0002 +xtensa xtreg a3 0x0003 +xtensa xtreg a4 0x0004 +xtensa xtreg a5 0x0005 +xtensa xtreg a6 0x0006 +xtensa xtreg a7 0x0007 +xtensa xtreg a8 0x0008 +xtensa xtreg a9 0x0009 +xtensa xtreg a10 0x000a +xtensa xtreg a11 0x000b +xtensa xtreg a12 0x000c +xtensa xtreg a13 0x000d +xtensa xtreg a14 0x000e +xtensa xtreg a15 0x000f +xtensa xtreg b0 0x0010 +xtensa xtreg b1 0x0011 +xtensa xtreg b2 0x0012 +xtensa xtreg b3 0x0013 +xtensa xtreg b4 0x0014 +xtensa xtreg b5 0x0015 +xtensa xtreg b6 0x0016 +xtensa xtreg b7 0x0017 +xtensa xtreg b8 0x0018 +xtensa xtreg b9 0x0019 +xtensa xtreg b10 0x001a +xtensa xtreg b11 0x001b +xtensa xtreg b12 0x001c +xtensa xtreg b13 0x001d +xtensa xtreg b14 0x001e +xtensa xtreg b15 0x001f diff --git a/tcl/target/xtensa-core-nxp_rt600.cfg b/tcl/target/xtensa-core-nxp_rt600.cfg new file mode 100644 index 0000000..abd961e --- /dev/null +++ b/tcl/target/xtensa-core-nxp_rt600.cfg @@ -0,0 +1,247 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# OpenOCD configuration file for Xtensa HiFi DSP in NXP RT600 target + + +# Core definition and ABI +xtensa xtdef LX +xtensa xtopt arnum 32 +xtensa xtopt windowed 1 + + +# Exception/Interrupt Options +xtensa xtopt exceptions 1 +xtensa xtopt hipriints 1 +xtensa xtopt intlevels 4 +xtensa xtopt excmlevel 2 + + +# Cache Options +xtensa xtmem icache 256 32768 4 +xtensa xtmem dcache 256 65536 4 1 + + +# Memory Options +xtensa xtmem iram 0x24020000 65536 +xtensa xtmem dram 0x24000000 65536 +xtensa xtmem sram 0x00000000 603979776 + + +# Memory Protection/Translation Options + + +# Debug Options +xtensa xtopt debuglevel 4 +xtensa xtopt ibreaknum 2 +xtensa xtopt dbreaknum 2 + + +# Core Registers +xtensa xtregs 208 +xtensa xtreg pc 0x0020 +xtensa xtreg ar0 0x0100 +xtensa xtreg ar1 0x0101 +xtensa xtreg ar2 0x0102 +xtensa xtreg ar3 0x0103 +xtensa xtreg ar4 0x0104 +xtensa xtreg ar5 0x0105 +xtensa xtreg ar6 0x0106 +xtensa xtreg ar7 0x0107 +xtensa xtreg ar8 0x0108 +xtensa xtreg ar9 0x0109 +xtensa xtreg ar10 0x010a +xtensa xtreg ar11 0x010b +xtensa xtreg ar12 0x010c +xtensa xtreg ar13 0x010d +xtensa xtreg ar14 0x010e +xtensa xtreg ar15 0x010f +xtensa xtreg ar16 0x0110 +xtensa xtreg ar17 0x0111 +xtensa xtreg ar18 0x0112 +xtensa xtreg ar19 0x0113 +xtensa xtreg ar20 0x0114 +xtensa xtreg ar21 0x0115 +xtensa xtreg ar22 0x0116 +xtensa xtreg ar23 0x0117 +xtensa xtreg ar24 0x0118 +xtensa xtreg ar25 0x0119 +xtensa xtreg ar26 0x011a +xtensa xtreg ar27 0x011b +xtensa xtreg ar28 0x011c +xtensa xtreg ar29 0x011d +xtensa xtreg ar30 0x011e +xtensa xtreg ar31 0x011f +xtensa xtreg lbeg 0x0200 +xtensa xtreg lend 0x0201 +xtensa xtreg lcount 0x0202 +xtensa xtreg sar 0x0203 +xtensa xtreg prefctl 0x0228 +xtensa xtreg windowbase 0x0248 +xtensa xtreg windowstart 0x0249 +xtensa xtreg configid0 0x02b0 +xtensa xtreg configid1 0x02d0 +xtensa xtreg ps 0x02e6 +xtensa xtreg threadptr 0x03e7 +xtensa xtreg br 0x0204 +xtensa xtreg scompare1 0x020c +xtensa xtreg acclo 0x0210 +xtensa xtreg acchi 0x0211 +xtensa xtreg m0 0x0220 +xtensa xtreg m1 0x0221 +xtensa xtreg m2 0x0222 +xtensa xtreg m3 0x0223 +xtensa xtreg expstate 0x03e6 +xtensa xtreg f64r_lo 0x03ea +xtensa xtreg f64r_hi 0x03eb +xtensa xtreg f64s 0x03ec +xtensa xtreg ae_ovf_sar 0x03f0 +xtensa xtreg ae_bithead 0x03f1 +xtensa xtreg ae_ts_fts_bu_bp 0x03f2 +xtensa xtreg ae_cw_sd_no 0x03f3 +xtensa xtreg ae_cbegin0 0x03f6 +xtensa xtreg ae_cend0 0x03f7 +xtensa xtreg ae_cbegin1 0x03f8 +xtensa xtreg ae_cend1 0x03f9 +xtensa xtreg aed0 0x1010 +xtensa xtreg aed1 0x1011 +xtensa xtreg aed2 0x1012 +xtensa xtreg aed3 0x1013 +xtensa xtreg aed4 0x1014 +xtensa xtreg aed5 0x1015 +xtensa xtreg aed6 0x1016 +xtensa xtreg aed7 0x1017 +xtensa xtreg aed8 0x1018 +xtensa xtreg aed9 0x1019 +xtensa xtreg aed10 0x101a +xtensa xtreg aed11 0x101b +xtensa xtreg aed12 0x101c +xtensa xtreg aed13 0x101d +xtensa xtreg aed14 0x101e +xtensa xtreg aed15 0x101f +xtensa xtreg u0 0x1020 +xtensa xtreg u1 0x1021 +xtensa xtreg u2 0x1022 +xtensa xtreg u3 0x1023 +xtensa xtreg aep0 0x1024 +xtensa xtreg aep1 0x1025 +xtensa xtreg aep2 0x1026 +xtensa xtreg aep3 0x1027 +xtensa xtreg fcr_fsr 0x1029 +xtensa xtreg mmid 0x0259 +xtensa xtreg ibreakenable 0x0260 +xtensa xtreg memctl 0x0261 +xtensa xtreg atomctl 0x0263 +xtensa xtreg ddr 0x0268 +xtensa xtreg ibreaka0 0x0280 +xtensa xtreg ibreaka1 0x0281 +xtensa xtreg dbreaka0 0x0290 +xtensa xtreg dbreaka1 0x0291 +xtensa xtreg dbreakc0 0x02a0 +xtensa xtreg dbreakc1 0x02a1 +xtensa xtreg epc1 0x02b1 +xtensa xtreg epc2 0x02b2 +xtensa xtreg epc3 0x02b3 +xtensa xtreg epc4 0x02b4 +xtensa xtreg epc5 0x02b5 +xtensa xtreg depc 0x02c0 +xtensa xtreg eps2 0x02c2 +xtensa xtreg eps3 0x02c3 +xtensa xtreg eps4 0x02c4 +xtensa xtreg eps5 0x02c5 +xtensa xtreg excsave1 0x02d1 +xtensa xtreg excsave2 0x02d2 +xtensa xtreg excsave3 0x02d3 +xtensa xtreg excsave4 0x02d4 +xtensa xtreg excsave5 0x02d5 +xtensa xtreg cpenable 0x02e0 +xtensa xtreg interrupt 0x02e2 +xtensa xtreg intset 0x02e2 +xtensa xtreg intclear 0x02e3 +xtensa xtreg intenable 0x02e4 +xtensa xtreg vecbase 0x02e7 +xtensa xtreg exccause 0x02e8 +xtensa xtreg debugcause 0x02e9 +xtensa xtreg ccount 0x02ea +xtensa xtreg prid 0x02eb +xtensa xtreg icount 0x02ec +xtensa xtreg icountlevel 0x02ed +xtensa xtreg excvaddr 0x02ee +xtensa xtreg ccompare0 0x02f0 +xtensa xtreg ccompare1 0x02f1 +xtensa xtreg misc0 0x02f4 +xtensa xtreg misc1 0x02f5 +xtensa xtreg pwrctl 0x2024 +xtensa xtreg pwrstat 0x2025 +xtensa xtreg eristat 0x2026 +xtensa xtreg cs_itctrl 0x2027 +xtensa xtreg cs_claimset 0x2028 +xtensa xtreg cs_claimclr 0x2029 +xtensa xtreg cs_lockaccess 0x202a +xtensa xtreg cs_lockstatus 0x202b +xtensa xtreg cs_authstatus 0x202c +xtensa xtreg pmg 0x203b +xtensa xtreg pmpc 0x203c +xtensa xtreg pm0 0x203d +xtensa xtreg pm1 0x203e +xtensa xtreg pmctrl0 0x203f +xtensa xtreg pmctrl1 0x2040 +xtensa xtreg pmstat0 0x2041 +xtensa xtreg pmstat1 0x2042 +xtensa xtreg ocdid 0x2043 +xtensa xtreg ocd_dcrclr 0x2044 +xtensa xtreg ocd_dcrset 0x2045 +xtensa xtreg ocd_dsr 0x2046 +xtensa xtreg a0 0x0000 +xtensa xtreg a1 0x0001 +xtensa xtreg a2 0x0002 +xtensa xtreg a3 0x0003 +xtensa xtreg a4 0x0004 +xtensa xtreg a5 0x0005 +xtensa xtreg a6 0x0006 +xtensa xtreg a7 0x0007 +xtensa xtreg a8 0x0008 +xtensa xtreg a9 0x0009 +xtensa xtreg a10 0x000a +xtensa xtreg a11 0x000b +xtensa xtreg a12 0x000c +xtensa xtreg a13 0x000d +xtensa xtreg a14 0x000e +xtensa xtreg a15 0x000f +xtensa xtreg b0 0x0010 +xtensa xtreg b1 0x0011 +xtensa xtreg b2 0x0012 +xtensa xtreg b3 0x0013 +xtensa xtreg b4 0x0014 +xtensa xtreg b5 0x0015 +xtensa xtreg b6 0x0016 +xtensa xtreg b7 0x0017 +xtensa xtreg b8 0x0018 +xtensa xtreg b9 0x0019 +xtensa xtreg b10 0x001a +xtensa xtreg b11 0x001b +xtensa xtreg b12 0x001c +xtensa xtreg b13 0x001d +xtensa xtreg b14 0x001e +xtensa xtreg b15 0x001f +xtensa xtreg psintlevel 0x2006 +xtensa xtreg psum 0x2007 +xtensa xtreg pswoe 0x2008 +xtensa xtreg psexcm 0x2009 +xtensa xtreg pscallinc 0x200a +xtensa xtreg psowb 0x200b +xtensa xtreg acc 0x200c +xtensa xtreg dbnum 0x2011 +xtensa xtreg ae_overflow 0x2014 +xtensa xtreg ae_sar 0x2015 +xtensa xtreg ae_cwrap 0x2016 +xtensa xtreg ae_bitptr 0x2017 +xtensa xtreg ae_bitsused 0x2018 +xtensa xtreg ae_tablesize 0x2019 +xtensa xtreg ae_first_ts 0x201a +xtensa xtreg ae_nextoffset 0x201b +xtensa xtreg ae_searchdone 0x201c +xtensa xtreg roundmode 0x201d +xtensa xtreg invalidflag 0x201e +xtensa xtreg divzeroflag 0x201f +xtensa xtreg overflowflag 0x2020 +xtensa xtreg underflowflag 0x2021 +xtensa xtreg inexactflag 0x2022 diff --git a/tcl/target/xtensa.cfg b/tcl/target/xtensa.cfg new file mode 100644 index 0000000..101e135 --- /dev/null +++ b/tcl/target/xtensa.cfg @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Target Support for Xtensa Processors +# + +set xtensa_ids { 0x120034e5 0x120134e5 + 0x209034e5 0x209134e5 0x209234e5 0x209334e5 0x209434e5 0x209534e5 0x209634e5 0x209734e5 + 0x20a034e5 0x20a134e5 0x20a234e5 0x20a334e5 0x20a434e5 0x20a534e5 0x20a634e5 0x20a734e5 0x20a834e5 + 0x20b034e5 } +set expected_xtensa_ids {} +foreach i $xtensa_ids { + lappend expected_xtensa_ids -expected-id $i +} + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xtensa +} + +if { [info exists CPUTAPID] } { + set _CPUTAPARGLIST "-expected-id $CPUTAPID" +} else { + set _CPUTAPARGLIST [join $expected_xtensa_ids] +} + +set _TARGETNAME $_CHIPNAME +set _CPU0NAME cpu +set _TAPNAME $_CHIPNAME.$_CPU0NAME + +if { [info exists XTENSA_DAP] } { + source [find target/swj-dp.tcl] + # SWD mode ignores the -irlen parameter + eval swj_newdap $_CHIPNAME cpu -irlen 4 $_CPUTAPARGLIST + dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + + set _TARGETNAME $_CHIPNAME.cpu + if { [info exists XTENSA_DAP_BASE] } { + # Specify fixed offset for accessing XDM via APB behind a DAP interface + target create $_TARGETNAME xtensa -dap $_CHIPNAME.dap -dbgbase $XTENSA_DAP_BASE + } else { + target create $_TARGETNAME xtensa -dap $_CHIPNAME.dap + } +} else { + # JTAG direct (without DAP) + eval jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 $_CPUTAPARGLIST + target create $_TARGETNAME xtensa -chain-position $_TAPNAME +} + +$_TARGETNAME configure -event reset-assert-post { soft_reset_halt } + +gdb_report_register_access_error enable diff --git a/tcl/target/zynq_7000.cfg b/tcl/target/zynq_7000.cfg index b4b6f9f..0272587 100644 --- a/tcl/target/zynq_7000.cfg +++ b/tcl/target/zynq_7000.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # # Xilinx Zynq-7000 All Programmable SoC # |