tcl: fix typo and spelling

Identified by checkpatch script from Linux kernel v5.7-rc1 using
the command
	find tcl/ -type f -exec ./tools/scripts/checkpatch.pl \
	-q --types TYPO_SPELLING --strict -f {} \;

Change-Id: I7b523f0ab5ec047ff167742a44c29984ac672cf4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5615
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins

9 files changed, 14 insertions, 14 deletions

diff --git a/tcl/target/aducm360.cfg b/tcl/target/aducm360.cfg
index caee965..b381728 100644
--- a/tcl/target/aducm360.cfg
+++ b/tcl/target/aducm360.cfg
@@ -10,7 +10,7 @@ if { [info exists CHIPNAME] } {
    set _CHIPNAME aducm360
 }
 
-# Endianess
+# Endianness
 if { [info exists ENDIAN] } {
    set _ENDIAN $ENDIAN
 } else {
diff --git a/tcl/target/at91rm9200.cfg b/tcl/target/at91rm9200.cfg
index 2e8c1e0..3d9a8d9 100644
--- a/tcl/target/at91rm9200.cfg
+++ b/tcl/target/at91rm9200.cfg
@@ -28,7 +28,7 @@ if { $_CPUTAPID == 0x15b0203f } {
    echo "- ERROR:                                              -"
    echo "- ERROR: In one position (0x05b0203f) it selects the  -"
    echo "- ERROR: ARM CPU, in the other position (0x1b0203f)   -"
-   echo "- ERROR: it selects boundry-scan not the ARM          -"
+   echo "- ERROR: it selects boundary-scan not the ARM         -"
    echo "- ERROR:                                              -"
    echo "-------------------------------------------------------"
 }
diff --git a/tcl/target/c100config.tcl b/tcl/target/c100config.tcl
index a72a2fa..53b2c5d 100644
--- a/tcl/target/c100config.tcl
+++ b/tcl/target/c100config.tcl
@@ -1,5 +1,5 @@
 
-# board(-config) specfic parameters file.
+# board(-config) specific parameters file.
 
 # set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
 proc config {label} {
diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl
index 9da3730..725ba70 100644
--- a/tcl/target/c100helper.tcl
+++ b/tcl/target/c100helper.tcl
@@ -15,7 +15,7 @@ proc helpC100 {} {
     echo "12) ooma_board_detect: will show which version of Telo you have"
     echo "13) setupDDR2:         will configure DDR2 controller, you must have PLLs configureg"
     echo "14) showDDR2:          will show DDR2 config registers"
-    echo "15) showWatchdog:      will show current regster config for watchdog"
+    echo "15) showWatchdog:      will show current register config for watchdog"
     echo "16) reboot:            will trigger watchdog and reboot Telo (hw reset)"
     echo "17) bootNOR:           will boot Telo from NOR"
     echo "18) setupUART0:        will configure UART0 for 115200 8N1, PLLs have to be confiured"
@@ -176,7 +176,7 @@ proc setupAmbaClk {} {
     mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF
     mmw $CLKCORE_AHB_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
     # wait for PLL to lock
-    echo "Wating for Amba PLL to lock"
+    echo "Waiting for Amba PLL to lock"
     while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 }
     # remove the internal PLL bypass
     mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
@@ -250,7 +250,7 @@ proc setupArmClk {} {
     mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF
     mmw $CLKCORE_ARM_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
     # wait for PLL to lock
-    echo "Wating for Amba PLL to lock"
+    echo "Waiting for Amba PLL to lock"
     while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 }
     # remove the internal PLL bypass
     mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
@@ -300,7 +300,7 @@ proc setupDDR2 {} {
 
     # Memory setup register
     mww $MEMORY_MAX_ADDR  [expr ($ddr_size - 1) + $MEMORY_BASE_ADDR]
-    # disbale ROM remap
+    # disable ROM remap
     mww $MEMORY_CR 0x0
     # Take DDR controller out of reset
     mmw $BLOCK_RESET_REG $DDR_RST 0x0
@@ -486,7 +486,7 @@ proc reboot {} {
     set TIMER_WDT_CURRENT_COUNT	[regs TIMER_WDT_CURRENT_COUNT]
 
     # allow the counter to count to high value  before triggering
-    # this is because regsiter writes are slow over JTAG and
+    # this is because register writes are slow over JTAG and
     # I don't want to miss the high_bound==curr_count condition
     mww $TIMER_WDT_HIGH_BOUND  0xffffff
     mww $TIMER_WDT_CURRENT_COUNT 0x0
@@ -494,7 +494,7 @@ proc reboot {} {
     adapter speed 100
     mww $TIMER_WDT_CONTROL 0x1
     # wait until the reset
-    echo -n "Wating for watchdog to trigger..."
+    echo -n "Waiting for watchdog to trigger..."
     #while {[mrw $TIMER_WDT_CONTROL] == 1} {
     #    echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
     #    sleep 1
diff --git a/tcl/target/dsp568013.cfg b/tcl/target/dsp568013.cfg
index c0c1df2..40fa3c2 100644
--- a/tcl/target/dsp568013.cfg
+++ b/tcl/target/dsp568013.cfg
@@ -35,7 +35,7 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME
 
 # Setup the interesting tap
-# Disable polling to be able to get idcode from core tap. If re enabled, can be re enabled, but it should be disabled to correctly unlock flash (operations requiere certain instruction to be in the IR register during reset, and polling would change this)
+# Disable polling to be able to get idcode from core tap. If re enabled, can be re enabled, but it should be disabled to correctly unlock flash (operations require certain instruction to be in the IR register during reset, and polling would change this)
 jtag configure $_CHIPNAME.chp -event setup "
      jtag tapenable $_TARGETNAME
      poll off
diff --git a/tcl/target/lpc2900.cfg b/tcl/target/lpc2900.cfg
index 5367787..523bc21 100644
--- a/tcl/target/lpc2900.cfg
+++ b/tcl/target/lpc2900.cfg
@@ -14,7 +14,7 @@ if { [info exists CPUTAPID] } {
 if { [info exists HAS_ETB] } {
 } else {
     # Set default (no ETB).
-    # Show a warning, because this should have been configured explicitely.
+    # Show a warning, because this should have been configured explicitly.
     set HAS_ETB 0
     # TODO: warning?
 }
diff --git a/tcl/target/lpc3131.cfg b/tcl/target/lpc3131.cfg
index 185c0aa..d6f2cdb 100644
--- a/tcl/target/lpc3131.cfg
+++ b/tcl/target/lpc3131.cfg
@@ -22,7 +22,7 @@ if { [info exists CPUTAPID] } {
 }
 
 # Scan Tap
-# Wired to seperate STDO pin on the lpc3131, externally muxed to TDO on ea3131 module 
+# Wired to separate STDO pin on the lpc3131, externally muxed to TDO on ea3131 module
 # JTAGSEL pin must be 0 to activate, which reassigns arm tdo to a pass through.
 if { [info exists SJCTAPID] } {
    set _SJCTAPID $SJCTAPID
diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg
index fb591c2..3cab4d1 100644
--- a/tcl/target/stellaris.cfg
+++ b/tcl/target/stellaris.cfg
@@ -164,7 +164,7 @@ $_TARGETNAME configure -event reset-start {
 	} else {
 		if {![using_hla]} {
 		   # Tempest and Firestorm default to using NVIC VECTRESET
-		   # peripherals will need reseting manually, see proc reset_peripherals
+		   # peripherals will need resetting manually, see proc reset_peripherals
 		   cortex_m reset_config vectreset
 		}
 		# reset peripherals, based on code in
diff --git a/tcl/target/ti_cc3220sf.cfg b/tcl/target/ti_cc3220sf.cfg
index 3e758e6..74269aa 100644
--- a/tcl/target/ti_cc3220sf.cfg
+++ b/tcl/target/ti_cc3220sf.cfg
@@ -25,7 +25,7 @@ proc ocd_process_reset_inner { MODE } {
 
 	soft_reset_halt
 
-	# Intialize MSP, PSP, and PC from vector table at flash 0x01000800
+	# Initialize MSP, PSP, and PC from vector table at flash 0x01000800
 	mem2array boot 32 0x01000800 2
 
 	reg msp $boot(0)