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| author | Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> | 2024-03-28 12:06:34 +0300 |
|---|---|---|
| committer | Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> | 2024-03-28 12:40:33 +0300 |
| commit | 46e7507e48993b3abe0cca98f980adfcce86e551 (patch) | |
| tree | ad72d2bb3cccf293d4640cb40855d59933368657 /tcl/target | |
| parent | 722cef1ae0ec55ee7aa47e60acafaa787be16b32 (diff) | |
| parent | a35e254c5383008cdacf7838a777f7f17af5eeb1 (diff) | |
| download | riscv-openocd-46e7507e48993b3abe0cca98f980adfcce86e551.zip riscv-openocd-46e7507e48993b3abe0cca98f980adfcce86e551.tar.gz riscv-openocd-46e7507e48993b3abe0cca98f980adfcce86e551.tar.bz2 | |
Merge up to a35e254c5383008cdacf7838a777f7f17af5eeb1 from upstream
Checkpatch-ignore: MACRO_ARG_REUSE, MACRO_ARG_PRECEDENCE
Change-Id: Icd10f44d162054f8f32019a579ccbdda2cee7a91
Diffstat (limited to 'tcl/target')
| -rw-r--r-- | tcl/target/nrf51.cfg | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/tcl/target/nrf51.cfg b/tcl/target/nrf51.cfg index 48c2715..3781ecc 100644 --- a/tcl/target/nrf51.cfg +++ b/tcl/target/nrf51.cfg @@ -45,13 +45,11 @@ if {![using_hla]} { cortex_m reset_config sysresetreq } -flash bank $_CHIPNAME.flash nrf51 0x00000000 0 1 1 $_TARGETNAME -flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME +flash bank $_CHIPNAME.flash nrf5 0x00000000 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 0 0 $_TARGETNAME -# # The chip should start up from internal 16Mhz RC, so setting adapter # clock to 1Mhz should be OK -# adapter speed 1000 proc enable_all_ram {} { @@ -60,4 +58,4 @@ proc enable_all_ram {} { # resetting we enable all banks via the RAMON register mww 0x40000524 0xF } -$_TARGETNAME configure -event reset-end { enable_all_ram } +$_TARGETNAME configure -event reset-init { enable_all_ram } |