Merge commit 'd4575b647a3603200a9bb4a784d170f792ab88d0' into from_upstream

Change-Id: Iaa299c50b338089f1b3b7ff7d89fad39ac20a7c1

1 files changed, 87 insertions, 30 deletions

diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 1cd85ee..23825b8 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -2,24 +2,30 @@
 # Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
 #
 # Texas Instruments K3 devices:
+# * AM243: https://www.ti.com/lit/pdf/spruim2
+#  Has 4 R5 Cores, M4F and an M3
+# * AM263: https://www.ti.com/lit/pdf/spruj17
+#  Has 4 R5 Cores and an M3
+# * AM273: https://www.ti.com/lit/pdf/spruiu0
+#  Has 2 R5 Cores and an M3
+# * AM625: https://www.ti.com/lit/pdf/spruiv7a
+#  Has 4 ARMV8 Cores and 1 R5 Core and an M4F
+# * AM62A7: https://www.ti.com/lit/pdf/spruj16a
+#  Has 4 ARMV8 Cores and 2 R5 Cores
+# * AM62P: https://www.ti.com/lit/pdf/spruj83
+#  Has 4 ARMV8 Cores and 2 R5 Cores
+# * AM642: https://www.ti.com/lit/pdf/spruim2
+#  Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
 # * AM654x: https://www.ti.com/lit/pdf/spruid7
 #  Has 4 ARMV8 Cores and 2 R5 Cores and an M3
-# * J721E: https://www.ti.com/lit/pdf/spruil1
-#  Has 2 ARMV8 Cores and 6 R5 Cores and an M3
 # * J7200: https://www.ti.com/lit/pdf/spruiu1
 #  Has 2 ARMV8 Cores and 4 R5 Cores and an M3
+# * J721E: https://www.ti.com/lit/pdf/spruil1
+#  Has 2 ARMV8 Cores and 6 R5 Cores and an M3
 # * J721S2: https://www.ti.com/lit/pdf/spruj28
 #  Has 2 ARMV8 Cores and 6 R5 Cores and an M4F
 # * J784S4/AM69: http://www.ti.com/lit/zip/spruj52
 #  Has 8 ARMV8 Cores and 8 R5 Cores
-# * AM642: https://www.ti.com/lit/pdf/spruim2
-#  Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
-# * AM625: https://www.ti.com/lit/pdf/spruiv7a
-#  Has 4 ARMV8 Cores and 1 R5 Core and an M4F
-# * AM62a7: https://www.ti.com/lit/pdf/spruj16a
-#  Has 4 ARMV8 Cores and 2 R5 Cores
-# * AM62P: https://www.ti.com/lit/pdf/spruj83
-#  Has 4 ARMV8 Cores and 2 R5 Cores
 #
 
 source [find target/swj-dp.tcl]
@@ -44,6 +50,7 @@ set CM3_CTIBASE		{0x3C016000}
 
 # sysctrl power-ap unlock offsets
 set _sysctrl_ap_unlock_offsets {0xf0 0x44}
+set _sysctrl_ap_num 7
 
 # All the ARMV8s are the next processors.
 #		   CL0,CORE0  CL0,CORE1  CL1,CORE0  CL1,CORE1
@@ -55,6 +62,7 @@ set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
 set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
+set _r5_ap_num 1
 
 # Finally an General Purpose(GP) MCU
 set CM4_CTIBASE		{0x20001000}
@@ -64,8 +72,46 @@ set _gp_mcu_cores 0
 # General Purpose MCU power-ap unlock offsets
 set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
 
+# Generic mem-ap port number
+set _mem_ap_num 2
+
 # Set configuration overrides for each SOC
 switch $_soc {
+	am263 {
+		set _K3_DAP_TAPID 0x2bb7d02f
+
+		# Mem-ap port
+		set _mem_ap_num 6
+
+		# AM263 has 0 ARMV8 CPUs
+		set _armv8_cores 0
+
+		# AM263 has 2 cluster of 2 R5s cores.
+		set _r5_cores 4
+		set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
+		set R5_DBGBASE {0x90030000 0x90032000 0x90050000 0x90052000}
+		set R5_CTIBASE {0x90038000 0x90039000 0x90058000 0x90059000}
+		set _r5_ap_num 5
+	}
+	am273 {
+		set _K3_DAP_TAPID 0x1bb6a02f
+
+		# Mem-ap port
+		set _mem_ap_num 6
+
+		# system controller is on AP0
+		set _sysctrl_ap_num 0
+
+		# AM273 has 0 ARMV8 CPUs
+		set _armv8_cores 0
+
+		# AM273 has 1 cluster of 2 R5s cores.
+		set _r5_cores 2
+		set R5_NAMES {main0_r5.0 main0_r5.1}
+		set R5_DBGBASE {0x90030000 0x90032000}
+		set R5_CTIBASE {0x90038000 0x90039000}
+		set _r5_ap_num 5
+	}
 	am654 {
 		set _K3_DAP_TAPID 0x0bb5a02f
 
@@ -80,6 +126,7 @@ switch $_soc {
 		# Sysctrl power-ap unlock offsets
 		set _sysctrl_ap_unlock_offsets {0xf0 0x50}
 	}
+	am243 -
 	am642 {
 		set _K3_DAP_TAPID 0x0bb3802f
 
@@ -97,6 +144,12 @@ switch $_soc {
 
 		# M4 processor
 		set _gp_mcu_cores 1
+
+		# Overrides for am243
+		if { "$_soc" == "am243" } {
+			# Uses the same JTAG ID
+			set _armv8_cores 0
+		}
 	}
 	am625 {
 		set _K3_DAP_TAPID 0x0bb7e02f
@@ -266,9 +319,11 @@ set _TARGETNAME $_CHIPNAME.cpu
 set _CTINAME $_CHIPNAME.cti
 
 # sysctrl is always present
-cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]
+cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap \
+	-ap-num $_sysctrl_ap_num -baseaddr [lindex $CM3_CTIBASE 0]
 
-target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine \
+target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap \
+	-ap-num $_sysctrl_ap_num -defer-examine \
 	-rtos [_get_rtos_type_for_cpu $_TARGETNAME.sysctrl]
 
 $_TARGETNAME.sysctrl configure -event reset-assert { }
@@ -334,34 +389,36 @@ for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
 	}
 }
 
-# Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
-set _armv8_up_cmd "$_armv8_cpu_name"_up
-# Available if V8_SMP_DEBUG is set to non-zero value
-set _armv8_smp_cmd "$_armv8_cpu_name"_smp
+if { $_armv8_cores > 0 } {
+	# Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
+	set _armv8_up_cmd "$_armv8_cpu_name"_up
+	# Available if V8_SMP_DEBUG is set to non-zero value
+	set _armv8_smp_cmd "$_armv8_cpu_name"_smp
 
-if { $_v8_smp_debug == 0 } {
-	proc $_armv8_up_cmd { args } {
-		foreach _core $args {
-			targets $_core
-			_cpu_no_smp_up
+	if { $_v8_smp_debug == 0 } {
+		proc $_armv8_up_cmd { args } {
+			foreach _core $args {
+				targets $_core
+				_cpu_no_smp_up
+			}
 		}
+	} else {
+		proc $_armv8_smp_cmd { args } {
+			_armv8_smp_up
+		}
+		# Declare SMP
+		target smp {*}$_v8_smp_targets
 	}
-} else {
-	proc $_armv8_smp_cmd { args } {
-		_armv8_smp_up
-	}
-	# Declare SMP
-	target smp {*}$_v8_smp_targets
 }
 
 for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
 	set _r5_name [lindex $R5_NAMES $_core]
-	cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num 1 \
+	cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num $_r5_ap_num \
 		-baseaddr [lindex $R5_CTIBASE $_core]
 
 	# inactive core examination will fail - wait till startup of additional core
 	target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
-		-dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine \
+		-dbgbase [lindex $R5_DBGBASE $_core] -ap-num $_r5_ap_num -defer-examine \
 		-rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_r5_name]
 
 	$_TARGETNAME.$_r5_name configure -event gdb-attach {
@@ -419,5 +476,5 @@ if { 0 == [string compare [adapter name] dmem ] } {
 	}
 } else {
 	# AXI AP access port for SoC address map
-	target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num 2
+	target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num $_mem_ap_num
 }