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| author | Daniel Anselmi <danselmi@gmx.ch> | 2022-11-17 02:01:04 +0100 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2023-07-08 18:01:37 +0000 |
| commit | d654e523babd26fc8d62a8fa0814c9de84826e0d (patch) | |
| tree | 1f5b05b1f25180a5b7307d35cea10bb58f1bfedc /tcl/target/zynq_7000.cfg | |
| parent | 9cb09f8cfe4c041333f70be5a6b44a5d7c5be4e0 (diff) | |
| download | riscv-openocd-d654e523babd26fc8d62a8fa0814c9de84826e0d.zip riscv-openocd-d654e523babd26fc8d62a8fa0814c9de84826e0d.tar.gz riscv-openocd-d654e523babd26fc8d62a8fa0814c9de84826e0d.tar.bz2 | |
tcl/cpld: add config files for more xilinx fpga families
Use configurable virtex pld driver to add support for more
xilinx fpga families.
Change-Id: Iff10c8c511787734fa289bdba15f03131d51e071
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: https://review.openocd.org/c/openocd/+/7352
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Diffstat (limited to 'tcl/target/zynq_7000.cfg')
| -rw-r--r-- | tcl/target/zynq_7000.cfg | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tcl/target/zynq_7000.cfg b/tcl/target/zynq_7000.cfg index 014c428..593abd7 100644 --- a/tcl/target/zynq_7000.cfg +++ b/tcl/target/zynq_7000.cfg @@ -47,6 +47,7 @@ ${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit" ${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit" pld create zynq_pl.pld virtex2 -chain-position zynq_pl.bs -no_jstart +virtex2 set_user_codes $zynq_pl.pld 0x02 0x03 0x22 0x23 set XC7_JSHUTDOWN 0x0d set XC7_JPROGRAM 0x0b |