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| author | Jacek Wuwer <jacekmw8@gmail.com> | 2021-04-06 20:08:11 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2022-02-14 15:12:10 +0000 |
| commit | f998a2aaf19c14b46fd7f7dd50607a0904f40bd3 (patch) | |
| tree | e9f04aeb797d8e831de62a8fa5805eec9ebc24bb /tcl/target/vd_riscv.cfg | |
| parent | 2a2636f138dc40be3fff06cb7bf1f126d906e0a1 (diff) | |
| download | riscv-openocd-f998a2aaf19c14b46fd7f7dd50607a0904f40bd3.zip riscv-openocd-f998a2aaf19c14b46fd7f7dd50607a0904f40bd3.tar.gz riscv-openocd-f998a2aaf19c14b46fd7f7dd50607a0904f40bd3.tar.bz2 | |
Cadence virtual debug interface (vdebug) integration
Change-Id: I1bc105b3addc3f34161c2356c482ff3011e3f2cc
Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6097
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'tcl/target/vd_riscv.cfg')
| -rw-r--r-- | tcl/target/vd_riscv.cfg | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/tcl/target/vd_riscv.cfg b/tcl/target/vd_riscv.cfg new file mode 100644 index 0000000..b42b25a --- /dev/null +++ b/tcl/target/vd_riscv.cfg @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# RISCV core + +if {![info exists _HARTID]} { + set _HARTID 0x00 +} +if {![info exists _CHIPNAME]} { + set _CHIPNAME riscv +} +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid $_HARTID + +riscv set_reset_timeout_sec 120 +riscv set_command_timeout_sec 120 +# prefer to use sba for system bus access +riscv set_prefer_sba on |