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author | Antonio Borneo <borneo.antonio@gmail.com> | 2020-10-12 00:12:05 +0200 |
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committer | Antonio Borneo <borneo.antonio@gmail.com> | 2021-03-10 21:33:53 +0000 |
commit | c945d6e6160598894319860a92b602a192c2c268 (patch) | |
tree | 933b6a269085f99f2aab6a80352ebe18c96cedcc /tcl/target/stm32mp15x.cfg | |
parent | 184724d14e120a9901fedfe05692bcd270f5eb57 (diff) | |
download | riscv-openocd-c945d6e6160598894319860a92b602a192c2c268.zip riscv-openocd-c945d6e6160598894319860a92b602a192c2c268.tar.gz riscv-openocd-c945d6e6160598894319860a92b602a192c2c268.tar.bz2 |
tcl/target: start using the new TPIU/SWO support
Create the TPIU and SWO device in target config file.
Replace the target event 'trace-config' with the TPIU/SWO event
'post-enable'.
Extend the existing code in the event handler to properly set the
gpio mode and speed to permit synchronous trace.
This patch is not exhaustive of all the targets that have SWO, but
has to be considered as an initial example.
Change-Id: If4bbf364c0d2aef3ae49951e76507a3b1cfd58e7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5859
Tested-by: jenkins
Reviewed-by: Adrian M Negreanu <adrian.negreanu@nxp.com>
Diffstat (limited to 'tcl/target/stm32mp15x.cfg')
-rw-r--r-- | tcl/target/stm32mp15x.cfg | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg index 4a8bc86..1b2ae7d 100644 --- a/tcl/target/stm32mp15x.cfg +++ b/tcl/target/stm32mp15x.cfg @@ -64,6 +64,9 @@ cti create $_CHIPNAME.cti.cpu0 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D800 cti create $_CHIPNAME.cti.cpu1 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D9000 cti create $_CHIPNAME.cti.cm4 -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE0043000 +swo create $_CHIPNAME.swo -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0083000 +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0093000 + # interface does not work while srst is asserted # this is target specific, valid for every board # Errata "2.3.5 Incorrect reset of glitch-free kernel clock switch" requires @@ -108,9 +111,13 @@ proc detect_cpu1 {} { if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine} } +proc rcc_enable_traceclk {} { + $::_CHIPNAME.ap2 mww 0x5000080c 0x301 +} + # FIXME: most of handler below will be removed once reset framework get merged $_CHIPNAME.ap1 configure -event reset-deassert-pre {adapter deassert srst deassert trst;dap init;catch {$::_CHIPNAME.dap apid 1}} -$_CHIPNAME.ap2 configure -event reset-deassert-pre {dbgmcu_enable_debug} +$_CHIPNAME.ap2 configure -event reset-deassert-pre {dbgmcu_enable_debug;rcc_enable_traceclk} $_CHIPNAME.cpu0 configure -event reset-deassert-pre {$::_CHIPNAME.cpu0 arp_examine} $_CHIPNAME.cpu1 configure -event reset-deassert-pre {$::_CHIPNAME.cpu1 arp_examine allow-defer} $_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0} @@ -118,4 +125,4 @@ $_CHIPNAME.cm4 configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_exami $_CHIPNAME.ap1 configure -event examine-start {dap init} $_CHIPNAME.ap2 configure -event examine-start {dbgmcu_enable_debug} $_CHIPNAME.cpu0 configure -event examine-end {detect_cpu1} -$_CHIPNAME.ap2 configure -event examine-end {$::_CHIPNAME.cm4 arp_examine} +$_CHIPNAME.ap2 configure -event examine-end {rcc_enable_traceclk;$::_CHIPNAME.cm4 arp_examine} |