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| author | Antonio Borneo <borneo.antonio@gmail.com> | 2020-10-12 00:12:05 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2021-03-10 21:33:53 +0000 |
| commit | c945d6e6160598894319860a92b602a192c2c268 (patch) | |
| tree | 933b6a269085f99f2aab6a80352ebe18c96cedcc /tcl/target/stm32h7x.cfg | |
| parent | 184724d14e120a9901fedfe05692bcd270f5eb57 (diff) | |
| download | riscv-openocd-c945d6e6160598894319860a92b602a192c2c268.zip riscv-openocd-c945d6e6160598894319860a92b602a192c2c268.tar.gz riscv-openocd-c945d6e6160598894319860a92b602a192c2c268.tar.bz2 | |
tcl/target: start using the new TPIU/SWO support
Create the TPIU and SWO device in target config file.
Replace the target event 'trace-config' with the TPIU/SWO event
'post-enable'.
Extend the existing code in the event handler to properly set the
gpio mode and speed to permit synchronous trace.
This patch is not exhaustive of all the targets that have SWO, but
has to be considered as an initial example.
Change-Id: If4bbf364c0d2aef3ae49951e76507a3b1cfd58e7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5859
Tested-by: jenkins
Reviewed-by: Adrian M Negreanu <adrian.negreanu@nxp.com>
Diffstat (limited to 'tcl/target/stm32h7x.cfg')
| -rw-r--r-- | tcl/target/stm32h7x.cfg | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg index 8258e50..26d0d93 100644 --- a/tcl/target/stm32h7x.cfg +++ b/tcl/target/stm32h7x.cfg @@ -77,6 +77,8 @@ if {![using_hla]} { # STM32H7 provides an APB-AP at access port 2, which allows the access to # the debug and trace features on the system APB System Debug Bus (APB-D). target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2 + swo create $_CHIPNAME.swo -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00E3000 + tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00F5000 } target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0 @@ -178,13 +180,20 @@ $_CHIPNAME.cpu0 configure -event examine-end { stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0 # DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2 stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0 -} -$_CHIPNAME.cpu0 configure -event trace-config { - # Set TRACECLKEN; TRACE_MODE is set to async; when using sync - # change this value accordingly to configure trace pins - # assignment + # Enable clock for tracing + # DBGMCU_CR |= TRACECLKEN stm32h7x_dbgmcu_mmw 0x004 0x00100000 0 + + # RM0399 (id 0x450) M7+M4 with SWO Funnel + # RM0433 (id 0x450) M7 with SWO Funnel + # RM0455 (id 0x480) M7 without SWO Funnel + # RM0468 (id 0x483) M7 without SWO Funnel + # Enable CM7 and CM4 slave ports in SWO trace Funnel + # Works ok also on devices single core and without SWO funnel + # Hack, use stm32h7x_dbgmcu_mmw with big offset to control SWTF + # SWTF_CTRL |= ENS0 | ENS1 + stm32h7x_dbgmcu_mmw 0x3000 0x00000003 0 } $_CHIPNAME.cpu0 configure -event reset-init { |