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author | Alexandre Torgue <alexandre.torgue@st.com> | 2017-11-13 17:00:58 +0100 |
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committer | Spencer Oliver <spen@spen-soft.co.uk> | 2017-12-06 21:29:41 +0000 |
commit | 6090a5b158ad212a54510f061226ca58155b51fe (patch) | |
tree | ff1a45c07a05269f65021a9677be3439a5ce650f /tcl/target/stm32h7x.cfg | |
parent | 6a66cccbad7e51ac1b3ea929ab0c86dd02617797 (diff) | |
download | riscv-openocd-6090a5b158ad212a54510f061226ca58155b51fe.zip riscv-openocd-6090a5b158ad212a54510f061226ca58155b51fe.tar.gz riscv-openocd-6090a5b158ad212a54510f061226ca58155b51fe.tar.bz2 |
Add STM32H7 config files
Add 2 target files:
-stm32h7x.cfg
-stm32h7x_dual_bank.cfg
Add 2 config files for:
-STM32H743zi-nucleo bord
-STM32H743i and STM32H753i eval boards.
Change-Id: I2aae2c5acff4f3ff8e1bf232fda5a11a87f71703
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Reviewed-on: http://openocd.zylin.com/4182
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'tcl/target/stm32h7x.cfg')
-rw-r--r-- | tcl/target/stm32h7x.cfg | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg new file mode 100644 index 0000000..02dbed4 --- /dev/null +++ b/tcl/target/stm32h7x.cfg @@ -0,0 +1,93 @@ +# script for stm32h7x family + +# +# stm32h7 devices support both JTAG and SWD transports. +# +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32h7x +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +# By default use 64kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x10000 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + set _CPUTAPID 0x6ba00477 + } { + set _CPUTAPID 0x6ba02477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +if {[using_jtag]} { + swj_newdap $_CHIPNAME bs -irlen 5 +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32h7x 0x08000000 0 0 0 $_TARGETNAME + +# Clock after reset is HSI at 64 MHz, no need of PLL +adapter_khz 1800 + +adapter_nsrst_delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +# use hardware reset, connect under reset +reset_config srst_only srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +$_TARGETNAME configure -event examine-end { + # Enable D3 and D1 DBG clocks + # DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN + mmw 0x5C001004 0x00600000 0 + + # Enable debug during low power modes (uses more power) + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3 & D1 Domains + mmw 0x5C001004 0x00000187 0 + + # Stop watchdog counters during halt + # DBGMCU_APB3FZ1 |= WWDG1 + mmw 0x5C001034 0x00000040 0 + # DBGMCU_APB4FZ1 |= WDGLSD1 + mmw 0x5C001054 0x00040000 0 +} + +$_TARGETNAME configure -event trace-config { + # Set TRACECLKEN; TRACE_MODE is set to async; when using sync + # change this value accordingly to configure trace pins + # assignment + mmw 0x5C001004 0x00100000 0 +} + +$_TARGETNAME configure -event reset-init { + # Clock after reset is HSI at 64 MHz, no need of PLL + adapter_khz 4000 +} |