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authorUwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>2015-01-09 10:53:30 +0100
committerFreddie Chopin <freddie.chopin@gmail.com>2015-11-12 15:24:19 +0000
commitd8ac9d5ac559aa6aaf6ef8cf6f704c6e6b75da3a (patch)
treecdfe179f7325f4ce97a4f72eb800e12edda647fa /tcl/target/stm32f4x.cfg
parentc4b8c74140bc03d376efe919d8b81231dc5a0700 (diff)
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tcl: Add default hooks for STM32F4x
Set up PLL and increase clock at reset init. Change-Id: I611bc6fb7c0c5afd8ed3f4ad8e64f3c7b981d31c Signed-off-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> Reviewed-on: http://openocd.zylin.com/2609 Tested-by: jenkins Reviewed-by: RĂ©mi PRUD'HOMME <prudhomme.remi@gmail.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Diffstat (limited to 'tcl/target/stm32f4x.cfg')
-rw-r--r--tcl/target/stm32f4x.cfg14
1 files changed, 14 insertions, 0 deletions
diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg
index 9aadf62..c7f6ee8 100644
--- a/tcl/target/stm32f4x.cfg
+++ b/tcl/target/stm32f4x.cfg
@@ -92,6 +92,7 @@ if {![using_hla]} {
}
$_TARGETNAME configure -event examine-end {
+ # Enable debug during low power modes (uses more power)
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0
@@ -106,3 +107,16 @@ $_TARGETNAME configure -event trace-config {
# assignment
mmw 0xE0042004 0x00000020 0
}
+
+$_TARGETNAME configure -event reset-init {
+ # Configure PLL to boost clock to HSI x 4 (64 MHz)
+ mww 0x40023804 0x08012008 ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)
+ mww 0x40023C00 0x00000102 ;# FLASH_ACR = PRFTBE | 2(Latency)
+ mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
+ sleep 10 ;# Wait for PLL to lock
+ mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2
+ mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
+
+ # Boost JTAG frequency
+ adapter_khz 8000
+}