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| author | Christopher Head <chead@zaber.com> | 2018-09-19 16:20:26 -0700 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2018-09-27 16:13:06 +0100 |
| commit | 6823a97beb706a5a3a4b7f813d33a7f3faadf2f0 (patch) | |
| tree | 8ba72a354432d9c2ef3d3a1cf88b440c96c43abb /tcl/target/atsamv.cfg | |
| parent | bdef93520a4721e1ed4ac4675476772fab064896 (diff) | |
| download | riscv-openocd-6823a97beb706a5a3a4b7f813d33a7f3faadf2f0.zip riscv-openocd-6823a97beb706a5a3a4b7f813d33a7f3faadf2f0.tar.gz riscv-openocd-6823a97beb706a5a3a4b7f813d33a7f3faadf2f0.tar.bz2 | |
target/atsamv: make APCSW cacheable
Change-Id: Ic00d3192642c682f370a6f7f8b70ae29744eb746
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4678
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'tcl/target/atsamv.cfg')
| -rw-r--r-- | tcl/target/atsamv.cfg | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/tcl/target/atsamv.cfg b/tcl/target/atsamv.cfg index d1f8454..1d026aa 100644 --- a/tcl/target/atsamv.cfg +++ b/tcl/target/atsamv.cfg @@ -50,3 +50,10 @@ if {![using_hla]} { set _FLASHNAME $_CHIPNAME.flash flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME +# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal +# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3 +# makes the data access cacheable. This allows reading and writing data in the +# CPU cache from the debugger, which is far more useful than going straight to +# RAM when operating on typical variables, and is generally no worse when +# operating on special memory locations. +$_CHIPNAME.dap apcsw 0x08000000 0x08000000 |