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| author | Aurelien Jacobs <aurel@gnuage.org> | 2011-10-17 15:19:24 +0200 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2011-11-08 08:07:22 +0000 |
| commit | ac813a666ab7717b497d2510197bf544adbe31be (patch) | |
| tree | 8fdeacd73401c9873775fbc3b6c6a40d32012c92 /tcl/target/at91sam7x512.cfg | |
| parent | 6fa4c5a456e27ed1446b08a590c0494199c95c8a (diff) | |
| download | riscv-openocd-ac813a666ab7717b497d2510197bf544adbe31be.zip riscv-openocd-ac813a666ab7717b497d2510197bf544adbe31be.tar.gz riscv-openocd-ac813a666ab7717b497d2510197bf544adbe31be.tar.bz2 | |
at91sam7: add a new target config file for at91sam7x512
The main difference with at91sam7x256 is the declaration of the second
bank of flash.
Change-Id: I87a20dcbb639b797799139ccf46cc73934fa3b9e
Signed-off-by: Aurelien Jacobs <aurel@gnuage.org>
Reviewed-on: http://openocd.zylin.com/173
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'tcl/target/at91sam7x512.cfg')
| -rw-r--r-- | tcl/target/at91sam7x512.cfg | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/tcl/target/at91sam7x512.cfg b/tcl/target/at91sam7x512.cfg new file mode 100644 index 0000000..9677eca --- /dev/null +++ b/tcl/target/at91sam7x512.cfg @@ -0,0 +1,51 @@ +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config srst_only srst_pulls_trst + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME sam7x512 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x3f0f0f0f +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi + +$_TARGETNAME configure -event reset-init { + # disable watchdog + mww 0xfffffd44 0x00008000 + # enable user reset + mww 0xfffffd08 0xa5000001 + # CKGR_MOR : enable the main oscillator + mww 0xfffffc20 0x00000601 + sleep 10 + # CKGR_PLLR: 96.1097 MHz + mww 0xfffffc2c 0x00481c0e + sleep 10 + # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz + mww 0xfffffc30 0x00000007 + sleep 10 + # MC_FMR: flash mode (FWS=1,FMCN=60) + mww 0xffffff60 0x003c0100 + sleep 100 +} + +$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0 + +#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>] +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME.0 at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432 +flash bank $_FLASHNAME.1 at91sam7 0 0 0 0 $_TARGETNAME 1 0 0 0 0 0 0 18432 |