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| author | Antonio Borneo <borneo.antonio@gmail.com> | 2022-06-12 23:51:51 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2022-06-24 21:54:12 +0000 |
| commit | 573a39b36cf133bb7403b12337301a5616112f1a (patch) | |
| tree | a10eca7bc224d727bddb75a62f83757dba26b568 /tcl/fpga | |
| parent | 3bccc77999175494ceb534c172475e509ff99189 (diff) | |
| download | riscv-openocd-573a39b36cf133bb7403b12337301a5616112f1a.zip riscv-openocd-573a39b36cf133bb7403b12337301a5616112f1a.tar.gz riscv-openocd-573a39b36cf133bb7403b12337301a5616112f1a.tar.bz2 | |
tcl: add SPDX tag
For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl | while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: Ief3da306a6e1978de7dfb8f552f9ff23151f9944
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7030
Tested-by: jenkins
Diffstat (limited to 'tcl/fpga')
| -rw-r--r-- | tcl/fpga/altera-10m50.cfg | 2 | ||||
| -rw-r--r-- | tcl/fpga/altera-ep3c10.cfg | 2 | ||||
| -rw-r--r-- | tcl/fpga/xilinx-dna.cfg | 2 | ||||
| -rw-r--r-- | tcl/fpga/xilinx-xadc.cfg | 2 |
4 files changed, 8 insertions, 0 deletions
diff --git a/tcl/fpga/altera-10m50.cfg b/tcl/fpga/altera-10m50.cfg index d5af710..1937cb4 100644 --- a/tcl/fpga/altera-10m50.cfg +++ b/tcl/fpga/altera-10m50.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # see MAX 10 FPGA Device Architecture # Table 3-1: IDCODE Information for MAX 10 Devices # Intel MAX 10M02 0x31810dd diff --git a/tcl/fpga/altera-ep3c10.cfg b/tcl/fpga/altera-ep3c10.cfg index 6e8962a..7c231f9 100644 --- a/tcl/fpga/altera-ep3c10.cfg +++ b/tcl/fpga/altera-ep3c10.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Altera Cyclone III EP3C10 # see Cyclone III Device Handbook, Volume 1; # Table 14–5. 32-Bit Cyclone III Device IDCODE diff --git a/tcl/fpga/xilinx-dna.cfg b/tcl/fpga/xilinx-dna.cfg index a805673..56f8c14 100644 --- a/tcl/fpga/xilinx-dna.cfg +++ b/tcl/fpga/xilinx-dna.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + proc xilinx_dna_addr {chip} { array set addrs { Spartan6 0x30 diff --git a/tcl/fpga/xilinx-xadc.cfg b/tcl/fpga/xilinx-xadc.cfg index 250879e..fdaf3a9 100644 --- a/tcl/fpga/xilinx-xadc.cfg +++ b/tcl/fpga/xilinx-xadc.cfg @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + # Xilinx XADC support for 7 Series FPGAs # # The 7 Series FPGAs contain an on-chip 12 bit ADC that can probe die |