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| author | Tim Newsome <tim@sifive.com> | 2023-11-03 10:30:35 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-11-03 10:30:35 -0700 |
| commit | b75bfab0261aa06597ee68895884a62eabceec18 (patch) | |
| tree | 8be5af962b0e99df64f96421d578e319d5d24f81 /tcl/fpga/altera-arriaii.cfg | |
| parent | 2676f05f2f6e93b2d73d095393061afb4549d999 (diff) | |
| parent | 805d394ff8c5e1d1d4f543956ed0393087306171 (diff) | |
| download | riscv-openocd-b75bfab0261aa06597ee68895884a62eabceec18.zip riscv-openocd-b75bfab0261aa06597ee68895884a62eabceec18.tar.gz riscv-openocd-b75bfab0261aa06597ee68895884a62eabceec18.tar.bz2 | |
Merge pull request #896 from AnastasiyaChernikova/ac-sc2
target/riscv: Adding register tables to make register names consiste
Diffstat (limited to 'tcl/fpga/altera-arriaii.cfg')
0 files changed, 0 insertions, 0 deletions