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authorTim Newsome <tim@sifive.com>2023-10-23 12:29:21 -0700
committerTim Newsome <tim@sifive.com>2023-10-23 12:29:21 -0700
commitaf08d582b55f8c8e326b422a46c63909bca6009c (patch)
tree86e13b5da9ce8b8c02e1ceec6ec066a9b9da27f0 /tcl/cpld
parent132e3faf1d47f4a2ca7d01aa0191c59f5e1816c5 (diff)
parente17fe4db0f256ee4fb97dcfd6b9f7f55c966b190 (diff)
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Merge commit 'e17fe4db0f256ee4fb97dcfd6b9f7f55c966b190' into from_upstream
Conflicts: src/flash/nor/drivers.c src/target/riscv/riscv.c Change-Id: Ide3eded7e0d5b0b446bfd0873a32c00cc9f128bd
Diffstat (limited to 'tcl/cpld')
-rw-r--r--tcl/cpld/altera-5m570z-cpld.cfg13
-rw-r--r--tcl/cpld/altera-epm240.cfg24
-rw-r--r--tcl/cpld/altera-max10.cfg30
-rw-r--r--tcl/cpld/altera-maxii.cfg21
-rw-r--r--tcl/cpld/altera-maxv.cfg19
5 files changed, 83 insertions, 24 deletions
diff --git a/tcl/cpld/altera-5m570z-cpld.cfg b/tcl/cpld/altera-5m570z-cpld.cfg
index 5dbd0de..4504a80 100644
--- a/tcl/cpld/altera-5m570z-cpld.cfg
+++ b/tcl/cpld/altera-5m570z-cpld.cfg
@@ -1,8 +1,9 @@
# SPDX-License-Identifier: GPL-2.0-or-later
-# Altera MAXV 5M24OZ/5M570Z CPLD
-# see MAX V Device Handbook
-# Table 6-3: 32-Bit MAX V Device IDCODE
-# Version Part Number Manuf. ID LSB
-# 0000 0010 0000 1010 0111 000 0110 1110 1
-jtag newtap 5m570z tap -expected-id 0x020a60dd -irlen 10
+# file altera-5m570z-cpld.cfg replaced by altera-maxv.cfg
+echo "DEPRECATED: use altera-maxv.cfg instead of deprecated altera-5m570z-cpld.cfg"
+
+#just to be backward compatible:
+#tap will be 5m570z.tap instead of maxv.tap:
+set CHIPNAME 5m570z
+source [find cpld/altera-maxv.cfg]
diff --git a/tcl/cpld/altera-epm240.cfg b/tcl/cpld/altera-epm240.cfg
index 39c409b..185925a 100644
--- a/tcl/cpld/altera-epm240.cfg
+++ b/tcl/cpld/altera-epm240.cfg
@@ -1,24 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-or-later
-# Altera MAXII EPM240T100C CPLD
+# file altera-epm240.cfg replaced by altera-maxii.cfg
+echo "DEPRECATED: use altera-maxii.cfg instead of deprecated altera-epm240.cfg"
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME epm240
-}
-
-# see MAX II Device Handbook
-# Table 3-3: 32-Bit MAX II Device IDCODE
-# Version Part Number Manuf. ID LSB
-# 0000 0010 0000 1010 0001 000 0110 1110 1
-jtag newtap $_CHIPNAME tap -irlen 10 \
- -expected-id 0x020a10dd \
- -expected-id 0x020a20dd \
- -expected-id 0x020a30dd \
- -expected-id 0x020a40dd \
- -expected-id 0x020a50dd \
- -expected-id 0x020a60dd
+#just to be backward compatible:
+#tap will be epm240.tap instead of maxii.tap:
+set CHIPNAME epm240
+source [find cpld/altera-maxii.cfg]
# 200ns seems like a good speed
# c.f. Table 5-34: MAX II JTAG Timing Parameters
diff --git a/tcl/cpld/altera-max10.cfg b/tcl/cpld/altera-max10.cfg
new file mode 100644
index 0000000..a2ed00a
--- /dev/null
+++ b/tcl/cpld/altera-max10.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# see MAX 10 FPGA Device Architecture
+# Table 3-1: IDCODE Information for MAX 10 Devices
+# Intel MAX 10M02 0x31810dd
+# Intel MAX 10M04 0x318a0dd
+# Intel MAX 10M08 0x31820dd
+# Intel MAX 10M16 0x31830dd
+# Intel MAX 10M25 0x31840dd
+# Intel MAX 10M40 0x318d0dd
+# Intel MAX 10M50 0x31850dd
+# Intel MAX 10M02 0x31010dd
+# Intel MAX 10M04 0x310a0dd
+# Intel MAX 10M08 0x31020dd
+# Intel MAX 10M16 0x31030dd
+# Intel MAX 10M25 0x31040dd
+# Intel MAX 10M40 0x310d0dd
+# Intel MAX 10M50 0x31050dd
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME max10
+}
+
+jtag newtap $_CHIPNAME tap -irlen 10 -expected-id 0x31810dd -expected-id 0x318a0dd \
+ -expected-id 0x31820dd -expected-id 0x31830dd -expected-id 0x31840dd \
+ -expected-id 0x318d0dd -expected-id 0x31850dd -expected-id 0x31010dd \
+ -expected-id 0x310a0dd -expected-id 0x31020dd -expected-id 0x31030dd \
+ -expected-id 0x31040dd -expected-id 0x310d0dd -expected-id 0x31050dd
diff --git a/tcl/cpld/altera-maxii.cfg b/tcl/cpld/altera-maxii.cfg
new file mode 100644
index 0000000..2dee37f
--- /dev/null
+++ b/tcl/cpld/altera-maxii.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Altera MAXII CPLD
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME maxii
+}
+
+# see MAX II Device Handbook
+# Table 3-3: 32-Bit MAX II Device IDCODE
+# Version Part Number Manuf. ID LSB
+# 0000 0010 0000 1010 0001 000 0110 1110 1
+jtag newtap $_CHIPNAME tap -irlen 10 \
+ -expected-id 0x020a10dd \
+ -expected-id 0x020a20dd \
+ -expected-id 0x020a30dd \
+ -expected-id 0x020a40dd \
+ -expected-id 0x020a50dd \
+ -expected-id 0x020a60dd
diff --git a/tcl/cpld/altera-maxv.cfg b/tcl/cpld/altera-maxv.cfg
new file mode 100644
index 0000000..03fad07
--- /dev/null
+++ b/tcl/cpld/altera-maxv.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Altera MAXV 5M24OZ/5M570Z CPLD
+# see MAX V Device Handbook
+# Table 6-3: 32-Bit MAX V Device IDCODE
+# 5M40Z 5M80Z 5M160Z 5M240Z: 0x020A50DD
+# 5M570Z: 0x020A60DD
+# 5M1270Z: 0x020A30DD
+# 5M1270Z 5M2210Z: 0x020A40DD
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME maxv
+}
+
+jtag newtap $_CHIPNAME tap -irlen 10 \
+ -expected-id 0x020A50DD -expected-id 0x020A60DD \
+ -expected-id 0x020A30DD -expected-id 0x020A40DD