jtagspi: new protocol that includes transfer length

This commit contains a rewrite of the jtagspi protocol and covers both
changes in the jtagspi.c openocd driver and the bscan_spi
(xilinx_bscan_spi) proxy bitstreams. The changes are as follows:

1. Always perform IR scan to ensure proper clearing of BYPASSed DRs.
2. Insert alignment cycles for all BYPASSed TAPs:

  The previous logic was erroneous. The delay in clock cyles from a bit
  written to the jtag interface to a bit read by the jtag interface is:

  * The number of BYPASSed TAPs before this (jtagspi) tap
  * The length of the jtagspi data register (1)
  * The number of BYPASSed TAPs before this one.

  I.e. it is just the number of enabled TAPs. This also gets rid of the
  configuration parameter DR_LENGTH.

3. Use marker bit to start spi transfer

  If there are TAPs ahead of this one on the JTAG chain, and we are in
  DR-SHIFT, there will be old bits toggled through first before the first
  valid bit destined for the flash.
  This delays the begin of the JTAGSPI transaction until the first high bit.

4. New jtagspi protocol

  A JTAGSPI transfer now consists of:

  * an arbitrary number of 0 bits (from BYPASS registers in front of the
    JTAG2SPI DR)
  * a marker bit (1) indicating the start of the JTAG2SPI transaction
  * 32 bits (big endian) describing the length of the SPI transaction
  * a number of SPI clock cycles (corresponding to 3.) with CS_N asserted
  * an arbitrary number of cycles (to shift MISO/TDO data through
    subsequent BYPASS registers)

5. xilinx_bscan_spi: clean up, add ultrascale

This is tested on the following configurations:

* KC705: XC7K325T
* Sayma AMC: XCKU040
* Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG
  adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx
  Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma
* Custom board with Lattice FPGA + XC7A35T
* CUstom board with 3x XCKU115-2FLVA1517E

Change-Id: I7361e9fb284ebb916302941735eebef3612aa103
Signed-off-by: Robert Jordens <jordens@gmail.com>
Reviewed-on: http://openocd.zylin.com/4236
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

1 files changed, 1 insertions, 7 deletions

diff --git a/tcl/cpld/jtagspi.cfg b/tcl/cpld/jtagspi.cfg
index 60c3cb1..e720c39 100644
--- a/tcl/cpld/jtagspi.cfg
+++ b/tcl/cpld/jtagspi.cfg
@@ -6,12 +6,6 @@ if { [info exists JTAGSPI_IR] } {
 	set _JTAGSPI_IR $_USER1
 }
 
-if { [info exists DR_LENGTH] } {
-	set _DR_LENGTH $DR_LENGTH
-} else {
-	set _DR_LENGTH 1
-}
-
 if { [info exists TARGETNAME] } {
 	set _TARGETNAME $TARGETNAME
 } else {
@@ -25,7 +19,7 @@ if { [info exists FLASHNAME] } {
 }
 
 target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
-flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR $_DR_LENGTH
+flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR
 
 proc jtagspi_init {chain_id proxy_bit} {
 	# load proxy bitstream $proxy_bit and probe spi flash