From upstream (#620)

* cortex_m: use unsigned int for FPB and DWT quantifiers

related quantifiers are:
 - fp_num_lit
 - fp_num_code
 - dwt_num_comp
 - dwt_comp_available

Change-Id: I07dec2d4aa21bc0e580be0d9fd0a6809f876c2a8
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6185
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* telnet: allow hiding selected commands during auto-completion

We have TCL procedure and commands that we do not want to show in
the list of auto-completion. E.g. TCL wrappers for deprecated
commands, internal procedures that are not supposed to be exposed
to user, or even commands that the user decides to hide.

Create a TCL procedure to be called by telnet auto-complete code
in place of the hard-coded TCL command. The procedure will run the
same command and will filter-out the unwanted command names.

Initialize the list of commands to be filtered-out with the name
of the TCL procedure above, as it is considered as internal.

Change-Id: I2d83bbf8194502368c589c85cccb617e69128c69
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6194
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>

* telnet/auto-complete: hide deprecated and internal commands

For both:
- TCL proc that redirect deprecated commands to the new commands,
- TCL proc used internally and not supposed to be exposed to user,
add their name to the list of commands that should be hide by the
telnet auto-complete.

Change-Id: I05237c6a79334b7d2b151dfb129fb57b2f40bba6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6195
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>

* startup.tcl: prepare for jimtcl 0.81 'expr' syntax change

Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

Modify the script startup.tcl compiled-in OpenOCD binary to comply
with the new jimtcl.

Change-Id: I520dcafacadaa289a815035f93f250447ca66ea0
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6158
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* tcl: [1/3] prepare for jimtcl 0.81 'expr' syntax change

Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

In the TCL scripts distributed with OpenOCD there are 1700+ lines
that should be modified before switching to jimtcl 0.81.

Apply the script below on every script in tcl folder. It fixes
more than 92% of the lines

%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
 #!/usr/bin/perl -Wpi

 my $re_sym = qr{[a-z_][a-z0-9_]*}i;
 my $re_var = qr{(?:\$|\$::)$re_sym};
 my $re_const = qr{0x[0-9a-f]+|[0-9]+|[0-9]*\.[0-9]*}i;
 my $re_item = qr{(?:~\s*)?(?:$re_var|$re_const)};
 my $re_op = qr{<<|>>|[+\-*/&|]};
 my $re_expr = qr{(
     (?:\(\s*(?:$re_item|(?-1))\s*\)|$re_item)
     \s*$re_op\s*
     (?:$re_item|(?-1)|\(\s*(?:$re_item|(?-1))\s*\))
 )}x;

 # [expr [dict get $regsC100 SYM] + HEXNUM]
 s/\[expr (\[dict get $re_var $re_sym\s*\] \+ *$re_const)\]/\[expr \{$1\}\]/;

 # [ expr (EXPR) ]
 # [ expr EXPR ]
 # note: $re_expr captures '$3'
 s/\[(\s*expr\s*)\((\s*$re_expr\s*)\)(\s*)\]/\[$1\{$2\}$4\]/;
 s/\[(\s*expr\s*)($re_expr)(\s*)\]/\[$1\{$2\}$4\]/;
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---

Change-Id: I0d6bddc6abf6dd29062f2b4e72b5a2b5080293b9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6159
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* tcl: [2/3] prepare for jimtcl 0.81 'expr' syntax change

Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

Enclose within double quote the argument of 'expr' when there is
the need to concatenate strings.

Change-Id: Ic0ea990ed37337a7e6c3a99670583685b570b8b1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6160
Tested-by: jenkins

* tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change

Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

Fix manually the remaining lines that don't match simple patterns
and would require dedicated boring scripting.
Remove the 'expr' command where appropriate.

Change-Id: Ia75210c8447f88d38515addab4a836af9103096d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6161
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* target/stm8: Make 'stm8_command_handlers' static

Change-Id: I5237a8f2a1ecba9383672e37bd56f8ccd17598b6
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6200
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/riscv: Change 'authdata_read' output

Use a constant output length and remove the line break to make the
authentication data easier to parse.

Change-Id: Iebbf1f171947ef89b0f360a2cb286a4ea15c6ba5
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6199
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tim Newsome <tim@sifive.com>

* Enable adapter "Bus Pirate" by default.

The Bus Pirate is now listed in the "OpenOCD configuration summary" too.

Change-Id: Ieb7bf9134af456ebe9803f3108a243204fb2a62d
Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Reviewed-on: http://openocd.zylin.com/5637
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* coding-style: additional style for C code

To improve readability and to push more uniform code style.

Prefer 'if (false) {...}' for unused code so it get checked by the
compiler.
Define preferred indentation for 'switch' statement.
Require balanced brackets in 'if/else'.
Report the max line length.
Report the formatting strings for stdint/inttypes types.
Report the type 'target_addr_t'.
Prefer 'unsigned int' to 'unsigned'.

Change-Id: I0192a4ed298f6c6c432764fdd156cffd4b13fc89
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6203
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Marc Schink <dev@zapb.de>

* Add IPDBG JtagHost functionality to OpenOCD

IPDBG are utilities to debug IP-cores. It uses JTAG for
transport to/from the FPGA. The different UIs use TCP/IP
as transport. The JtagHost makes the bridge between these
two.

Comparable to the bridge between GDB and the in-circuit-
debugging-unit of a micro controller.

Change-Id: Ib1bc10dcbd4ea426e492bb7b2d85c1ed1b7a8d5a
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: http://openocd.zylin.com/5938
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* flash/nor/xcf: Do not use 'Yoda conditions'

Change-Id: I17308f5237338ce468e5b86289a0634429deaaa9
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6201
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* cortex_m: add armv8m special registers

Change-Id: I1942f375a5f4282ad1fe4a2ff3b8f3cbc64d8f7f
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6016
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* rtos: Add support for Zephyr RTOS

With this patch, the Zephyr[1] RTOS is supported by OpenOCD.

As usual with support for other RTOSes, Zephyr must be compiled with
the DEBUG_THREAD_INFO option. This will generate some symbols
with information needed in order to build the list of threads.

The current implementation is limited to Zephyr running on ARM
Cortex-M processors. This is the only ARM variant supported by Zephyr
at the moment and is used on most of the officially supported boards.

[1] https://www.zephyrproject.org/

Change-Id: I22afdbec91562f3a22cf5b88cd4ea3a7a59ba0b4
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Signed-off-by: Daniel Glöckner <dg@emlix.com>
Reviewed-on: http://openocd.zylin.com/4988
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/armv7m.h: [style] replace tab with space between variable type and name

Change-Id: I9740c25857295a2a655d3046322a3f23f0ee7f78
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6230
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* server: gdb_server: Add colon for target extended-remote

Both GDB commands "target remote" and "target extended-remote" require
to have ":" right before port number.

e.g.
    (gdb) target extended-remote :3333

Add ":" to the warning message so that users can copy & past it.

Change-Id: Id6d8ec1e4dfd3c12cb7f3b314064f2c35fa7ab55
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Reviewed-on: http://openocd.zylin.com/6237
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* jimtcl: restrict memory leak workaround on Linux only

The workaround for jimtcl 0.80 in commit 36ae487ed04b ("jimtcl:
add temporary workaround for memory leak in jimtcl 0.80") issues a
compile time error on macOS:
	../src/helper/command.c:157:22: error: aliases are not
	supported on darwin
	__attribute__((weak, alias("workaround_createcommand")));
The OS is x86_64-apple-darwin19.6.0 and the compiler used is
x86_64-apple-darwin13.4.0-clang.

Restrict the workaround on Linux host only. The fix for 'expr'
syntax change is already merged and the workaround will be dropped
soon.

Change-Id: I925109a9c57c05f8c95b70bc7d6604eb1172cd79
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Adam Jeliński <ajelinski@users.sourceforge.net>
Fixes: 36ae487ed04b ("jimtcl: add temporary workaround for memory leak in jimtcl 0.80")
Fixes: https://sourceforge.net/p/openocd/tickets/304/
Reviewed-on: http://openocd.zylin.com/6241
Tested-by: jenkins

* target/armv7m: fix static analyzer warning

Despite of assert(is_packed) clang static analyser complains on use
of the uninitialized offset variable.

Cross compiling with latest x86_64-w64-mingw32-gcc hits warnings
	src/target/armv7m.c: In function ‘armv7m_read_core_reg’:
	src/target/armv7m.c:337:54: error: ‘reg32_id’ may be used
	    uninitialized in this function [-Werror=maybe-uninitialized]

It happens because mingw32 defines assert() without the attribute
"noreturn", whatever NDEBUG is defined or not.

Replace assert(is_packed) by if (is_packed) conditional and call
assert(false) in the else branch.

Change-Id: Id3c7dcccb65106e28be200b9a4d2b642f4d31019
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/6256
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Andrzej Sierżęga <asier70@gmail.com>

* cmsis_dap: fix build on macOS

Compile fails with error:
	src/jtag/drivers/cmsis_dap.c:683:28: error: format specifies type
	    'unsigned char' but the argument has type 'int' [-Werror,-Wformat]
	                         " received 0x%" PRIx8, CMD_DAP_TFER, resp[0]);
	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~

Fix the format specifier.

Change-Id: I0a5a1a35452d634019989d14d849501fb8a7e93a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6255
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* cortex_m: do not perform soft_reset_halt on targets without VECTRESET

Change-Id: Ib3df457e0afe4e342c82ad1af25e03aad6979d87
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6209
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

* cortex_m: fix VECTRESET detection for ARMv6-M cores

VECTRESET check should be done after verifying if the core is an ARMv6-M core,
and not before that.

Fixes: 2dc9c1df81b6 ("cortex_m: [FIX] ARMv8-M does not support VECTRESET")
Change-Id: I8306affd332b3a35cea69bba39ef24ca71244273
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6232
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/arm_dpm: rename 'wp_pc' as 'wp_addr'

The field 'wp_pc' was originally introduced in commit 55eeea7fceb6
("ARMv7a/Cortex-A8: report watchpoint trigger insn") in end 2009
to contain the address of the instruction which triggered a
watchpoint. Later on with commit 651b861d5d5f ("target/aarch64:
Add watchpoint support") it has been reused in to hold directly
the memory address that triggered a watchpoint.

Rename 'wp_pc' as 'wp_addr' and change its doxygen description.
While there, fix the format string to print the field.

Change-Id: I2e5ced1497e4a6fb6b38f91e881807512e8d8c47
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6204
Tested-by: jenkins
Reviewed-by: Liming Sun <limings@nvidia.com>

* target/aarch64: fix watchpoint management

The early documentation for armv8a report the debug register WFAR
as containing the address of the instruction that triggered the
watchpoint. More recent documentation report the register EDWAR as
containing the data memory address that triggered the watchpoint.

The name of macros CPUV8_DBG_WFAR0 and CPUV8_DBG_WFAR1 is not
correct as they point to the debug register EDWAR, so reading such
register returns directly the data memory address that triggered
the watchpoint. The code incorrectly passes this address value to
the function armv8_dpm_report_wfar(); this function is supposed to
adjust the PC value, decrementing it to remove the effects of the
CPU pipeline. This pipeline offset, that has no meaning on the
value in EDWAR, caused commit 651b861d5d5f ("target/aarch64: Add
watchpoint support") to add back the offset while comparing the
address with the watchpoint enabled.

The upper 32 bits of EDWAR are not valid in aarch32 mode and have
to be ignored.

Rename CPUV8_DBG_WFAR0/1 as CPUV8_DBG_EDWAR0/1.
Remove the function armv8_dpm_report_wfar().
Remove the offset while searching the matching watchpoint.
Ignore the upper 32 bits of EDWAR in aarch32 mode.
Fix a comment and the LOG text.

Change-Id: I7cbdbeb766fa18e31cc72be098ca2bc501877ed1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6205
Tested-by: jenkins
Reviewed-by: Liming Sun <limings@nvidia.com>

* flash/stm32l4x: add missing break statement

this is not a bug fix, this for loop will issue only one match
adding the break will save unnecessary more loops.

Change-Id: Ic1484ea8cdea1b284eb570f9e3e7818e07daf5cd
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6248
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins

* github/action: create a permanent 'latest' release

this commit extends the existing snapshot action to create a release named
'latest' with the built binaries for windows.

this 'latest' release will be updated after every push to github.

Change-Id: I75a64c598169241743add3ac9aa7a0337fbab7f2
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6127
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* tcl/rp2040: remove empty line at end of file

Change-Id: I212a96b77282b151a8ecbd46a6436e2bbbda4161
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6221
Tested-by: jenkins

* tcl: fix some minor typo

Minor typos found by the new checkpatch boosted by the dictionary
provided by 'codespell'.
While there, fix one indentation.

Change-Id: I72369ed26f363bacd760b40b8c83dd95e89d28a4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6214
Tested-by: jenkins

* flash: fix some minor typo

Minor typos found by the new checkpatch boosted by the dictionary
provided by 'codespell'.

Change-Id: Ia5f134c91beb483fd865df9e4877e0ec3e789478
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6215
Tested-by: jenkins

* jtag: fix some minor typo

Minor typos found by the new checkpatch boosted by the dictionary
provided by 'codespell'.

Change-Id: I101c76a638805d77c1ff356cf0f027552389e5d3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6216
Tested-by: jenkins

* target: fix some minor typo

Minor typos found by the new checkpatch boosted by the dictionary
provided by 'codespell'.

Change-Id: I548581247db72e683249749d1b8725035530b06e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6217
Tested-by: jenkins

* openocd: fix some minor typo

Minor typos found by the new checkpatch boosted by the dictionary
provided by 'codespell'.

Change-Id: I7b4cae1798ff5ea048fcbc671a397af763fdc605
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6218
Tested-by: jenkins

* Document the buspirate interface driver.

Change-Id: Iaff13fc5187041a840f4f00eb6b4ee52880cf47e
Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Reviewed-on: http://openocd.zylin.com/6231
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Warn on undefined preprocessor symbols

Preprocessor directives like "#if SYMBOL" silently replace undefined or
misspelt symbols with 0, which makes configuration bugs hard to spot.
Compiler flag "-Wundef" prevents such errors.

Change-Id: I91b7ba2db02ef0c3c452d334601c53aebda4660e
Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Reviewed-on: http://openocd.zylin.com/6238
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Remove compatibility macros m4_ifblank and m4_ifnblank

They are at least since Autoconf 2.67 present,
and we are requiring version 2.69.

Change-Id: I41b33d4ebe02198f03cdddcc4a3c1beedd993d78
Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Reviewed-on: http://openocd.zylin.com/6239
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* configure.ac: use a separate folder for Autoconf-generated files

Autoconf generates several files in root folder of the project.
Keep the root folder cleaner by specifying subfolder 'build-aux'.
Align .gitignore accordingly.

Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Change-Id: Ied87faba495d9eeb8f98e78c2e2b7e7e596febfb
Reviewed-on: http://openocd.zylin.com/6236
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* helper/command: silent debug msg on command register/unregister

Commit e216186fab59 ("helper/command: register full-name commands
in jim") and commit a7d68878e4ba ("helper/command: unregister
commands through their full-name") introduce a LOG_DEBUG() message
each for command registration and unregistration.
The messages above are quite noisy and pollute the log when
debug_level is 3 or higher.
They can be useful to debug the command registration logic, but
for the other debug activities on OpenOCD are just noisy.
Already commit a03ac1ba3087 ("helper/command: disable logging of
registered commands [RFC]") was merged to silent the first case
that is now back with additional logs.

Silent both log messages.
Use 'if (false)' to silent them, making easy to re-enable it when
or if someone needs it.

Change-Id: Id8a067e60e822d4ecbddcb036d081298f7e6181f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6220
Tested-by: jenkins

* mem_ap: fix target arch_info type

The target mem_ap appears as an ARM target, thus it allows the
execution of ARM specific commands causing the crash of OpenOCD.
E.g. 'arm mrc ...' can be executed and segfaults.

Replace the incorrect ARM magic number with a dedicated one.
While there, remove the 'struct arm', that is now holding only the
mem_ap's dap, and replace it with a pointer to the dap.

Change-Id: I881332d3fdf8d8f8271b8711607737b052a5699b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6213
Tested-by: jenkins

* riscv: drop unused variable

The array newly_halted[] is assigned but its value is never used.
Drop it!

Change-Id: I678812a31c45a3ec03716e3eee6a30b8e8947926
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6257
Tested-by: jenkins
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Tim Newsome <tim@sifive.com>

* riscv: replace macro DIM() with ARRAY_SIZE()

OpenOCD already defines the macro ARRAY_SIZE, while riscv code
uses a local macro DIM.

Prefer using the macro ARRAY_SIZE() instead of DIM().
Not all the riscv code has been upstreamed, yes; this patch only
covers the code already upstreamed.

Change-Id: I89a58a6d91916d85c53ba5e4091b558271f8d618
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6258
Reviewed-by: Xiang W <wxjstz@126.com>
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>

* target/zynqmp : Add AXI AP access port

The Xilinx Zynq UltraScale+ SoC have an "AXI-AP" access port for direct memory accesses without halting CPUs.

Change-Id: I6303331c217795657575de4759444938e775dee1
Signed-off-by: Olivier DANET <odanet@caramail.com>
Reviewed-on: http://openocd.zylin.com/6263
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* drivers/versaloon: use ARRAY_SIZE()

Replace the custom macro dimof() with the OpenOCD macro
ARRAY_SIZE().

Change-Id: I2fe638444f6c16f2a78c1fd558b21550f76282d6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6259
Tested-by: jenkins
Reviewed-by: Xiang W <wxjstz@126.com>

* openocd: use macro ARRAY_SIZE()

There are still few cases where the macro ARRAY_SIZE() should be
used in place of custom code.

Use ARRAY_SIZE() whenever possible.

Change-Id: Iba0127a02357bc704fe639e08562a4f9aa7011df
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6260
Reviewed-by: Xiang W <wxjstz@126.com>
Tested-by: jenkins

* rtos: use ARRAY_SIZE() and simplify rtos_type.create()

Use the existing macro ARRAY_SIZE().
Rewrite the functions rtos_type.create() to simplify the logic.

Change-Id: I8833354767045d1642801d26944c9087a77add00
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6261
Tested-by: jenkins

* tcl: remove remaining deprecated commands

There are still few adapter_khz, ftdi_location, jtag_nsrst_delay
and xds110_serial strolling around ...

Change-Id: I3e8503dcc3875e3c92e6536f3d455a5e448d51ff
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6270
Tested-by: jenkins

* help text: remove trailing space

Some help text end with a useless space character.
Remove it.

Change-Id: I397e1194fac8042f0fab694222f925f906716de3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6222
Tested-by: jenkins

* help: fix line size in 'usage' output

The implementation of command 'usage' is broken while checking the
line limit of 76 chars per line (e.g. 'usage load_image') and the
line wrapping is not correct. The same broken code is used for the
first output line of command 'help' too.

When call command_help_show_wrap(), include the command's name in
the string so the whole text would be wrapped.

Change-Id: Idece01ce54994db7e851d8522435ff764b11f3ac
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6223
Tested-by: jenkins

* LICENSES: Add the MIT license

Add the full text of the MIT license to the kernel tree.  It was copied
directly from:

  https://spdx.org/licenses/MIT.html#licenseText

Add the required tags for reference and tooling.

Change-Id: I94a5dea5ced6421809ea2a3448f8dda19a93f5c9
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6219
Tested-by: jenkins

* stlink: add comment of firmware version for each flag bit

Change-Id: I7f7c7b9c9cfd88125f82662ed864a2c0715140b1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6211
Tested-by: jenkins

* stlink: reorder the flag macro by firmware release

The corresponding bit for each macro is changed, but this is not
relevant in the code.

Change-Id: I7039464f5a3d55d008208f44952aadeb815bd5a3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6212
Tested-by: jenkins

* tcl/board: Add ST NUCLEO-8S208RB

Change-Id: I384c6ad9b4cbabbc004160677f600d8c4bd3eb71
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6268
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/arm_adi_v5: Fix clear sticky overrun flag during replay of commands

When a WAIT occurs the commands after the WAIT are replayed and the
STICKYORUN is cleared. However if another WAIT occurs during the
command replay, the command itself is resent but the STICKYORUN bit
shall also be cleared. If this is not done, the MEM-AP hangs.

Change-Id: I14e8340cd5d8f58f4de31509da96cfa2ecb630d1
Signed-off-by: micbis <michele.bisogno.ct@renesas.com>
Reviewed-on: http://openocd.zylin.com/6278
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* target/cortex_a: add support for watchpoints

The current implementation of OpenOCD does not support watchpoints for
cortex_a architecture. So, I replaced the add_watchpoint and
remove_watchpoint with the specific implementation for the
cortex a and using the breakpoint implementation and the arm
documentation [1] as reference. In particular, I have made the
following changes:

* added the following functions

- cortex_a_add_watchpoint
  This wrapper function check whether there are any watchpoint
  available on the target device by calling cortex_a_set_watchpoint.

- cortex_a_set_watchpoint
  This function is responsible for settings the watchpoint register
  pair. In particular, it sets the WVR and the WCR registers with
  the cortex_a_dap command.

- cortex_a_remove_watchpoint
  This wrapper function the selected watchpoint on the target device
  by calling cortex_a_unset_watchpoint.

- cortex_a_unset_watchpoint
  This function sets both the WVR and the WCR registers to zero, thus
  unsetting the watchpoint.

[1]
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/BCGDHIEJ.html

Change-Id: I86611dab474cb84836662af572b17636dc68e282
Signed-off-by: Chengyu Zheng <chengyu.zheng@polimi.it>
Reviewed-on: http://openocd.zylin.com/3913
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins

* target/cortex_a: fix number of watchpoints

Decrement the available watchpoints only when succeed setting it.
Initialize the available watchpoint with the correct value.

Change-Id: I0f93b347300b8ebedbcd9e718d4ba32b26cf6846
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6196
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* target/cortex_a: add support for watchpoint length of 1, 2 and 4 bytes

Use byte address select for 1 and 2 bytes length.
Use normal mode for 4 bytes length.

Change-Id: I28d182f25145d0635de64d0361d456f1ad96640e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6197
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* target/cortex_a: fix memory leak on watchpoints

The memory allocated to hold the watchpoints is not freed at
OpenOCD exit.

Free the watchpoint memory at OpenOCD exit.

Change-Id: I518c9ce0dc901cde2913d752e3154734f878b854
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6210
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

* helper/jim-nvp: comply with coding style [1/2]

The helper jim-nvp does not comply with OpenOCD coding style due
to typedef of struct and CamelCase symbol names.
While it's trivial fixing the helper and all its current use in
the code, changing these APIs will potentially break a number of
patches pending in gerrit. Gerrit will not trigger any alert, but
the code will generate compile error after the merge.

Add the compile flag "-Wno-error=deprecated-declarations" to keep
as warning (not as error) the use of "deprecated" functions and
types.
Rename all the CamelCase symbols is lowercase and provide struct
prototypes in place of the typedef.
Add a DEPRECATED section to 'jim-nvp.h' where the old CamelCase
symbols and the old typedef are re-declared with compile attribute
'deprecated'.

With this change OpenOCD compiles, but generates warnings.
The remaining changes allover OpenOCD code will be fixed in a
separate patch for easier review.

The patches merged later that still use the old deprecated API
will compile with warnings. This will permit to identify and fix
these cases.

Change-Id: I786385d0f662dbb1be5be313ae42623156d68ce5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6183
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>

* helper/jim-nvp: comply with coding style [2/2]

With the API fixed to comply with OpenOCD coding style, fix all
the references in the code.

Patch generated automatically with the script below.
The list is in reverse order to replace a common prefix after the
replacement of the symbols with the same prefix.

%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---
(cat << EOF
Jim_SetResult_NvpUnknown         jim_set_result_nvp_unknown
Jim_Nvp_value2name_simple        jim_nvp_value2name_simple
Jim_Nvp_value2name_obj           jim_nvp_value2name_obj
Jim_Nvp_value2name               jim_nvp_value2name
Jim_Nvp_name2value_simple        jim_nvp_name2value_simple
Jim_Nvp_name2value_obj_nocase    jim_nvp_name2value_obj_nocase
Jim_Nvp_name2value_obj           jim_nvp_name2value_obj
Jim_Nvp_name2value_nocase_simple jim_nvp_name2value_nocase_simple
Jim_Nvp_name2value_nocase        jim_nvp_name2value_nocase
Jim_Nvp_name2value               jim_nvp_name2value
Jim_Nvp                        struct jim_nvp
Jim_GetOpt_Wide                  jim_getopt_wide
Jim_GetOpt_String                jim_getopt_string
Jim_GetOpt_Setup                 jim_getopt_setup
Jim_GetOpt_Obj                   jim_getopt_obj
Jim_GetOpt_NvpUnknown            jim_getopt_nvp_unknown
Jim_GetOpt_Nvp                   jim_getopt_nvp
Jim_GetOpt_Enum                  jim_getopt_enum
Jim_GetOpt_Double                jim_getopt_double
Jim_GetOpt_Debug                 jim_getopt_debug
Jim_GetOptInfo                 struct jim_getopt_info
Jim_GetNvp                       jim_get_nvp
Jim_Debug_ArgvString             jim_debug_argv_string
EOF
) | while read a b; do
    sed -i "s/$a/$b/g" $(find src -type f ! -name jim-nvp.\? )
done
%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---%<---

Change-Id: I10a12bd64bb8b17575fd9150482c989c92b298a2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6184
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins

* server/telnet: fix autocomplete for jimtcl commands

Current autocomplete filters-out some command reported by "info
commands". One of the filter rule concerns the command's private
data.
Every command registered by OpenOCD has its 'struct command' as
private data.

By ignoring commands without private data, we loose several TCL
commands registered by jimtcl, e.g. 'foreach', 'llength'.

By assuming that every command with non-NULL private data has
'struct command' as private data, we risk at best to access
inconsistent data, at worst to trigger a segmentation fault.

Export the already available functions:
- to check if a command has been registered by OpenOCD and
- to get the private data.
While there, rename jimcmd_is_ocd_command() as
jimcmd_is_oocd_command().
Don't filter-out jimtcl commands with no private data.
Check the private data only on OpenOCD commands.

Change-Id: Ib5bf8d2bc5c12440c0cfae438f637c38724a79b7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6282
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>

* helper/list.h: align file to Linux v5.12

Main improvement is in the doxygen comments.
Minimize the delta with kernel file.
Skip the functions hlist_unhashed_lockless() and
__list_del_clearprev() that are relevant only in kernel.
Remove gcc extension "omitted conditional operand".

Change-Id: I2e9ddb54cfe2fa5f7cf18f44726acd144e1f98b9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6276
Reviewed-by: <rdiezmail-openocd@yahoo.de>
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>

* contrib: add an example of using list.h

Change-Id: Ic3d399d7ad2e4d10677cf78d64968040941b74e5
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6280
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>

* helper/list.h: add mention to the example in contrib

Without such reference, it could be difficult to find the example.

Change-Id: Ia9ffb06bc1a45446c2c7b53197ab3400e1d8a9e9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6281
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>

* tcl/target/stm32f4x: fix hardcoded chip name

Fixes: c945d6e61605 ("tcl/target: start using the new TPIU/SWO support")
Change-Id: I4543c9a204f7b4b3b14e6eabc5042653106aff0e
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/6277
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins

* Makefile: add special target .DELETE_ON_ERROR

The special .DELETE_ON_ERROR deletes the target file on recipe error.
Otherwise, an incomplete output file may be considered up to date
the next time around. .DELETE_ON_ERROR provides reasonable
protection at virtually no cost.

Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Change-Id: I67dca47ae5ddf3786993c87b9991b3046a85f00b
Reviewed-on: http://openocd.zylin.com/6235
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* gdb_server: Log both incoming and outgoing GDB packets

- Made sure that also outgoing GDB packets are logged,
  not only the incoming ones.

- Improved the treatment of non-printable characters
  in the packets to make it more robust.

Prior to this change:

- Outgoing packets were not printed unless OpenOCD was
  re-compiled with _DEBUG_GDB_IO_.
- Non-prinable characters were only treated in incoming
  'X' packets.

After this change:

- Both incoming and outgoing GDB packets are logged
  on debug_level >= 3, so that both directions of the
  GDB channel are visible.
- Non-printable characters are checked for in every packet
  so that hey do not interfere with the terminal.

Change-Id: I0613e57ae5059b3279b0abcb71276cf5719a8699
Signed-off-by: Jan Matyas <matyas@codasip.com>
Reviewed-on: http://openocd.zylin.com/6269
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/renesas_rz_g2: Introduce tcl config file for RZ/G2 devices

Initial support for Renesas RZ/G2 MPU family

Change-Id: I5ca74cddfd0c105a5307de56c3ade7084f9c28d2
Signed-off-by: micbis <michele.bisogno.ct@renesas.com>
Reviewed-on: http://openocd.zylin.com/6250
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* drivers/jlink: Remove trailing dots

This makes the messages consistent with most of the rest of
the OpenOCD output.

Change-Id: I915a01187e7fc317e02483ac0bbd39ec077d6321
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6274
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target: Use 'bool' for 'reset_halt'

Change-Id: I974a6360ea7467067511541ac212f2e9d3de7895
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6262
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* cmsis_dap: add support for swo commands

Replaced mixed snake_case_CamelCase with snake_case.
Define variables at first-use location.

CMSIS-DAP SWO specification:

    https://arm-software.github.io/CMSIS_5/DAP/html/group__DAP__swo__gr.html

Change-Id: Ieba79b16efd445143f964b614673d041aae74f92
Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
Reviewed-on: http://openocd.zylin.com/5820
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Add target_data_bits().

This is used to compute memory block read alignment, and specifically
allows 64-bit targets to ensure that memory block reads are only
requested on 64-bit boundaries.

Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: Idb1a27b9fc02c46245556bb0f3d6d94b368c4817
Reviewed-on: http://openocd.zylin.com/6249
Reviewed-by: Marc Schink <dev@zapb.de>
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Avoid non-standard conditionals with omitted operands.

Fixes bug #257.

Change-Id: I05fc6468306d46399e769098e031e7e588798afc
Signed-off-by: R. Diez <rdiezmail-openocd@yahoo.de>
Reviewed-on: http://openocd.zylin.com/6271
Tested-by: jenkins
Reviewed-by: Xiang W <wxjstz@126.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* target/startup.tcl: Do not use 'Yoda conditions'

Change-Id: I5e1bbaf032659dda1b365ef4ec6ea4a635d921ce
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: http://openocd.zylin.com/6284
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

* Fix build.

Change-Id: I4f2667db91f84f07af354691aac5d4c9e3aea3fa
Signed-off-by: Tim Newsome <tim@sifive.com>

Co-authored-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Co-authored-by: Antonio Borneo <borneo.antonio@gmail.com>
Co-authored-by: Marc Schink <dev@zapb.de>
Co-authored-by: R. Diez <rdiezmail-openocd@yahoo.de>
Co-authored-by: Daniel Anselmi <danselmi@gmx.ch>
Co-authored-by: Evgeniy Didin <didin@synopsys.com>
Co-authored-by: Yasushi SHOJI <yashi@spacecubics.com>
Co-authored-by: Tomas Vanek <vanekt@fbl.cz>
Co-authored-by: Olivier DANET <odanet@caramail.com>
Co-authored-by: Thomas Gleixner <tglx@linutronix.de>
Co-authored-by: micbis <michele.bisogno.ct@renesas.com>
Co-authored-by: Chengyu Zheng <chengyu.zheng@polimi.it>
Co-authored-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Co-authored-by: Jan Matyas <matyas@codasip.com>
Co-authored-by: Adrian Negreanu <adrian.negreanu@nxp.com>

16 files changed, 492 insertions, 492 deletions

diff --git a/tcl/chip/atmel/at91/aic.tcl b/tcl/chip/atmel/at91/aic.tcl
index ba0f2a9..b0b1002 100644
--- a/tcl/chip/atmel/at91/aic.tcl
+++ b/tcl/chip/atmel/at91/aic.tcl
@@ -1,38 +1,38 @@
-set AIC_SMR      	[expr $AT91C_BASE_AIC + 0x00000000 ]
+set AIC_SMR      	[expr {$AT91C_BASE_AIC + 0x00000000} ]
 global AIC_SMR
-set AIC_SVR      	[expr $AT91C_BASE_AIC + 0x00000080 ]
+set AIC_SVR      	[expr {$AT91C_BASE_AIC + 0x00000080} ]
 global AIC_SVR
-set AIC_IVR      	[expr $AT91C_BASE_AIC + 0x00000100 ]
+set AIC_IVR      	[expr {$AT91C_BASE_AIC + 0x00000100} ]
 global AIC_IVR
-set AIC_FVR      	[expr $AT91C_BASE_AIC + 0x00000104 ]
+set AIC_FVR      	[expr {$AT91C_BASE_AIC + 0x00000104} ]
 global AIC_FVR
-set AIC_ISR      	[expr $AT91C_BASE_AIC + 0x00000108 ]
+set AIC_ISR      	[expr {$AT91C_BASE_AIC + 0x00000108} ]
 global AIC_ISR
-set AIC_IPR      	[expr $AT91C_BASE_AIC + 0x0000010C ]
+set AIC_IPR      	[expr {$AT91C_BASE_AIC + 0x0000010C} ]
 global AIC_IPR
-set AIC_IMR      	[expr $AT91C_BASE_AIC + 0x00000110 ]
+set AIC_IMR      	[expr {$AT91C_BASE_AIC + 0x00000110} ]
 global AIC_IMR
-set AIC_CISR     	[expr $AT91C_BASE_AIC + 0x00000114 ]
+set AIC_CISR     	[expr {$AT91C_BASE_AIC + 0x00000114} ]
 global AIC_CISR
-set AIC_IECR     	[expr $AT91C_BASE_AIC + 0x00000120 ]
+set AIC_IECR     	[expr {$AT91C_BASE_AIC + 0x00000120} ]
 global AIC_IECR
-set AIC_IDCR     	[expr $AT91C_BASE_AIC + 0x00000124 ]
+set AIC_IDCR     	[expr {$AT91C_BASE_AIC + 0x00000124} ]
 global AIC_IDCR
-set AIC_ICCR     	[expr $AT91C_BASE_AIC + 0x00000128 ]
+set AIC_ICCR     	[expr {$AT91C_BASE_AIC + 0x00000128} ]
 global AIC_ICCR
-set AIC_ISCR     	[expr $AT91C_BASE_AIC + 0x0000012C ]
+set AIC_ISCR     	[expr {$AT91C_BASE_AIC + 0x0000012C} ]
 global AIC_ISCR
-set AIC_EOICR    	[expr $AT91C_BASE_AIC + 0x00000130 ]
+set AIC_EOICR    	[expr {$AT91C_BASE_AIC + 0x00000130} ]
 global AIC_EOICR
-set AIC_SPU      	[expr $AT91C_BASE_AIC + 0x00000134 ]
+set AIC_SPU      	[expr {$AT91C_BASE_AIC + 0x00000134} ]
 global AIC_SPU
-set AIC_DCR      	[expr $AT91C_BASE_AIC + 0x00000138 ]
+set AIC_DCR      	[expr {$AT91C_BASE_AIC + 0x00000138} ]
 global AIC_DCR
-set AIC_FFER     	[expr $AT91C_BASE_AIC + 0x00000140 ]
+set AIC_FFER     	[expr {$AT91C_BASE_AIC + 0x00000140} ]
 global AIC_FFER
-set AIC_FFDR     	[expr $AT91C_BASE_AIC + 0x00000144 ]
+set AIC_FFDR     	[expr {$AT91C_BASE_AIC + 0x00000144} ]
 global AIC_FFDR
-set AIC_FFSR     	[expr $AT91C_BASE_AIC + 0x00000148 ]
+set AIC_FFSR     	[expr {$AT91C_BASE_AIC + 0x00000148} ]
 global AIC_FFSR
 
 
@@ -54,7 +54,7 @@ proc show_AIC_IMR_helper { NAME ADDR VAL } {
 
 proc show_AIC { } {
     global AIC_SMR
-    if [catch { mem2array aaa 32 $AIC_SMR [expr 32 * 4] } msg ] {
+    if [catch { mem2array aaa 32 $AIC_SMR [expr {32 * 4}] } msg ] {
 	error [format "%s (%s)" $msg AIC_SMR]
     }
     echo "AIC_SMR: Mode & Type"
@@ -71,7 +71,7 @@ proc show_AIC { } {
 	incr x
     }
     global AIC_SVR
-    if [catch { mem2array aaa 32 $AIC_SVR [expr 32 * 4] } msg ] {
+    if [catch { mem2array aaa 32 $AIC_SVR [expr {32 * 4}] } msg ] {
 	error [format "%s (%s)" $msg AIC_SVR]
     }
     echo "AIC_SVR: Vectors"
diff --git a/tcl/chip/atmel/at91/at91_pmc.cfg b/tcl/chip/atmel/at91/at91_pmc.cfg
index 88b1370..dd554ce 100644
--- a/tcl/chip/atmel/at91/at91_pmc.cfg
+++ b/tcl/chip/atmel/at91/at91_pmc.cfg
@@ -1,113 +1,113 @@
-set	AT91_PMC_SCER		[expr ($AT91_PMC + 0x00)]	;# System Clock Enable Register
-set	AT91_PMC_SCDR		[expr ($AT91_PMC + 0x04)]	;# System Clock Disable Register
+set	AT91_PMC_SCER		[expr {$AT91_PMC + 0x00}]	;# System Clock Enable Register
+set	AT91_PMC_SCDR		[expr {$AT91_PMC + 0x04}]	;# System Clock Disable Register
 
-set	AT91_PMC_SCSR		[expr ($AT91_PMC + 0x08)]	;# System Clock Status Register
-set		AT91_PMC_PCK		[expr (1 <<  0)]		;# Processor Clock
-set		AT91RM9200_PMC_UDP	[expr (1 <<  1)]		;# USB Devcice Port Clock [AT91RM9200 only]
-set		AT91RM9200_PMC_MCKUDP	[expr (1 <<  2)]		;# USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only]
-set		AT91CAP9_PMC_DDR	[expr (1 <<  2)]		;# DDR Clock [CAP9 revC & some SAM9 only]
-set		AT91RM9200_PMC_UHP	[expr (1 <<  4)]		;# USB Host Port Clock [AT91RM9200 only]
-set		AT91SAM926x_PMC_UHP	[expr (1 <<  6)]		;# USB Host Port Clock [AT91SAM926x only]
-set		AT91CAP9_PMC_UHP	[expr (1 <<  6)]		;# USB Host Port Clock [AT91CAP9 only]
-set		AT91SAM926x_PMC_UDP	[expr (1 <<  7)]		;# USB Devcice Port Clock [AT91SAM926x only]
-set		AT91_PMC_PCK0		[expr (1 <<  8)]		;# Programmable Clock 0
-set		AT91_PMC_PCK1		[expr (1 <<  9)]		;# Programmable Clock 1
-set		AT91_PMC_PCK2		[expr (1 << 10)]		;# Programmable Clock 2
-set		AT91_PMC_PCK3		[expr (1 << 11)]		;# Programmable Clock 3
-set		AT91_PMC_HCK0		[expr (1 << 16)]		;# AHB Clock (USB host) [AT91SAM9261 only]
-set		AT91_PMC_HCK1		[expr (1 << 17)]		;# AHB Clock (LCD) [AT91SAM9261 only]
+set	AT91_PMC_SCSR		[expr {$AT91_PMC + 0x08}]	;# System Clock Status Register
+set		AT91_PMC_PCK		[expr {1 <<  0}]		;# Processor Clock
+set		AT91RM9200_PMC_UDP	[expr {1 <<  1}]		;# USB Devcice Port Clock [AT91RM9200 only]
+set		AT91RM9200_PMC_MCKUDP	[expr {1 <<  2}]		;# USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only]
+set		AT91CAP9_PMC_DDR	[expr {1 <<  2}]		;# DDR Clock [CAP9 revC & some SAM9 only]
+set		AT91RM9200_PMC_UHP	[expr {1 <<  4}]		;# USB Host Port Clock [AT91RM9200 only]
+set		AT91SAM926x_PMC_UHP	[expr {1 <<  6}]		;# USB Host Port Clock [AT91SAM926x only]
+set		AT91CAP9_PMC_UHP	[expr {1 <<  6}]		;# USB Host Port Clock [AT91CAP9 only]
+set		AT91SAM926x_PMC_UDP	[expr {1 <<  7}]		;# USB Devcice Port Clock [AT91SAM926x only]
+set		AT91_PMC_PCK0		[expr {1 <<  8}]		;# Programmable Clock 0
+set		AT91_PMC_PCK1		[expr {1 <<  9}]		;# Programmable Clock 1
+set		AT91_PMC_PCK2		[expr {1 << 10}]		;# Programmable Clock 2
+set		AT91_PMC_PCK3		[expr {1 << 11}]		;# Programmable Clock 3
+set		AT91_PMC_HCK0		[expr {1 << 16}]		;# AHB Clock (USB host) [AT91SAM9261 only]
+set		AT91_PMC_HCK1		[expr {1 << 17}]		;# AHB Clock (LCD) [AT91SAM9261 only]
 
-set	AT91_PMC_PCER		[expr ($AT91_PMC + 0x10)]	;# Peripheral Clock Enable Register
-set	AT91_PMC_PCDR		[expr ($AT91_PMC + 0x14)]	;# Peripheral Clock Disable Register
-set	AT91_PMC_PCSR		[expr ($AT91_PMC + 0x18)]	;# Peripheral Clock Status Register
+set	AT91_PMC_PCER		[expr {$AT91_PMC + 0x10}]	;# Peripheral Clock Enable Register
+set	AT91_PMC_PCDR		[expr {$AT91_PMC + 0x14}]	;# Peripheral Clock Disable Register
+set	AT91_PMC_PCSR		[expr {$AT91_PMC + 0x18}]	;# Peripheral Clock Status Register
 
-set	AT91_CKGR_UCKR		[expr ($AT91_PMC + 0x1C)]	;# UTMI Clock Register [some SAM9, CAP9]
-set		AT91_PMC_UPLLEN		[expr (1   << 16)]		;# UTMI PLL Enable
-set		AT91_PMC_UPLLCOUNT	[expr (0xf << 20)]		;# UTMI PLL Start-up Time
-set		AT91_PMC_BIASEN		[expr (1   << 24)]		;# UTMI BIAS Enable
-set		AT91_PMC_BIASCOUNT	[expr (0xf << 28)]		;# UTMI BIAS Start-up Time
+set	AT91_CKGR_UCKR		[expr {$AT91_PMC + 0x1C}]	;# UTMI Clock Register [some SAM9, CAP9]
+set		AT91_PMC_UPLLEN		[expr {1   << 16}]		;# UTMI PLL Enable
+set		AT91_PMC_UPLLCOUNT	[expr {0xf << 20}]		;# UTMI PLL Start-up Time
+set		AT91_PMC_BIASEN		[expr {1   << 24}]		;# UTMI BIAS Enable
+set		AT91_PMC_BIASCOUNT	[expr {0xf << 28}]		;# UTMI BIAS Start-up Time
 
-set	AT91_CKGR_MOR		[expr ($AT91_PMC + 0x20)]	;# Main Oscillator Register [not on SAM9RL]
-set		AT91_PMC_MOSCEN		[expr (1    << 0)]		;# Main Oscillator Enable
-set		AT91_PMC_OSCBYPASS	[expr (1    << 1)]		;# Oscillator Bypass [SAM9x, CAP9]
-set		AT91_PMC_OSCOUNT	[expr (0xff << 8)]		;# Main Oscillator Start-up Time
+set	AT91_CKGR_MOR		[expr {$AT91_PMC + 0x20}]	;# Main Oscillator Register [not on SAM9RL]
+set		AT91_PMC_MOSCEN		[expr {1    << 0}]		;# Main Oscillator Enable
+set		AT91_PMC_OSCBYPASS	[expr {1    << 1}]		;# Oscillator Bypass [SAM9x, CAP9]
+set		AT91_PMC_OSCOUNT	[expr {0xff << 8}]		;# Main Oscillator Start-up Time
 
-set	AT91_CKGR_MCFR		[expr ($AT91_PMC + 0x24)]	;# Main Clock Frequency Register
-set		AT91_PMC_MAINF		[expr (0xffff <<  0)]		;# Main Clock Frequency
-set		AT91_PMC_MAINRDY	[expr (1	<< 16)]		;# Main Clock Ready
+set	AT91_CKGR_MCFR		[expr {$AT91_PMC + 0x24}]	;# Main Clock Frequency Register
+set		AT91_PMC_MAINF		[expr {0xffff <<  0}]		;# Main Clock Frequency
+set		AT91_PMC_MAINRDY	[expr {1	<< 16}]		;# Main Clock Ready
 
-set	AT91_CKGR_PLLAR		[expr ($AT91_PMC + 0x28)]	;# PLL A Register
-set	AT91_CKGR_PLLBR		[expr ($AT91_PMC + 0x2c)]	;# PLL B Register
-set		AT91_PMC_DIV		[expr (0xff  <<  0)]		;# Divider
-set		AT91_PMC_PLLCOUNT	[expr (0x3f  <<  8)]		;# PLL Counter
-set		AT91_PMC_OUT		[expr (3     << 14)]		;# PLL Clock Frequency Range
-set		AT91_PMC_MUL		[expr (0x7ff << 16)]		;# PLL Multiplier
-set		AT91_PMC_USBDIV		[expr (3     << 28)]		;# USB Divisor (PLLB only)
-set			AT91_PMC_USBDIV_1		[expr (0 << 28)]
-set			AT91_PMC_USBDIV_2		[expr (1 << 28)]
-set			AT91_PMC_USBDIV_4		[expr (2 << 28)]
-set		AT91_PMC_USB96M		[expr (1     << 28)]		;# Divider by 2 Enable (PLLB only)
-set		AT91_PMC_PLLA_WR_ERRATA	[expr (1     << 29)]		;# Bit 29 must always be set to 1 when programming the CKGR_PLLAR register
+set	AT91_CKGR_PLLAR		[expr {$AT91_PMC + 0x28}]	;# PLL A Register
+set	AT91_CKGR_PLLBR		[expr {$AT91_PMC + 0x2c}]	;# PLL B Register
+set		AT91_PMC_DIV		[expr {0xff  <<  0}]		;# Divider
+set		AT91_PMC_PLLCOUNT	[expr {0x3f  <<  8}]		;# PLL Counter
+set		AT91_PMC_OUT		[expr {3     << 14}]		;# PLL Clock Frequency Range
+set		AT91_PMC_MUL		[expr {0x7ff << 16}]		;# PLL Multiplier
+set		AT91_PMC_USBDIV		[expr {3     << 28}]		;# USB Divisor (PLLB only)
+set			AT91_PMC_USBDIV_1		[expr {0 << 28}]
+set			AT91_PMC_USBDIV_2		[expr {1 << 28}]
+set			AT91_PMC_USBDIV_4		[expr {2 << 28}]
+set		AT91_PMC_USB96M		[expr {1     << 28}]		;# Divider by 2 Enable (PLLB only)
+set		AT91_PMC_PLLA_WR_ERRATA	[expr {1     << 29}]		;# Bit 29 must always be set to 1 when programming the CKGR_PLLAR register
 
-set	AT91_PMC_MCKR		[expr ($AT91_PMC + 0x30)]	;# Master Clock Register
-set		AT91_PMC_CSS		[expr (3 <<  0)]		;# Master Clock Selection
-set			AT91_PMC_CSS_SLOW		[expr (0 << 0)]
-set			AT91_PMC_CSS_MAIN		[expr (1 << 0)]
-set			AT91_PMC_CSS_PLLA		[expr (2 << 0)]
-set			AT91_PMC_CSS_PLLB		[expr (3 << 0)]
-set			AT91_PMC_CSS_UPLL		[expr (3 << 0)]	;# [some SAM9 only]
-set		AT91_PMC_PRES		[expr (7 <<  2)]		;# Master Clock Prescaler
-set			AT91_PMC_PRES_1			[expr (0 << 2)]
-set			AT91_PMC_PRES_2			[expr (1 << 2)]
-set			AT91_PMC_PRES_4			[expr (2 << 2)]
-set			AT91_PMC_PRES_8			[expr (3 << 2)]
-set			AT91_PMC_PRES_16		[expr (4 << 2)]
-set			AT91_PMC_PRES_32		[expr (5 << 2)]
-set			AT91_PMC_PRES_64		[expr (6 << 2)]
-set		AT91_PMC_MDIV		[expr (3 <<  8)]		;# Master Clock Division
-set			AT91RM9200_PMC_MDIV_1		[expr (0 << 8)]	;# [AT91RM9200 only]
-set			AT91RM9200_PMC_MDIV_2		[expr (1 << 8)]
-set			AT91RM9200_PMC_MDIV_3		[expr (2 << 8)]
-set			AT91RM9200_PMC_MDIV_4		[expr (3 << 8)]
-set			AT91SAM9_PMC_MDIV_1		[expr (0 << 8)]	;# [SAM9,CAP9 only]
-set			AT91SAM9_PMC_MDIV_2		[expr (1 << 8)]
-set			AT91SAM9_PMC_MDIV_4		[expr (2 << 8)]
-set			AT91SAM9_PMC_MDIV_6		[expr (3 << 8)]	;# [some SAM9 only]
-set			AT91SAM9_PMC_MDIV_3		[expr (3 << 8)]	;# [some SAM9 only]
-set		AT91_PMC_PDIV		[expr (1 << 12)]		;# Processor Clock Division [some SAM9 only]
-set			AT91_PMC_PDIV_1			[expr (0 << 12)]
-set			AT91_PMC_PDIV_2			[expr (1 << 12)]
-set		AT91_PMC_PLLADIV2	[expr (1 << 12)]		;# PLLA divisor by 2 [some SAM9 only]
-set			AT91_PMC_PLLADIV2_OFF		[expr (0 << 12)]
-set			AT91_PMC_PLLADIV2_ON		[expr (1 << 12)]
+set	AT91_PMC_MCKR		[expr {$AT91_PMC + 0x30}]	;# Master Clock Register
+set		AT91_PMC_CSS		[expr {3 <<  0}]		;# Master Clock Selection
+set			AT91_PMC_CSS_SLOW		[expr {0 << 0}]
+set			AT91_PMC_CSS_MAIN		[expr {1 << 0}]
+set			AT91_PMC_CSS_PLLA		[expr {2 << 0}]
+set			AT91_PMC_CSS_PLLB		[expr {3 << 0}]
+set			AT91_PMC_CSS_UPLL		[expr {3 << 0}]	;# [some SAM9 only]
+set		AT91_PMC_PRES		[expr {7 <<  2}]		;# Master Clock Prescaler
+set			AT91_PMC_PRES_1			[expr {0 << 2}]
+set			AT91_PMC_PRES_2			[expr {1 << 2}]
+set			AT91_PMC_PRES_4			[expr {2 << 2}]
+set			AT91_PMC_PRES_8			[expr {3 << 2}]
+set			AT91_PMC_PRES_16		[expr {4 << 2}]
+set			AT91_PMC_PRES_32		[expr {5 << 2}]
+set			AT91_PMC_PRES_64		[expr {6 << 2}]
+set		AT91_PMC_MDIV		[expr {3 <<  8}]		;# Master Clock Division
+set			AT91RM9200_PMC_MDIV_1		[expr {0 << 8}]	;# [AT91RM9200 only]
+set			AT91RM9200_PMC_MDIV_2		[expr {1 << 8}]
+set			AT91RM9200_PMC_MDIV_3		[expr {2 << 8}]
+set			AT91RM9200_PMC_MDIV_4		[expr {3 << 8}]
+set			AT91SAM9_PMC_MDIV_1		[expr {0 << 8}]	;# [SAM9,CAP9 only]
+set			AT91SAM9_PMC_MDIV_2		[expr {1 << 8}]
+set			AT91SAM9_PMC_MDIV_4		[expr {2 << 8}]
+set			AT91SAM9_PMC_MDIV_6		[expr {3 << 8}]	;# [some SAM9 only]
+set			AT91SAM9_PMC_MDIV_3		[expr {3 << 8}]	;# [some SAM9 only]
+set		AT91_PMC_PDIV		[expr {1 << 12}]		;# Processor Clock Division [some SAM9 only]
+set			AT91_PMC_PDIV_1			[expr {0 << 12}]
+set			AT91_PMC_PDIV_2			[expr {1 << 12}]
+set		AT91_PMC_PLLADIV2	[expr {1 << 12}]		;# PLLA divisor by 2 [some SAM9 only]
+set			AT91_PMC_PLLADIV2_OFF		[expr {0 << 12}]
+set			AT91_PMC_PLLADIV2_ON		[expr {1 << 12}]
 
-set	AT91_PMC_USB		[expr ($AT91_PMC + 0x38)]	;# USB Clock Register [some SAM9 only]
-set		AT91_PMC_USBS		[expr (0x1 <<  0)]		;# USB OHCI Input clock selection
-set			AT91_PMC_USBS_PLLA		[expr (0 << 0)]
-set			AT91_PMC_USBS_UPLL		[expr (1 << 0)]
-set		AT91_PMC_OHCIUSBDIV	[expr (0xF <<  8)]		;# Divider for USB OHCI Clock
+set	AT91_PMC_USB		[expr {$AT91_PMC + 0x38}]	;# USB Clock Register [some SAM9 only]
+set		AT91_PMC_USBS		[expr {0x1 <<  0}]		;# USB OHCI Input clock selection
+set			AT91_PMC_USBS_PLLA		[expr {0 << 0}]
+set			AT91_PMC_USBS_UPLL		[expr {1 << 0}]
+set		AT91_PMC_OHCIUSBDIV	[expr {0xF <<  8}]		;# Divider for USB OHCI Clock
 
-;# set	AT91_PMC_PCKR(n)	[expr ($AT91_PMC + 0x40 + ((n) * 4))]	;# Programmable Clock 0-N Registers
-set		AT91_PMC_CSSMCK		[expr (0x1 <<  8)]		;# CSS or Master Clock Selection
-set			AT91_PMC_CSSMCK_CSS		[expr (0 << 8)]
-set			AT91_PMC_CSSMCK_MCK		[expr (1 << 8)]
+;# set	AT91_PMC_PCKR(n)	[expr {$AT91_PMC + 0x40 + ((n) * 4)}]	;# Programmable Clock 0-N Registers
+set		AT91_PMC_CSSMCK		[expr {0x1 <<  8}]		;# CSS or Master Clock Selection
+set			AT91_PMC_CSSMCK_CSS		[expr {0 << 8}]
+set			AT91_PMC_CSSMCK_MCK		[expr {1 << 8}]
 
-set	AT91_PMC_IER		[expr ($AT91_PMC + 0x60)]	;# Interrupt Enable Register
-set	AT91_PMC_IDR		[expr ($AT91_PMC + 0x64)]	;# Interrupt Disable Register
-set	AT91_PMC_SR		[expr ($AT91_PMC + 0x68)]	;# Status Register
-set		AT91_PMC_MOSCS		[expr (1 <<  0)]		;# MOSCS Flag
-set		AT91_PMC_LOCKA		[expr (1 <<  1)]		;# PLLA Lock
-set		AT91_PMC_LOCKB		[expr (1 <<  2)]		;# PLLB Lock
-set		AT91_PMC_MCKRDY		[expr (1 <<  3)]		;# Master Clock
-set		AT91_PMC_LOCKU		[expr (1 <<  6)]		;# UPLL Lock [some SAM9, AT91CAP9 only]
-set		AT91_PMC_OSCSEL		[expr (1 <<  7)]		;# Slow Clock Oscillator [AT91CAP9 revC only]
-set		AT91_PMC_PCK0RDY	[expr (1 <<  8)]		;# Programmable Clock 0
-set		AT91_PMC_PCK1RDY	[expr (1 <<  9)]		;# Programmable Clock 1
-set		AT91_PMC_PCK2RDY	[expr (1 << 10)]		;# Programmable Clock 2
-set		AT91_PMC_PCK3RDY	[expr (1 << 11)]		;# Programmable Clock 3
-set	AT91_PMC_IMR		[expr ($AT91_PMC + 0x6c)]	;# Interrupt Mask Register
+set	AT91_PMC_IER		[expr {$AT91_PMC + 0x60}]	;# Interrupt Enable Register
+set	AT91_PMC_IDR		[expr {$AT91_PMC + 0x64}]	;# Interrupt Disable Register
+set	AT91_PMC_SR		[expr {$AT91_PMC + 0x68}]	;# Status Register
+set		AT91_PMC_MOSCS		[expr {1 <<  0}]		;# MOSCS Flag
+set		AT91_PMC_LOCKA		[expr {1 <<  1}]		;# PLLA Lock
+set		AT91_PMC_LOCKB		[expr {1 <<  2}]		;# PLLB Lock
+set		AT91_PMC_MCKRDY		[expr {1 <<  3}]		;# Master Clock
+set		AT91_PMC_LOCKU		[expr {1 <<  6}]		;# UPLL Lock [some SAM9, AT91CAP9 only]
+set		AT91_PMC_OSCSEL		[expr {1 <<  7}]		;# Slow Clock Oscillator [AT91CAP9 revC only]
+set		AT91_PMC_PCK0RDY	[expr {1 <<  8}]		;# Programmable Clock 0
+set		AT91_PMC_PCK1RDY	[expr {1 <<  9}]		;# Programmable Clock 1
+set		AT91_PMC_PCK2RDY	[expr {1 << 10}]		;# Programmable Clock 2
+set		AT91_PMC_PCK3RDY	[expr {1 << 11}]		;# Programmable Clock 3
+set	AT91_PMC_IMR		[expr {$AT91_PMC + 0x6c}]	;# Interrupt Mask Register
 
-set AT91_PMC_PROT		[expr ($AT91_PMC + 0xe4)]	;# Protect Register [AT91CAP9 revC only]
+set AT91_PMC_PROT		[expr {$AT91_PMC + 0xe4}]	;# Protect Register [AT91CAP9 revC only]
 set		AT91_PMC_PROTKEY	0x504d4301	;# Activation Code
 
-set AT91_PMC_VER		[expr ($AT91_PMC + 0xfc)]	;# PMC Module Version [AT91CAP9 only]
+set AT91_PMC_VER		[expr {$AT91_PMC + 0xfc}]	;# PMC Module Version [AT91CAP9 only]
diff --git a/tcl/chip/atmel/at91/at91_rstc.cfg b/tcl/chip/atmel/at91/at91_rstc.cfg
index ed60822..6673fe6 100644
--- a/tcl/chip/atmel/at91/at91_rstc.cfg
+++ b/tcl/chip/atmel/at91/at91_rstc.cfg
@@ -1,21 +1,21 @@
-set AT91_RSTC_CR		[expr ($AT91_RSTC + 0x00)]	;# Reset Controller Control Register
-set		AT91_RSTC_PROCRST	[expr (1 << 0)]		;# Processor Reset
-set		AT91_RSTC_PERRST	[expr (1 << 2)]		;# Peripheral Reset
-set		AT91_RSTC_EXTRST	[expr (1 << 3)]		;# External Reset
-set		AT91_RSTC_KEY		[expr (0xa5 << 24)]		;# KEY Password
+set AT91_RSTC_CR		[expr {$AT91_RSTC + 0x00}]	;# Reset Controller Control Register
+set		AT91_RSTC_PROCRST	[expr {1 << 0}]		;# Processor Reset
+set		AT91_RSTC_PERRST	[expr {1 << 2}]		;# Peripheral Reset
+set		AT91_RSTC_EXTRST	[expr {1 << 3}]		;# External Reset
+set		AT91_RSTC_KEY		[expr {0xa5 << 24}]		;# KEY Password
 
-set AT91_RSTC_SR		[expr ($AT91_RSTC + 0x04)]	;# Reset Controller Status Register
-set		AT91_RSTC_URSTS		[expr (1 << 0)]		;# User Reset Status
-set		AT91_RSTC_RSTTYP	[expr (7 << 8)]		;# Reset Type
-set			AT91_RSTC_RSTTYP_GENERAL	[expr (0 << 8)]
-set			AT91_RSTC_RSTTYP_WAKEUP		[expr (1 << 8)]
-set			AT91_RSTC_RSTTYP_WATCHDOG	[expr (2 << 8)]
-set			AT91_RSTC_RSTTYP_SOFTWARE	[expr (3 << 8)]
-set			AT91_RSTC_RSTTYP_USER	[expr (4 << 8)]
-set		AT91_RSTC_NRSTL		[expr (1 << 16)]		;# NRST Pin Level
-set		AT91_RSTC_SRCMP		[expr (1 << 17)]		;# Software Reset Command in Progress
+set AT91_RSTC_SR		[expr {$AT91_RSTC + 0x04}]	;# Reset Controller Status Register
+set		AT91_RSTC_URSTS		[expr {1 << 0}]		;# User Reset Status
+set		AT91_RSTC_RSTTYP	[expr {7 << 8}]		;# Reset Type
+set			AT91_RSTC_RSTTYP_GENERAL	[expr {0 << 8}]
+set			AT91_RSTC_RSTTYP_WAKEUP		[expr {1 << 8}]
+set			AT91_RSTC_RSTTYP_WATCHDOG	[expr {2 << 8}]
+set			AT91_RSTC_RSTTYP_SOFTWARE	[expr {3 << 8}]
+set			AT91_RSTC_RSTTYP_USER	[expr {4 << 8}]
+set		AT91_RSTC_NRSTL		[expr {1 << 16}]		;# NRST Pin Level
+set		AT91_RSTC_SRCMP		[expr {1 << 17}]		;# Software Reset Command in Progress
 
-set AT91_RSTC_MR		[expr ($AT91_RSTC + 0x08)]	;# Reset Controller Mode Register
-set		AT91_RSTC_URSTEN	[expr (1 << 0)]		;# User Reset Enable
-set		AT91_RSTC_URSTIEN	[expr (1 << 4)]		;# User Reset Interrupt Enable
-set		AT91_RSTC_ERSTL		[expr (0xf << 8)]		;# External Reset Length
+set AT91_RSTC_MR		[expr {$AT91_RSTC + 0x08}]	;# Reset Controller Mode Register
+set		AT91_RSTC_URSTEN	[expr {1 << 0}]		;# User Reset Enable
+set		AT91_RSTC_URSTIEN	[expr {1 << 4}]		;# User Reset Interrupt Enable
+set		AT91_RSTC_ERSTL		[expr {0xf << 8}]		;# External Reset Length
diff --git a/tcl/chip/atmel/at91/at91_wdt.cfg b/tcl/chip/atmel/at91/at91_wdt.cfg
index a263cc7..9b4e817 100644
--- a/tcl/chip/atmel/at91/at91_wdt.cfg
+++ b/tcl/chip/atmel/at91/at91_wdt.cfg
@@ -1,17 +1,17 @@
-set AT91_WDT_CR		[expr ($AT91_WDT + 0x00)]	;# Watchdog Control Register
-set		AT91_WDT_WDRSTT		[expr (1    << 0)]	;# Restart
-set		AT91_WDT_KEY		[expr (0xa5 << 24)]	;# KEY Password
+set AT91_WDT_CR		[expr {$AT91_WDT + 0x00}]	;# Watchdog Control Register
+set		AT91_WDT_WDRSTT		[expr {1    << 0}]	;# Restart
+set		AT91_WDT_KEY		[expr {0xa5 << 24}]	;# KEY Password
 
-set AT91_WDT_MR		[expr ($AT91_WDT + 0x04)]	;# Watchdog Mode Register
-set		AT91_WDT_WDV		[expr (0xfff << 0)]	;# Counter Value
-set		AT91_WDT_WDFIEN		[expr (1     << 12)]	;# Fault Interrupt Enable
-set		AT91_WDT_WDRSTEN	[expr (1     << 13)]	;# Reset Processor
-set		AT91_WDT_WDRPROC	[expr (1     << 14)]	;# Timer Restart
-set		AT91_WDT_WDDIS		[expr (1     << 15)]	;# Watchdog Disable
-set		AT91_WDT_WDD		[expr (0xfff << 16)]	;# Delta Value
-set		AT91_WDT_WDDBGHLT	[expr (1     << 28)]	;# Debug Halt
-set		AT91_WDT_WDIDLEHLT	[expr (1     << 29)]	;# Idle Halt
+set AT91_WDT_MR		[expr {$AT91_WDT + 0x04}]	;# Watchdog Mode Register
+set		AT91_WDT_WDV		[expr {0xfff << 0}]	;# Counter Value
+set		AT91_WDT_WDFIEN		[expr {1     << 12}]	;# Fault Interrupt Enable
+set		AT91_WDT_WDRSTEN	[expr {1     << 13}]	;# Reset Processor
+set		AT91_WDT_WDRPROC	[expr {1     << 14}]	;# Timer Restart
+set		AT91_WDT_WDDIS		[expr {1     << 15}]	;# Watchdog Disable
+set		AT91_WDT_WDD		[expr {0xfff << 16}]	;# Delta Value
+set		AT91_WDT_WDDBGHLT	[expr {1     << 28}]	;# Debug Halt
+set		AT91_WDT_WDIDLEHLT	[expr {1     << 29}]	;# Idle Halt
 
-set AT91_WDT_SR		[expr ($AT91_WDT + 0x08)]	;# Watchdog Status Register
-set		AT91_WDT_WDUNF		[expr (1 << 0)]		;# Watchdog Underflow
-set		AT91_WDT_WDERR		[expr (1 << 1)]		;# Watchdog Error
+set AT91_WDT_SR		[expr {$AT91_WDT + 0x08}]	;# Watchdog Status Register
+set		AT91_WDT_WDUNF		[expr {1 << 0}]		;# Watchdog Underflow
+set		AT91_WDT_WDERR		[expr {1 << 1}]		;# Watchdog Error
diff --git a/tcl/chip/atmel/at91/at91sam9261_matrix.cfg b/tcl/chip/atmel/at91/at91sam9261_matrix.cfg
index dc8de23..238e658 100644
--- a/tcl/chip/atmel/at91/at91sam9261_matrix.cfg
+++ b/tcl/chip/atmel/at91/at91sam9261_matrix.cfg
@@ -1,46 +1,46 @@
 
-set AT91_MATRIX_MCFG	[expr ($AT91_MATRIX + 0x00)]	;# Master Configuration Register #
-set		AT91_MATRIX_RCB0	[expr (1 << 0)]		;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)
-set		AT91_MATRIX_RCB1	[expr (1 << 1)]		;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master)
+set AT91_MATRIX_MCFG	[expr {$AT91_MATRIX + 0x00}]	;# Master Configuration Register #
+set		AT91_MATRIX_RCB0	[expr {1 << 0}]		;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)
+set		AT91_MATRIX_RCB1	[expr {1 << 1}]		;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master)
 
-set AT91_MATRIX_SCFG0	[expr ($AT91_MATRIX + 0x04)]	;# Slave Configuration Register 0
-set AT91_MATRIX_SCFG1	[expr ($AT91_MATRIX + 0x08)]	;# Slave Configuration Register 1
-set AT91_MATRIX_SCFG2	[expr ($AT91_MATRIX + 0x0C)]	;# Slave Configuration Register 2
-set AT91_MATRIX_SCFG3	[expr ($AT91_MATRIX + 0x10)]	;# Slave Configuration Register 3
-set AT91_MATRIX_SCFG4	[expr ($AT91_MATRIX + 0x14)]	;# Slave Configuration Register 4
-set		AT91_MATRIX_SLOT_CYCLE		[expr (0xff << 0)]	;# Maximum Number of Allowed Cycles for a Burst
-set		AT91_MATRIX_DEFMSTR_TYPE	[expr (3    << 16)]	;# Default Master Type
-set			AT91_MATRIX_DEFMSTR_TYPE_NONE	[expr (0 << 16)]
-set			AT91_MATRIX_DEFMSTR_TYPE_LAST	[expr (1 << 16)]
-set			AT91_MATRIX_DEFMSTR_TYPE_FIXED	[expr (2 << 16)]
-set		AT91_MATRIX_FIXED_DEFMSTR	[expr (7    << 18)]	;# Fixed Index of Default Master
+set AT91_MATRIX_SCFG0	[expr {$AT91_MATRIX + 0x04}]	;# Slave Configuration Register 0
+set AT91_MATRIX_SCFG1	[expr {$AT91_MATRIX + 0x08}]	;# Slave Configuration Register 1
+set AT91_MATRIX_SCFG2	[expr {$AT91_MATRIX + 0x0C}]	;# Slave Configuration Register 2
+set AT91_MATRIX_SCFG3	[expr {$AT91_MATRIX + 0x10}]	;# Slave Configuration Register 3
+set AT91_MATRIX_SCFG4	[expr {$AT91_MATRIX + 0x14}]	;# Slave Configuration Register 4
+set		AT91_MATRIX_SLOT_CYCLE		[expr {0xff << 0}]	;# Maximum Number of Allowed Cycles for a Burst
+set		AT91_MATRIX_DEFMSTR_TYPE	[expr {3    << 16}]	;# Default Master Type
+set			AT91_MATRIX_DEFMSTR_TYPE_NONE	[expr {0 << 16}]
+set			AT91_MATRIX_DEFMSTR_TYPE_LAST	[expr {1 << 16}]
+set			AT91_MATRIX_DEFMSTR_TYPE_FIXED	[expr {2 << 16}]
+set		AT91_MATRIX_FIXED_DEFMSTR	[expr {7    << 18}]	;# Fixed Index of Default Master
 
-set AT91_MATRIX_TCR		[expr ($AT91_MATRIX + 0x24)]	;# TCM Configuration Register
-set		AT91_MATRIX_ITCM_SIZE		[expr (0xf << 0)]	;# Size of ITCM enabled memory block
-set			AT91_MATRIX_ITCM_0		[expr (0 << 0)]
-set			AT91_MATRIX_ITCM_16		[expr (5 << 0)]
-set			AT91_MATRIX_ITCM_32		[expr (6 << 0)]
-set			AT91_MATRIX_ITCM_64		[expr (7 << 0)]
-set		AT91_MATRIX_DTCM_SIZE		[expr (0xf << 4)]	;# Size of DTCM enabled memory block
-set			AT91_MATRIX_DTCM_0		[expr (0 << 4)]
-set			AT91_MATRIX_DTCM_16		[expr (5 << 4)]
-set			AT91_MATRIX_DTCM_32		[expr (6 << 4)]
-set			AT91_MATRIX_DTCM_64		[expr (7 << 4)]
+set AT91_MATRIX_TCR		[expr {$AT91_MATRIX + 0x24}]	;# TCM Configuration Register
+set		AT91_MATRIX_ITCM_SIZE		[expr {0xf << 0}]	;# Size of ITCM enabled memory block
+set			AT91_MATRIX_ITCM_0		[expr {0 << 0}]
+set			AT91_MATRIX_ITCM_16		[expr {5 << 0}]
+set			AT91_MATRIX_ITCM_32		[expr {6 << 0}]
+set			AT91_MATRIX_ITCM_64		[expr {7 << 0}]
+set		AT91_MATRIX_DTCM_SIZE		[expr {0xf << 4}]	;# Size of DTCM enabled memory block
+set			AT91_MATRIX_DTCM_0		[expr {0 << 4}]
+set			AT91_MATRIX_DTCM_16		[expr {5 << 4}]
+set			AT91_MATRIX_DTCM_32		[expr {6 << 4}]
+set			AT91_MATRIX_DTCM_64		[expr {7 << 4}]
 
-set AT91_MATRIX_EBICSA	[expr ($AT91_MATRIX + 0x30)]	;# EBI Chip Select Assignment Register
-set		AT91_MATRIX_CS1A		[expr (1 << 1)]	;# Chip Select 1 Assignment
-set			AT91_MATRIX_CS1A_SMC		[expr (0 << 1)]
-set			AT91_MATRIX_CS1A_SDRAMC		[expr (1 << 1)]
-set		AT91_MATRIX_CS3A		[expr (1 << 3)]	;# Chip Select 3 Assignment
-set			AT91_MATRIX_CS3A_SMC		[expr (0 << 3)]
-set			AT91_MATRIX_CS3A_SMC_SMARTMEDIA	[expr (1 << 3)]
-set		AT91_MATRIX_CS4A		[expr (1 << 4)]	;# Chip Select 4 Assignment
-set			AT91_MATRIX_CS4A_SMC		[expr (0 << 4)]
-set			AT91_MATRIX_CS4A_SMC_CF1	[expr (1 << 4)]
-set		AT91_MATRIX_CS5A		[expr (1 << 5)]	;# Chip Select 5 Assignment
-set			AT91_MATRIX_CS5A_SMC		[expr (0 << 5)]
-set			AT91_MATRIX_CS5A_SMC_CF2	[expr (1 << 5)]
-set		AT91_MATRIX_DBPUC		[expr (1 << 8)]	;# Data Bus Pull-up Configuration
+set AT91_MATRIX_EBICSA	[expr {$AT91_MATRIX + 0x30}]	;# EBI Chip Select Assignment Register
+set		AT91_MATRIX_CS1A		[expr {1 << 1}]	;# Chip Select 1 Assignment
+set			AT91_MATRIX_CS1A_SMC		[expr {0 << 1}]
+set			AT91_MATRIX_CS1A_SDRAMC		[expr {1 << 1}]
+set		AT91_MATRIX_CS3A		[expr {1 << 3}]	;# Chip Select 3 Assignment
+set			AT91_MATRIX_CS3A_SMC		[expr {0 << 3}]
+set			AT91_MATRIX_CS3A_SMC_SMARTMEDIA	[expr {1 << 3}]
+set		AT91_MATRIX_CS4A		[expr {1 << 4}]	;# Chip Select 4 Assignment
+set			AT91_MATRIX_CS4A_SMC		[expr {0 << 4}]
+set			AT91_MATRIX_CS4A_SMC_CF1	[expr {1 << 4}]
+set		AT91_MATRIX_CS5A		[expr {1 << 5}]	;# Chip Select 5 Assignment
+set			AT91_MATRIX_CS5A_SMC		[expr {0 << 5}]
+set			AT91_MATRIX_CS5A_SMC_CF2	[expr {1 << 5}]
+set		AT91_MATRIX_DBPUC		[expr {1 << 8}]	;# Data Bus Pull-up Configuration
 
-set AT91_MATRIX_USBPUCR	[expr ($AT91_MATRIX + 0x34)]	;# USB Pad Pull-Up Control Register
-set		AT91_MATRIX_USBPUCR_PUON	[expr (1 << 30)]	;# USB Device PAD Pull-up Enable
+set AT91_MATRIX_USBPUCR	[expr {$AT91_MATRIX + 0x34}]	;# USB Pad Pull-Up Control Register
+set		AT91_MATRIX_USBPUCR_PUON	[expr {1 << 30}]	;# USB Device PAD Pull-up Enable
diff --git a/tcl/chip/atmel/at91/at91sam9263_matrix.cfg b/tcl/chip/atmel/at91/at91sam9263_matrix.cfg
index f287cd9..b4a07d3 100644
--- a/tcl/chip/atmel/at91/at91sam9263_matrix.cfg
+++ b/tcl/chip/atmel/at91/at91sam9263_matrix.cfg
@@ -1,110 +1,110 @@
-set AT91_MATRIX_MCFG0	[expr ($AT91_MATRIX + 0x00)]	;# Master Configuration Register 0
-set AT91_MATRIX_MCFG1	[expr ($AT91_MATRIX + 0x04)]	;# Master Configuration Register 1
-set AT91_MATRIX_MCFG2	[expr ($AT91_MATRIX + 0x08)]	;# Master Configuration Register 2
-set AT91_MATRIX_MCFG3	[expr ($AT91_MATRIX + 0x0C)]	;# Master Configuration Register 3
-set AT91_MATRIX_MCFG4	[expr ($AT91_MATRIX + 0x10)]	;# Master Configuration Register 4
-set AT91_MATRIX_MCFG5	[expr ($AT91_MATRIX + 0x14)]	;# Master Configuration Register 5
-set AT91_MATRIX_MCFG6	[expr ($AT91_MATRIX + 0x18)]	;# Master Configuration Register 6
-set AT91_MATRIX_MCFG7	[expr ($AT91_MATRIX + 0x1C)]	;# Master Configuration Register 7
-set AT91_MATRIX_MCFG8	[expr ($AT91_MATRIX + 0x20)]	;# Master Configuration Register 8
-set		AT91_MATRIX_ULBT	[expr (7 << 0)]	;# Undefined Length Burst Type
-set			AT91_MATRIX_ULBT_INFINITE	[expr (0 << 0)]
-set			AT91_MATRIX_ULBT_SINGLE		[expr (1 << 0)]
-set			AT91_MATRIX_ULBT_FOUR		[expr (2 << 0)]
-set			AT91_MATRIX_ULBT_EIGHT		[expr (3 << 0)]
-set			AT91_MATRIX_ULBT_SIXTEEN	[expr (4 << 0)]
+set AT91_MATRIX_MCFG0	[expr {$AT91_MATRIX + 0x00}]	;# Master Configuration Register 0
+set AT91_MATRIX_MCFG1	[expr {$AT91_MATRIX + 0x04}]	;# Master Configuration Register 1
+set AT91_MATRIX_MCFG2	[expr {$AT91_MATRIX + 0x08}]	;# Master Configuration Register 2
+set AT91_MATRIX_MCFG3	[expr {$AT91_MATRIX + 0x0C}]	;# Master Configuration Register 3
+set AT91_MATRIX_MCFG4	[expr {$AT91_MATRIX + 0x10}]	;# Master Configuration Register 4
+set AT91_MATRIX_MCFG5	[expr {$AT91_MATRIX + 0x14}]	;# Master Configuration Register 5
+set AT91_MATRIX_MCFG6	[expr {$AT91_MATRIX + 0x18}]	;# Master Configuration Register 6
+set AT91_MATRIX_MCFG7	[expr {$AT91_MATRIX + 0x1C}]	;# Master Configuration Register 7
+set AT91_MATRIX_MCFG8	[expr {$AT91_MATRIX + 0x20}]	;# Master Configuration Register 8
+set		AT91_MATRIX_ULBT	[expr {7 << 0}]	;# Undefined Length Burst Type
+set			AT91_MATRIX_ULBT_INFINITE	[expr {0 << 0}]
+set			AT91_MATRIX_ULBT_SINGLE		[expr {1 << 0}]
+set			AT91_MATRIX_ULBT_FOUR		[expr {2 << 0}]
+set			AT91_MATRIX_ULBT_EIGHT		[expr {3 << 0}]
+set			AT91_MATRIX_ULBT_SIXTEEN	[expr {4 << 0}]
 
-set AT91_MATRIX_SCFG0	[expr ($AT91_MATRIX + 0x40)]	;# Slave Configuration Register 0
-set AT91_MATRIX_SCFG1	[expr ($AT91_MATRIX + 0x44)]	;# Slave Configuration Register 1
-set AT91_MATRIX_SCFG2	[expr ($AT91_MATRIX + 0x48)]	;# Slave Configuration Register 2
-set AT91_MATRIX_SCFG3	[expr ($AT91_MATRIX + 0x4C)]	;# Slave Configuration Register 3
-set AT91_MATRIX_SCFG4	[expr ($AT91_MATRIX + 0x50)]	;# Slave Configuration Register 4
-set AT91_MATRIX_SCFG5	[expr ($AT91_MATRIX + 0x54)]	;# Slave Configuration Register 5
-set AT91_MATRIX_SCFG6	[expr ($AT91_MATRIX + 0x58)]	;# Slave Configuration Register 6
-set AT91_MATRIX_SCFG7	[expr ($AT91_MATRIX + 0x5C)]	;# Slave Configuration Register 7
-set		AT91_MATRIX_SLOT_CYCLE		[expr (0xff << 0)]	;# Maximum Number of Allowed Cycles for a Burst
-set		AT91_MATRIX_DEFMSTR_TYPE	[expr (3    << 16)]	;# Default Master Type
-set			AT91_MATRIX_DEFMSTR_TYPE_NONE	[expr (0 << 16)]
-set			AT91_MATRIX_DEFMSTR_TYPE_LAST	[expr (1 << 16)]
-set			AT91_MATRIX_DEFMSTR_TYPE_FIXED	[expr (2 << 16)]
-set		AT91_MATRIX_FIXED_DEFMSTR	[expr (0xf  << 18)]	;# Fixed Index of Default Master
-set		AT91_MATRIX_ARBT		[expr (3    << 24)]	;# Arbitration Type
-set			AT91_MATRIX_ARBT_ROUND_ROBIN	[expr (0 << 24)]
-set			AT91_MATRIX_ARBT_FIXED_PRIORITY	[expr (1 << 24)]
+set AT91_MATRIX_SCFG0	[expr {$AT91_MATRIX + 0x40}]	;# Slave Configuration Register 0
+set AT91_MATRIX_SCFG1	[expr {$AT91_MATRIX + 0x44}]	;# Slave Configuration Register 1
+set AT91_MATRIX_SCFG2	[expr {$AT91_MATRIX + 0x48}]	;# Slave Configuration Register 2
+set AT91_MATRIX_SCFG3	[expr {$AT91_MATRIX + 0x4C}]	;# Slave Configuration Register 3
+set AT91_MATRIX_SCFG4	[expr {$AT91_MATRIX + 0x50}]	;# Slave Configuration Register 4
+set AT91_MATRIX_SCFG5	[expr {$AT91_MATRIX + 0x54}]	;# Slave Configuration Register 5
+set AT91_MATRIX_SCFG6	[expr {$AT91_MATRIX + 0x58}]	;# Slave Configuration Register 6
+set AT91_MATRIX_SCFG7	[expr {$AT91_MATRIX + 0x5C}]	;# Slave Configuration Register 7
+set		AT91_MATRIX_SLOT_CYCLE		[expr {0xff << 0}]	;# Maximum Number of Allowed Cycles for a Burst
+set		AT91_MATRIX_DEFMSTR_TYPE	[expr {3    << 16}]	;# Default Master Type
+set			AT91_MATRIX_DEFMSTR_TYPE_NONE	[expr {0 << 16}]
+set			AT91_MATRIX_DEFMSTR_TYPE_LAST	[expr {1 << 16}]
+set			AT91_MATRIX_DEFMSTR_TYPE_FIXED	[expr {2 << 16}]
+set		AT91_MATRIX_FIXED_DEFMSTR	[expr {0xf  << 18}]	;# Fixed Index of Default Master
+set		AT91_MATRIX_ARBT		[expr {3    << 24}]	;# Arbitration Type
+set			AT91_MATRIX_ARBT_ROUND_ROBIN	[expr {0 << 24}]
+set			AT91_MATRIX_ARBT_FIXED_PRIORITY	[expr {1 << 24}]
 
-set AT91_MATRIX_PRAS0	[expr ($AT91_MATRIX + 0x80)]	;# Priority Register A for Slave 0
-set AT91_MATRIX_PRBS0	[expr ($AT91_MATRIX + 0x84)]	;# Priority Register B for Slave 0
-set AT91_MATRIX_PRAS1	[expr ($AT91_MATRIX + 0x88)]	;# Priority Register A for Slave 1
-set AT91_MATRIX_PRBS1	[expr ($AT91_MATRIX + 0x8C)]	;# Priority Register B for Slave 1
-set AT91_MATRIX_PRAS2	[expr ($AT91_MATRIX + 0x90)]	;# Priority Register A for Slave 2
-set AT91_MATRIX_PRBS2	[expr ($AT91_MATRIX + 0x94)]	;# Priority Register B for Slave 2
-set AT91_MATRIX_PRAS3	[expr ($AT91_MATRIX + 0x98)]	;# Priority Register A for Slave 3
-set AT91_MATRIX_PRBS3	[expr ($AT91_MATRIX + 0x9C)]	;# Priority Register B for Slave 3
-set AT91_MATRIX_PRAS4	[expr ($AT91_MATRIX + 0xA0)]	;# Priority Register A for Slave 4
-set AT91_MATRIX_PRBS4	[expr ($AT91_MATRIX + 0xA4)]	;# Priority Register B for Slave 4
-set AT91_MATRIX_PRAS5	[expr ($AT91_MATRIX + 0xA8)]	;# Priority Register A for Slave 5
-set AT91_MATRIX_PRBS5	[expr ($AT91_MATRIX + 0xAC)]	;# Priority Register B for Slave 5
-set AT91_MATRIX_PRAS6	[expr ($AT91_MATRIX + 0xB0)]	;# Priority Register A for Slave 6
-set AT91_MATRIX_PRBS6	[expr ($AT91_MATRIX + 0xB4)]	;# Priority Register B for Slave 6
-set AT91_MATRIX_PRAS7	[expr ($AT91_MATRIX + 0xB8)]	;# Priority Register A for Slave 7
-set AT91_MATRIX_PRBS7	[expr ($AT91_MATRIX + 0xBC)]	;# Priority Register B for Slave 7
-set		AT91_MATRIX_M0PR		[expr (3 << 0)]		;# Master 0 Priority
-set		AT91_MATRIX_M1PR		[expr (3 << 4)]		;# Master 1 Priority
-set		AT91_MATRIX_M2PR		[expr (3 << 8)]		;# Master 2 Priority
-set		AT91_MATRIX_M3PR		[expr (3 << 12)]	;# Master 3 Priority
-set		AT91_MATRIX_M4PR		[expr (3 << 16)]	;# Master 4 Priority
-set		AT91_MATRIX_M5PR		[expr (3 << 20)]	;# Master 5 Priority
-set		AT91_MATRIX_M6PR		[expr (3 << 24)]	;# Master 6 Priority
-set		AT91_MATRIX_M7PR		[expr (3 << 28)]	;# Master 7 Priority
-set		AT91_MATRIX_M8PR		[expr (3 << 0)]		;# Master 8 Priority (in Register B)
+set AT91_MATRIX_PRAS0	[expr {$AT91_MATRIX + 0x80}]	;# Priority Register A for Slave 0
+set AT91_MATRIX_PRBS0	[expr {$AT91_MATRIX + 0x84}]	;# Priority Register B for Slave 0
+set AT91_MATRIX_PRAS1	[expr {$AT91_MATRIX + 0x88}]	;# Priority Register A for Slave 1
+set AT91_MATRIX_PRBS1	[expr {$AT91_MATRIX + 0x8C}]	;# Priority Register B for Slave 1
+set AT91_MATRIX_PRAS2	[expr {$AT91_MATRIX + 0x90}]	;# Priority Register A for Slave 2
+set AT91_MATRIX_PRBS2	[expr {$AT91_MATRIX + 0x94}]	;# Priority Register B for Slave 2
+set AT91_MATRIX_PRAS3	[expr {$AT91_MATRIX + 0x98}]	;# Priority Register A for Slave 3
+set AT91_MATRIX_PRBS3	[expr {$AT91_MATRIX + 0x9C}]	;# Priority Register B for Slave 3
+set AT91_MATRIX_PRAS4	[expr {$AT91_MATRIX + 0xA0}]	;# Priority Register A for Slave 4
+set AT91_MATRIX_PRBS4	[expr {$AT91_MATRIX + 0xA4}]	;# Priority Register B for Slave 4
+set AT91_MATRIX_PRAS5	[expr {$AT91_MATRIX + 0xA8}]	;# Priority Register A for Slave 5
+set AT91_MATRIX_PRBS5	[expr {$AT91_MATRIX + 0xAC}]	;# Priority Register B for Slave 5
+set AT91_MATRIX_PRAS6	[expr {$AT91_MATRIX + 0xB0}]	;# Priority Register A for Slave 6
+set AT91_MATRIX_PRBS6	[expr {$AT91_MATRIX + 0xB4}]	;# Priority Register B for Slave 6
+set AT91_MATRIX_PRAS7	[expr {$AT91_MATRIX + 0xB8}]	;# Priority Register A for Slave 7
+set AT91_MATRIX_PRBS7	[expr {$AT91_MATRIX + 0xBC}]	;# Priority Register B for Slave 7
+set		AT91_MATRIX_M0PR		[expr {3 << 0}]		;# Master 0 Priority
+set		AT91_MATRIX_M1PR		[expr {3 << 4}]		;# Master 1 Priority
+set		AT91_MATRIX_M2PR		[expr {3 << 8}]		;# Master 2 Priority
+set		AT91_MATRIX_M3PR		[expr {3 << 12}]	;# Master 3 Priority
+set		AT91_MATRIX_M4PR		[expr {3 << 16}]	;# Master 4 Priority
+set		AT91_MATRIX_M5PR		[expr {3 << 20}]	;# Master 5 Priority
+set		AT91_MATRIX_M6PR		[expr {3 << 24}]	;# Master 6 Priority
+set		AT91_MATRIX_M7PR		[expr {3 << 28}]	;# Master 7 Priority
+set		AT91_MATRIX_M8PR		[expr {3 << 0}]		;# Master 8 Priority (in Register B)
 
-set AT91_MATRIX_MRCR	[expr ($AT91_MATRIX + 0x100)]	;# Master Remap Control Register
-set		AT91_MATRIX_RCB0		[expr (1 << 0)]	;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)
-set		AT91_MATRIX_RCB1		[expr (1 << 1)]	;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master)
-set		AT91_MATRIX_RCB2		[expr (1 << 2)]
-set		AT91_MATRIX_RCB3		[expr (1 << 3)]
-set		AT91_MATRIX_RCB4		[expr (1 << 4)]
-set		AT91_MATRIX_RCB5		[expr (1 << 5)]
-set		AT91_MATRIX_RCB6		[expr (1 << 6)]
-set		AT91_MATRIX_RCB7		[expr (1 << 7)]
-set		AT91_MATRIX_RCB8		[expr (1 << 8)]
+set AT91_MATRIX_MRCR	[expr {$AT91_MATRIX + 0x100}]	;# Master Remap Control Register
+set		AT91_MATRIX_RCB0		[expr {1 << 0}]	;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)
+set		AT91_MATRIX_RCB1		[expr {1 << 1}]	;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master)
+set		AT91_MATRIX_RCB2		[expr {1 << 2}]
+set		AT91_MATRIX_RCB3		[expr {1 << 3}]
+set		AT91_MATRIX_RCB4		[expr {1 << 4}]
+set		AT91_MATRIX_RCB5		[expr {1 << 5}]
+set		AT91_MATRIX_RCB6		[expr {1 << 6}]
+set		AT91_MATRIX_RCB7		[expr {1 << 7}]
+set		AT91_MATRIX_RCB8		[expr {1 << 8}]
 
-set AT91_MATRIX_TCMR	[expr ($AT91_MATRIX + 0x114)]	;# TCM Configuration Register
-set		AT91_MATRIX_ITCM_SIZE		[expr (0xf << 0)]	;# Size of ITCM enabled memory block
-set			AT91_MATRIX_ITCM_0		[expr (0 << 0)]
-set			AT91_MATRIX_ITCM_16		[expr (5 << 0)]
-set			AT91_MATRIX_ITCM_32		[expr (6 << 0)]
-set		AT91_MATRIX_DTCM_SIZE		[expr (0xf << 4)]	;# Size of DTCM enabled memory block
-set			AT91_MATRIX_DTCM_0		[expr (0 << 4)]
-set			AT91_MATRIX_DTCM_16		[expr (5 << 4)]
-set			AT91_MATRIX_DTCM_32		[expr (6 << 4)]
+set AT91_MATRIX_TCMR	[expr {$AT91_MATRIX + 0x114}]	;# TCM Configuration Register
+set		AT91_MATRIX_ITCM_SIZE		[expr {0xf << 0}]	;# Size of ITCM enabled memory block
+set			AT91_MATRIX_ITCM_0		[expr {0 << 0}]
+set			AT91_MATRIX_ITCM_16		[expr {5 << 0}]
+set			AT91_MATRIX_ITCM_32		[expr {6 << 0}]
+set		AT91_MATRIX_DTCM_SIZE		[expr {0xf << 4}]	;# Size of DTCM enabled memory block
+set			AT91_MATRIX_DTCM_0		[expr {0 << 4}]
+set			AT91_MATRIX_DTCM_16		[expr {5 << 4}]
+set			AT91_MATRIX_DTCM_32		[expr {6 << 4}]
 
-set AT91_MATRIX_EBI0CSA	[expr ($AT91_MATRIX + 0x120)]	;# EBI0 Chip Select Assignment Register
-set		AT91_MATRIX_EBI0_CS1A		[expr (1 << 1)]	;# Chip Select 1 Assignment
-set			AT91_MATRIX_EBI0_CS1A_SMC		[expr (0 << 1)]
-set			AT91_MATRIX_EBI0_CS1A_SDRAMC		[expr (1 << 1)]
-set		AT91_MATRIX_EBI0_CS3A		[expr (1 << 3)]	;# Chip Select 3 Assignmen
-set			AT91_MATRIX_EBI0_CS3A_SMC		[expr (0 << 3)]
-set			AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA	[expr (1 << 3)]
-set		AT91_MATRIX_EBI0_CS4A		[expr (1 << 4)]	;# Chip Select 4 Assignment
-set			AT91_MATRIX_EBI0_CS4A_SMC		[expr (0 << 4)]
-set			AT91_MATRIX_EBI0_CS4A_SMC_CF1		[expr (1 << 4)]
-set		AT91_MATRIX_EBI0_CS5A		[expr (1 << 5)]	;# Chip Select 5 Assignment
-set			AT91_MATRIX_EBI0_CS5A_SMC		[expr (0 << 5)]
-set			AT91_MATRIX_EBI0_CS5A_SMC_CF2		[expr (1 << 5)]
-set		AT91_MATRIX_EBI0_DBPUC		[expr (1 << 8)]	;# Data Bus Pull-up Configuration
-set		AT91_MATRIX_EBI0_VDDIOMSEL	[expr (1 << 16)]	;# Memory voltage selection
-set			AT91_MATRIX_EBI0_VDDIOMSEL_1_8V		[expr (0 << 16)]
-set			AT91_MATRIX_EBI0_VDDIOMSEL_3_3V		[expr (1 << 16)]
+set AT91_MATRIX_EBI0CSA	[expr {$AT91_MATRIX + 0x120}]	;# EBI0 Chip Select Assignment Register
+set		AT91_MATRIX_EBI0_CS1A		[expr {1 << 1}]	;# Chip Select 1 Assignment
+set			AT91_MATRIX_EBI0_CS1A_SMC		[expr {0 << 1}]
+set			AT91_MATRIX_EBI0_CS1A_SDRAMC		[expr {1 << 1}]
+set		AT91_MATRIX_EBI0_CS3A		[expr {1 << 3}]	;# Chip Select 3 Assignmen
+set			AT91_MATRIX_EBI0_CS3A_SMC		[expr {0 << 3}]
+set			AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA	[expr {1 << 3}]
+set		AT91_MATRIX_EBI0_CS4A		[expr {1 << 4}]	;# Chip Select 4 Assignment
+set			AT91_MATRIX_EBI0_CS4A_SMC		[expr {0 << 4}]
+set			AT91_MATRIX_EBI0_CS4A_SMC_CF1		[expr {1 << 4}]
+set		AT91_MATRIX_EBI0_CS5A		[expr {1 << 5}]	;# Chip Select 5 Assignment
+set			AT91_MATRIX_EBI0_CS5A_SMC		[expr {0 << 5}]
+set			AT91_MATRIX_EBI0_CS5A_SMC_CF2		[expr {1 << 5}]
+set		AT91_MATRIX_EBI0_DBPUC		[expr {1 << 8}]	;# Data Bus Pull-up Configuration
+set		AT91_MATRIX_EBI0_VDDIOMSEL	[expr {1 << 16}]	;# Memory voltage selection
+set			AT91_MATRIX_EBI0_VDDIOMSEL_1_8V		[expr {0 << 16}]
+set			AT91_MATRIX_EBI0_VDDIOMSEL_3_3V		[expr {1 << 16}]
 
-set AT91_MATRIX_EBI1CSA	[expr ($AT91_MATRIX + 0x124)]	;# EBI1 Chip Select Assignment Register
-set		AT91_MATRIX_EBI1_CS1A		[expr (1 << 1)]	;# Chip Select 1 Assignment
-set			AT91_MATRIX_EBI1_CS1A_SMC		[expr (0 << 1)]
-set			AT91_MATRIX_EBI1_CS1A_SDRAMC		[expr (1 << 1)]
-set		AT91_MATRIX_EBI1_CS2A		[expr (1 << 3)]	;# Chip Select 3 Assignment
-set			AT91_MATRIX_EBI1_CS2A_SMC		[expr (0 << 3)]
-set			AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA	[expr (1 << 3)]
-set		AT91_MATRIX_EBI1_DBPUC		[expr (1 << 8)]	;# Data Bus Pull-up Configuration
-set		AT91_MATRIX_EBI1_VDDIOMSEL	[expr (1 << 16)]	;# Memory voltage selection
-set			AT91_MATRIX_EBI1_VDDIOMSEL_1_8V		[expr (0 << 16)]
-set			AT91_MATRIX_EBI1_VDDIOMSEL_3_3V		[expr (1 << 16)]
+set AT91_MATRIX_EBI1CSA	[expr {$AT91_MATRIX + 0x124}]	;# EBI1 Chip Select Assignment Register
+set		AT91_MATRIX_EBI1_CS1A		[expr {1 << 1}]	;# Chip Select 1 Assignment
+set			AT91_MATRIX_EBI1_CS1A_SMC		[expr {0 << 1}]
+set			AT91_MATRIX_EBI1_CS1A_SDRAMC		[expr {1 << 1}]
+set		AT91_MATRIX_EBI1_CS2A		[expr {1 << 3}]	;# Chip Select 3 Assignment
+set			AT91_MATRIX_EBI1_CS2A_SMC		[expr {0 << 3}]
+set			AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA	[expr {1 << 3}]
+set		AT91_MATRIX_EBI1_DBPUC		[expr {1 << 8}]	;# Data Bus Pull-up Configuration
+set		AT91_MATRIX_EBI1_VDDIOMSEL	[expr {1 << 16}]	;# Memory voltage selection
+set			AT91_MATRIX_EBI1_VDDIOMSEL_1_8V		[expr {0 << 16}]
+set			AT91_MATRIX_EBI1_VDDIOMSEL_3_3V		[expr {1 << 16}]
diff --git a/tcl/chip/atmel/at91/at91sam9_init.cfg b/tcl/chip/atmel/at91/at91sam9_init.cfg
index 2d78d24..27611eb 100644
--- a/tcl/chip/atmel/at91/at91sam9_init.cfg
+++ b/tcl/chip/atmel/at91/at91sam9_init.cfg
@@ -11,9 +11,9 @@ proc at91sam9_reset_start { } {
 	jtag_rclk 8
 	halt
 	wait_halt 10000
-	set rstc_mr_val [expr $::AT91_RSTC_KEY]
-	set rstc_mr_val [expr ($rstc_mr_val | (5 << 8))]
-	set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)]
+	set rstc_mr_val $::AT91_RSTC_KEY
+	set rstc_mr_val [expr {$rstc_mr_val | (5 << 8)}]
+	set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
 	mww $::AT91_RSTC_MR $rstc_mr_val	;# RSTC_MR : enable user reset.
 }
 
@@ -21,28 +21,28 @@ proc at91sam9_reset_init { config } {
 
 	mww $::AT91_WDT_MR $config(wdt_mr_val)	;# disable watchdog
 
-	set ckgr_mor [expr ($::AT91_PMC_MOSCEN | (255 << 8))]
+	set ckgr_mor [expr {$::AT91_PMC_MOSCEN | (255 << 8)}]
 
 	mww $::AT91_CKGR_MOR $ckgr_mor	;# CKGR_MOR - enable main osc.
-	while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS] != $::AT91_PMC_MOSCS } { sleep 1 }
+	while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS}] != $::AT91_PMC_MOSCS } { sleep 1 }
 
-	set pllar_val	[expr $::AT91_PMC_PLLA_WR_ERRATA] ;# Bit 29 must be 1 when prog
-	set pllar_val	[expr ($pllar_val | $::AT91_PMC_OUT)]
-	set pllar_val	[expr ($pllar_val | $::AT91_PMC_PLLCOUNT)]
-	set pllar_val	[expr ($pllar_val | ($config(master_pll_mul) - 1) << 16)]
-	set pllar_val	[expr ($pllar_val | $config(master_pll_div))]
+	set pllar_val	$::AT91_PMC_PLLA_WR_ERRATA ;# Bit 29 must be 1 when prog
+	set pllar_val	[expr {$pllar_val | $::AT91_PMC_OUT}]
+	set pllar_val	[expr {$pllar_val | $::AT91_PMC_PLLCOUNT}]
+	set pllar_val	[expr {$pllar_val | ($config(master_pll_mul) - 1) << 16}]
+	set pllar_val	[expr {$pllar_val | $config(master_pll_div)}]
 
 	mww $::AT91_CKGR_PLLAR $pllar_val	 ;# CKGR_PLLA - (18.432MHz/13)*141 = 199.9 MHz
-	while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA] != $::AT91_PMC_LOCKA } { sleep 1 }
+	while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA}] != $::AT91_PMC_LOCKA } { sleep 1 }
 
 	;# PCK/2 = MCK Master Clock from PLLA
-	set mckr_val	[expr $::AT91_PMC_CSS_PLLA]
-	set mckr_val	[expr ($mckr_val | $::AT91_PMC_PRES_1)]
-	set mckr_val	[expr ($mckr_val | $::AT91SAM9_PMC_MDIV_2)]
-	set mckr_val	[expr ($mckr_val | $::AT91_PMC_PDIV_1)]
+	set mckr_val	$::AT91_PMC_CSS_PLLA
+	set mckr_val	[expr {$mckr_val | $::AT91_PMC_PRES_1}]
+	set mckr_val	[expr {$mckr_val | $::AT91SAM9_PMC_MDIV_2}]
+	set mckr_val	[expr {$mckr_val | $::AT91_PMC_PDIV_1}]
 
 	mww $::AT91_PMC_MCKR $mckr_val	;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz)
-	while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY] != $::AT91_PMC_MCKRDY } { sleep 1 }
+	while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY}] != $::AT91_PMC_MCKRDY } { sleep 1 }
 
 	## switch JTAG clock to highspeed clock
 	jtag_rclk 0
@@ -50,20 +50,20 @@ proc at91sam9_reset_init { config } {
 	arm7_9 dcc_downloads enable	;# Enable faster DCC downloads
 	arm7_9 fast_memory_access enable
 
-	set rstc_mr_val [expr ($::AT91_RSTC_KEY)]
-	set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)]
+	set rstc_mr_val $::AT91_RSTC_KEY
+	set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
 	mww $::AT91_RSTC_MR $rstc_mr_val	;# user reset enable
 
 	if { [info exists config(sdram_piod)] } {
-		set pdr_addr	[expr ($::AT91_PIOD + $::PIO_PDR)]
-		set pudr_addr	[expr ($::AT91_PIOD + $::PIO_PUDR)]
-		set asr_addr	[expr ($::AT91_PIOD + $::PIO_ASR)]
+		set pdr_addr	[expr {$::AT91_PIOD + $::PIO_PDR}]
+		set pudr_addr	[expr {$::AT91_PIOD + $::PIO_PUDR}]
+		set asr_addr	[expr {$::AT91_PIOD + $::PIO_ASR}]
 		mww $pdr_addr 0xffff0000				;# define PDC[31:16] as DATA[31:16]
 		mww $pudr_addr 0xffff0000				;# no pull-up for D[31:16]
 		mww $asr_addr 0xffff0000
 	} else {
-		set pdr_addr	[expr ($::AT91_PIOC + $::PIO_PDR)]
-		set pudr_addr	[expr ($::AT91_PIOC + $::PIO_PUDR)]
+		set pdr_addr	[expr {$::AT91_PIOC + $::PIO_PDR}]
+		set pudr_addr	[expr {$::AT91_PIOC + $::PIO_PUDR}]
 		mww $pdr_addr 0xffff0000				;# define PDC[31:16] as DATA[31:16]
 		mww $pudr_addr 0xffff0000				;# no pull-up for D[31:16]
 	}
diff --git a/tcl/chip/atmel/at91/at91sam9_sdramc.cfg b/tcl/chip/atmel/at91/at91sam9_sdramc.cfg
index dbca497..7b09369 100644
--- a/tcl/chip/atmel/at91/at91sam9_sdramc.cfg
+++ b/tcl/chip/atmel/at91/at91sam9_sdramc.cfg
@@ -1,7 +1,7 @@
 
 # SDRAM Controller (SDRAMC) registers
-set AT91_SDRAMC_MR		[expr ($AT91_SDRAMC + 0x00)]	;# SDRAM Controller Mode Register
-set		AT91_SDRAMC_MODE	[expr (0xf << 0)]	;# Command Mode
+set AT91_SDRAMC_MR		[expr {$AT91_SDRAMC + 0x00}]	;# SDRAM Controller Mode Register
+set		AT91_SDRAMC_MODE	[expr {0xf << 0}]	;# Command Mode
 set			AT91_SDRAMC_MODE_NORMAL		0
 set			AT91_SDRAMC_MODE_NOP		1
 set			AT91_SDRAMC_MODE_PRECHARGE	2
@@ -10,57 +10,57 @@ set			AT91_SDRAMC_MODE_REFRESH	4
 set			AT91_SDRAMC_MODE_EXT_LMR	5
 set			AT91_SDRAMC_MODE_DEEP		6
 
-set AT91_SDRAMC_TR		[expr ($AT91_SDRAMC + 0x04)]	;# SDRAM Controller Refresh Timer Register
-set		AT91_SDRAMC_COUNT	[expr (0xfff << 0)]		;# Refresh Timer Counter
+set AT91_SDRAMC_TR		[expr {$AT91_SDRAMC + 0x04}]	;# SDRAM Controller Refresh Timer Register
+set		AT91_SDRAMC_COUNT	[expr {0xfff << 0}]		;# Refresh Timer Counter
 
-set AT91_SDRAMC_CR		[expr ($AT91_SDRAMC + 0x08)]	;# SDRAM Controller Configuration Register
-set		AT91_SDRAMC_NC		[expr (3 << 0)]		;# Number of Column Bits
-set			AT91_SDRAMC_NC_8	[expr (0 << 0)]
-set			AT91_SDRAMC_NC_9	[expr (1 << 0)]
-set			AT91_SDRAMC_NC_10	[expr (2 << 0)]
-set			AT91_SDRAMC_NC_11	[expr (3 << 0)]
-set		AT91_SDRAMC_NR		[expr (3 << 2)]		;# Number of Row Bits
-set			AT91_SDRAMC_NR_11	[expr (0 << 2)]
-set			AT91_SDRAMC_NR_12	[expr (1 << 2)]
-set			AT91_SDRAMC_NR_13	[expr (2 << 2)]
-set		AT91_SDRAMC_NB		[expr (1 << 4)]		;# Number of Banks
-set			AT91_SDRAMC_NB_2	[expr (0 << 4)]
-set			AT91_SDRAMC_NB_4	[expr (1 << 4)]
-set		AT91_SDRAMC_CAS		[expr (3 << 5)]		;# CAS Latency
-set			AT91_SDRAMC_CAS_1	[expr (1 << 5)]
-set			AT91_SDRAMC_CAS_2	[expr (2 << 5)]
-set			AT91_SDRAMC_CAS_3	[expr (3 << 5)]
-set		AT91_SDRAMC_DBW		[expr (1 << 7)]		;# Data Bus Width
-set			AT91_SDRAMC_DBW_32	[expr (0 << 7)]
-set			AT91_SDRAMC_DBW_16	[expr (1 << 7)]
-set		AT91_SDRAMC_TWR		[expr (0xf <<  8)]		;# Write Recovery Delay
-set		AT91_SDRAMC_TRC		[expr (0xf << 12)]		;# Row Cycle Delay
-set		AT91_SDRAMC_TRP		[expr (0xf << 16)]		;# Row Precharge Delay
-set		AT91_SDRAMC_TRCD	[expr (0xf << 20)]		;# Row to Column Delay
-set		AT91_SDRAMC_TRAS	[expr (0xf << 24)]		;# Active to Precharge Delay
-set		AT91_SDRAMC_TXSR	[expr (0xf << 28)]		;# Exit Self Refresh to Active Delay
+set AT91_SDRAMC_CR		[expr {$AT91_SDRAMC + 0x08}]	;# SDRAM Controller Configuration Register
+set		AT91_SDRAMC_NC		[expr {3 << 0}]		;# Number of Column Bits
+set			AT91_SDRAMC_NC_8	[expr {0 << 0}]
+set			AT91_SDRAMC_NC_9	[expr {1 << 0}]
+set			AT91_SDRAMC_NC_10	[expr {2 << 0}]
+set			AT91_SDRAMC_NC_11	[expr {3 << 0}]
+set		AT91_SDRAMC_NR		[expr {3 << 2}]		;# Number of Row Bits
+set			AT91_SDRAMC_NR_11	[expr {0 << 2}]
+set			AT91_SDRAMC_NR_12	[expr {1 << 2}]
+set			AT91_SDRAMC_NR_13	[expr {2 << 2}]
+set		AT91_SDRAMC_NB		[expr {1 << 4}]		;# Number of Banks
+set			AT91_SDRAMC_NB_2	[expr {0 << 4}]
+set			AT91_SDRAMC_NB_4	[expr {1 << 4}]
+set		AT91_SDRAMC_CAS		[expr {3 << 5}]		;# CAS Latency
+set			AT91_SDRAMC_CAS_1	[expr {1 << 5}]
+set			AT91_SDRAMC_CAS_2	[expr {2 << 5}]
+set			AT91_SDRAMC_CAS_3	[expr {3 << 5}]
+set		AT91_SDRAMC_DBW		[expr {1 << 7}]		;# Data Bus Width
+set			AT91_SDRAMC_DBW_32	[expr {0 << 7}]
+set			AT91_SDRAMC_DBW_16	[expr {1 << 7}]
+set		AT91_SDRAMC_TWR		[expr {0xf <<  8}]		;# Write Recovery Delay
+set		AT91_SDRAMC_TRC		[expr {0xf << 12}]		;# Row Cycle Delay
+set		AT91_SDRAMC_TRP		[expr {0xf << 16}]		;# Row Precharge Delay
+set		AT91_SDRAMC_TRCD	[expr {0xf << 20}]		;# Row to Column Delay
+set		AT91_SDRAMC_TRAS	[expr {0xf << 24}]		;# Active to Precharge Delay
+set		AT91_SDRAMC_TXSR	[expr {0xf << 28}]		;# Exit Self Refresh to Active Delay
 
-set AT91_SDRAMC_LPR		[expr ($AT91_SDRAMC + 0x10)]	;# SDRAM Controller Low Power Register
-set		AT91_SDRAMC_LPCB		[expr (3 << 0)]	;# Low-power Configurations
+set AT91_SDRAMC_LPR		[expr {$AT91_SDRAMC + 0x10}]	;# SDRAM Controller Low Power Register
+set		AT91_SDRAMC_LPCB		[expr {3 << 0}]	;# Low-power Configurations
 set			AT91_SDRAMC_LPCB_DISABLE		0
 set			AT91_SDRAMC_LPCB_SELF_REFRESH		1
 set			AT91_SDRAMC_LPCB_POWER_DOWN		2
 set			AT91_SDRAMC_LPCB_DEEP_POWER_DOWN	3
-set		AT91_SDRAMC_PASR		[expr (7 << 4)]	;# Partial Array Self Refresh
-set		AT91_SDRAMC_TCSR		[expr (3 << 8)]	;# Temperature Compensated Self Refresh
-set		AT91_SDRAMC_DS			[expr (3 << 10)]	;# Drive Strength
-set		AT91_SDRAMC_TIMEOUT		[expr (3 << 12)]	;# Time to define when Low Power Mode is enabled
-set			AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES	[expr (0 << 12)]
-set			AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES	[expr (1 << 12)]
-set			AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES	[expr (2 << 12)]
+set		AT91_SDRAMC_PASR		[expr {7 << 4}]	;# Partial Array Self Refresh
+set		AT91_SDRAMC_TCSR		[expr {3 << 8}]	;# Temperature Compensated Self Refresh
+set		AT91_SDRAMC_DS			[expr {3 << 10}]	;# Drive Strength
+set		AT91_SDRAMC_TIMEOUT		[expr {3 << 12}]	;# Time to define when Low Power Mode is enabled
+set			AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES	[expr {0 << 12}]
+set			AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES	[expr {1 << 12}]
+set			AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES	[expr {2 << 12}]
 
-set AT91_SDRAMC_IER		[expr ($AT91_SDRAMC + 0x14)]	;# SDRAM Controller Interrupt Enable Register
-set AT91_SDRAMC_IDR		[expr ($AT91_SDRAMC + 0x18)]	;# SDRAM Controller Interrupt Disable Register
-set AT91_SDRAMC_IMR		[expr ($AT91_SDRAMC + 0x1C)]	;# SDRAM Controller Interrupt Mask Register
-set AT91_SDRAMC_ISR		[expr ($AT91_SDRAMC + 0x20)]	;# SDRAM Controller Interrupt Status Register
-set		AT91_SDRAMC_RES		[expr (1 << 0)]		;# Refresh Error Status
+set AT91_SDRAMC_IER		[expr {$AT91_SDRAMC + 0x14}]	;# SDRAM Controller Interrupt Enable Register
+set AT91_SDRAMC_IDR		[expr {$AT91_SDRAMC + 0x18}]	;# SDRAM Controller Interrupt Disable Register
+set AT91_SDRAMC_IMR		[expr {$AT91_SDRAMC + 0x1C}]	;# SDRAM Controller Interrupt Mask Register
+set AT91_SDRAMC_ISR		[expr {$AT91_SDRAMC + 0x20}]	;# SDRAM Controller Interrupt Status Register
+set		AT91_SDRAMC_RES		[expr {1 << 0}]		;# Refresh Error Status
 
-set AT91_SDRAMC_MDR		[expr ($AT91_SDRAMC + 0x24)]	;# SDRAM Memory Device Register
-set		AT91_SDRAMC_MD		[expr (3 << 0)]		;# Memory Device Type
+set AT91_SDRAMC_MDR		[expr {$AT91_SDRAMC + 0x24}]	;# SDRAM Memory Device Register
+set		AT91_SDRAMC_MD		[expr {3 << 0}]		;# Memory Device Type
 set			AT91_SDRAMC_MD_SDRAM		0
 set			AT91_SDRAMC_MD_LOW_POWER_SDRAM	1
diff --git a/tcl/chip/atmel/at91/at91sam9_smc.cfg b/tcl/chip/atmel/at91/at91sam9_smc.cfg
index 7dc7638..3a76d14 100644
--- a/tcl/chip/atmel/at91/at91sam9_smc.cfg
+++ b/tcl/chip/atmel/at91/at91sam9_smc.cfg
@@ -1,20 +1,20 @@
-set		AT91_SMC_READMODE	[expr (1 <<  0)]		;# Read Mode
-set		AT91_SMC_WRITEMODE	[expr (1 <<  1)]		;# Write Mode
-set		AT91_SMC_EXNWMODE	[expr (3 <<  4)]		;# NWAIT Mode
-set			AT91_SMC_EXNWMODE_DISABLE	[expr (0 << 4)]
-set			AT91_SMC_EXNWMODE_FROZEN	[expr (2 << 4)]
-set			AT91_SMC_EXNWMODE_READY		[expr (3 << 4)]
-set		AT91_SMC_BAT		[expr (1 <<  8)]		;# Byte Access Type
-set			AT91_SMC_BAT_SELECT		[expr (0 << 8)]
-set			AT91_SMC_BAT_WRITE		[expr (1 << 8)]
-set		AT91_SMC_DBW		[expr (3 << 12)]		;# Data Bus Width */
-set			AT91_SMC_DBW_8			[expr (0 << 12)]
-set			AT91_SMC_DBW_16			[expr (1 << 12)]
-set			AT91_SMC_DBW_32			[expr (2 << 12)]
-set		AT91_SMC_TDFMODE	[expr (1 << 20)]		;# TDF Optimization - Enabled
-set		AT91_SMC_PMEN		[expr (1 << 24)]		;# Page Mode Enabled
-set		AT91_SMC_PS		[expr (3 << 28)]		;# Page Size
-set			AT91_SMC_PS_4			[expr (0 << 28)]
-set			AT91_SMC_PS_8			[expr (1 << 28)]
-set			AT91_SMC_PS_16			[expr (2 << 28)]
-set			AT91_SMC_PS_32			[expr (3 << 28)]
+set		AT91_SMC_READMODE	[expr {1 <<  0}]		;# Read Mode
+set		AT91_SMC_WRITEMODE	[expr {1 <<  1}]		;# Write Mode
+set		AT91_SMC_EXNWMODE	[expr {3 <<  4}]		;# NWAIT Mode
+set			AT91_SMC_EXNWMODE_DISABLE	[expr {0 << 4}]
+set			AT91_SMC_EXNWMODE_FROZEN	[expr {2 << 4}]
+set			AT91_SMC_EXNWMODE_READY		[expr {3 << 4}]
+set		AT91_SMC_BAT		[expr {1 <<  8}]		;# Byte Access Type
+set			AT91_SMC_BAT_SELECT		[expr {0 << 8}]
+set			AT91_SMC_BAT_WRITE		[expr {1 << 8}]
+set		AT91_SMC_DBW		[expr {3 << 12}]		;# Data Bus Width */
+set			AT91_SMC_DBW_8			[expr {0 << 12}]
+set			AT91_SMC_DBW_16			[expr {1 << 12}]
+set			AT91_SMC_DBW_32			[expr {2 << 12}]
+set		AT91_SMC_TDFMODE	[expr {1 << 20}]		;# TDF Optimization - Enabled
+set		AT91_SMC_PMEN		[expr {1 << 24}]		;# Page Mode Enabled
+set		AT91_SMC_PS		[expr {3 << 28}]		;# Page Size
+set			AT91_SMC_PS_4			[expr {0 << 28}]
+set			AT91_SMC_PS_8			[expr {1 << 28}]
+set			AT91_SMC_PS_16			[expr {2 << 28}]
+set			AT91_SMC_PS_32			[expr {3 << 28}]
diff --git a/tcl/chip/atmel/at91/rtt.tcl b/tcl/chip/atmel/at91/rtt.tcl
index 2dd74fa..d49ce71 100644
--- a/tcl/chip/atmel/at91/rtt.tcl
+++ b/tcl/chip/atmel/at91/rtt.tcl
@@ -1,15 +1,15 @@
 
-set RTTC_RTMR [expr $AT91C_BASE_RTTC + 0x00]
-set RTTC_RTAR [expr $AT91C_BASE_RTTC + 0x04]
-set RTTC_RTVR [expr $AT91C_BASE_RTTC + 0x08]
-set RTTC_RTSR [expr $AT91C_BASE_RTTC + 0x0c]
+set RTTC_RTMR [expr {$AT91C_BASE_RTTC + 0x00}]
+set RTTC_RTAR [expr {$AT91C_BASE_RTTC + 0x04}]
+set RTTC_RTVR [expr {$AT91C_BASE_RTTC + 0x08}]
+set RTTC_RTSR [expr {$AT91C_BASE_RTTC + 0x0c}]
 global RTTC_RTMR
 global RTTC_RTAR
 global RTTC_RTVR
 global RTTC_RTSR
 
 proc show_RTTC_RTMR_helper { NAME ADDR VAL } {
-    set rtpres [expr $VAL & 0x0ffff]
+    set rtpres [expr {$VAL & 0x0ffff}]
     global BIT16 BIT17
     if { $rtpres == 0 } {
 	set rtpres 65536;
@@ -17,7 +17,7 @@ proc show_RTTC_RTMR_helper { NAME ADDR VAL } {
     global AT91C_SLOWOSC_FREQ
     # Nasty hack, make this a float by tacking a .0 on the end
     # otherwise, jim makes the value an integer
-    set f [expr $AT91C_SLOWOSC_FREQ.0 / $rtpres.0]
+    set f [expr "$AT91C_SLOWOSC_FREQ.0 / $rtpres.0"]
     echo [format "\tPrescale value: 0x%04x (%5d) => %f Hz" $rtpres $rtpres $f]
     if { $VAL & $BIT16 } {
 	echo "\tBit16 -> Alarm IRQ Enabled"
diff --git a/tcl/chip/atmel/at91/usarts.tcl b/tcl/chip/atmel/at91/usarts.tcl
index ecc4f60..253b7fb 100644
--- a/tcl/chip/atmel/at91/usarts.tcl
+++ b/tcl/chip/atmel/at91/usarts.tcl
@@ -1,20 +1,20 @@
 # the DBGU and USARTs are 'almost' indentical'
-set DBGU_CR         [expr $AT91C_BASE_DBGU + 0x00000000]
-set DBGU_MR         [expr $AT91C_BASE_DBGU + 0x00000004]
-set DBGU_IER        [expr $AT91C_BASE_DBGU + 0x00000008]
-set DBGU_IDR        [expr $AT91C_BASE_DBGU + 0x0000000C]
-set DBGU_IMR        [expr $AT91C_BASE_DBGU + 0x00000010]
-set DBGU_CSR        [expr $AT91C_BASE_DBGU + 0x00000014]
-set DBGU_RHR        [expr $AT91C_BASE_DBGU + 0x00000018]
-set DBGU_THR        [expr $AT91C_BASE_DBGU + 0x0000001C]
-set DBGU_BRGR       [expr $AT91C_BASE_DBGU + 0x00000020]
+set DBGU_CR         [expr {$AT91C_BASE_DBGU + 0x00000000}]
+set DBGU_MR         [expr {$AT91C_BASE_DBGU + 0x00000004}]
+set DBGU_IER        [expr {$AT91C_BASE_DBGU + 0x00000008}]
+set DBGU_IDR        [expr {$AT91C_BASE_DBGU + 0x0000000C}]
+set DBGU_IMR        [expr {$AT91C_BASE_DBGU + 0x00000010}]
+set DBGU_CSR        [expr {$AT91C_BASE_DBGU + 0x00000014}]
+set DBGU_RHR        [expr {$AT91C_BASE_DBGU + 0x00000018}]
+set DBGU_THR        [expr {$AT91C_BASE_DBGU + 0x0000001C}]
+set DBGU_BRGR       [expr {$AT91C_BASE_DBGU + 0x00000020}]
 # no RTOR
 # no TTGR
 # no FIDI
 # no NER
-set DBGU_CIDR       [expr $AT91C_BASE_DBGU + 0x00000040]
-set DBGU_EXID       [expr $AT91C_BASE_DBGU + 0x00000044]
-set DBGU_FNTR       [expr $AT91C_BASE_DBGU + 0x00000048]
+set DBGU_CIDR       [expr {$AT91C_BASE_DBGU + 0x00000040}]
+set DBGU_EXID       [expr {$AT91C_BASE_DBGU + 0x00000044}]
+set DBGU_FNTR       [expr {$AT91C_BASE_DBGU + 0x00000048}]
 
 
 set USx_CR           0x00000000
@@ -54,7 +54,7 @@ proc show_mmr_USx_MR_helper { NAME ADDR VAL } {
 	2 { set s "Force=0" }
 	3 { set s "Force=1" }
 	* {
-	    set $x [expr $x & 6]
+	    set $x [expr {$x & 6}]
 	    switch -exact $x {
 		4 { set s "None" }
 		6 { set s "Multidrop Mode" }
@@ -63,7 +63,7 @@ proc show_mmr_USx_MR_helper { NAME ADDR VAL } {
     }
     echo [format "\tParity: %s " $s]
 
-    set x [expr 5 + [show_normalize_bitfield $VAL 7 6]]
+    set x [expr {5 + [show_normalize_bitfield $VAL 7 6]}]
     echo [format "\tDatabits: %d" $x]
 
     set x [show_normalize_bitfield $VAL 13 12]
@@ -89,7 +89,7 @@ foreach WHO { US0 US1 US2 US3 US4 US5 US6 US7 US8 US9 } {
 	    set vn [set WHO]_[set REG]
 	    # vn = USx_IER
 	    # vv = variable value
-	    set vv [expr $$n + [set USx_[set REG]]]
+	    set vv [expr "$$n + [set USx_[set REG]]"]
 	    # And VV is the address in memory of that register
 
 
diff --git a/tcl/chip/st/spear/quirk_no_srst.tcl b/tcl/chip/st/spear/quirk_no_srst.tcl
index fd02d07..551df06 100644
--- a/tcl/chip/st/spear/quirk_no_srst.tcl
+++ b/tcl/chip/st/spear/quirk_no_srst.tcl
@@ -24,7 +24,7 @@ set sp_reset_mode ""
 proc sp_is_halted {} {
 	global sp_target_name
 
-	return [expr [string compare [$sp_target_name curstate] "halted" ] == 0]
+	return [expr {[string compare [$sp_target_name curstate] "halted" ] == 0}]
 }
 
 # wait for reset button to be pressed, causing CPU to get halted
@@ -38,8 +38,8 @@ proc sp_reset_deassert_post {} {
 
 	poll on
 	echo "====> Press reset button on the board <===="
-	for {set i 0} { [sp_is_halted] == 0 } { set i [expr $i + 1]} {
-		echo -n "$bar([expr $i & 3])\r"
+	for {set i 0} { [sp_is_halted] == 0 } { set i [expr {$i + 1}]} {
+		echo -n "$bar([expr {$i & 3}])\r"
 		sleep 200
 	}
 
diff --git a/tcl/chip/st/spear/spear3xx.tcl b/tcl/chip/st/spear/spear3xx.tcl
index ef38841..86f2a1d 100644
--- a/tcl/chip/st/spear/spear3xx.tcl
+++ b/tcl/chip/st/spear/spear3xx.tcl
@@ -19,7 +19,7 @@ proc sp3xx_clock_default {} {
 	mww 0xfca00014 0x0ffffff8	;# set pll timeout to minimum (100us ?!?)
 
 	# DDRCORE disable to change frequency
-	set val [expr ([mrw 0xfca8002c] & ~0x20000000) | 0x40000000]
+	set val [expr {([mrw 0xfca8002c] & ~0x20000000) | 0x40000000}]
 	mww 0xfca8002c $val
 	mww 0xfca8002c $val ;# Yes, write twice!
 
@@ -29,7 +29,7 @@ proc sp3xx_clock_default {} {
 	mww 0xfca80008 0x00001c0e	;# enable
 	mww 0xfca80008 0x00001c06	;# strobe
 	mww 0xfca80008 0x00001c0e
-	while { [expr [mrw 0xfca80008] & 0x01] == 0x00 } { sleep 1 }
+	while { [expr {[mrw 0xfca80008] & 0x01}] == 0x00 } { sleep 1 }
 
 	# programming PLL2
 	mww 0xfca80018 0xa600010c	;# M=166, P=1, N=12
@@ -37,13 +37,13 @@ proc sp3xx_clock_default {} {
 	mww 0xfca80014 0x00001c0e	;# enable
 	mww 0xfca80014 0x00001c06	;# strobe
 	mww 0xfca80014 0x00001c0e
-	while { [expr [mrw 0xfca80014] & 0x01] == 0x00 } { sleep 1 }
+	while { [expr {[mrw 0xfca80014] & 0x01}] == 0x00 } { sleep 1 }
 
 	mww 0xfca80028 0x00000082	;# enable plltimeen
 	mww 0xfca80024 0x00000511	;# set hclkdiv="/2" & pclkdiv="/2"
 
 	mww 0xfca00000 0x00000004	;# setting SYSCTL to NORMAL mode
-	while { [expr [mrw 0xfca00000] & 0x20] != 0x20 } { sleep 1 }
+	while { [expr {[mrw 0xfca00000] & 0x20}] != 0x20 } { sleep 1 }
 
 	# Select source of DDR clock
 	#mmw 0xfca80020 0x10000000 0x70000000 ;# PLL1
diff --git a/tcl/chip/st/spear/spear3xx_ddr.tcl b/tcl/chip/st/spear/spear3xx_ddr.tcl
index a9787d1..22fe06e 100644
--- a/tcl/chip/st/spear/spear3xx_ddr.tcl
+++ b/tcl/chip/st/spear/spear3xx_ddr.tcl
@@ -28,7 +28,7 @@ proc sp3xx_ddr_init {ddr_type {ddr_chips 1}} {
 	if { $ddr_chips == 2 } {
 		echo [format \
 			"Double chip DDR memory. Total memory size 0x%08x byte" \
-			[expr 2 * $ddr_size]]
+			[expr {2 * $ddr_size}]]
 	} else {
 		echo [format \
 			"Single chip DDR memory. Memory size 0x%08x byte" \
diff --git a/tcl/chip/st/stm32/stm32_rcc.tcl b/tcl/chip/st/stm32/stm32_rcc.tcl
index 07718b6..fa652a2 100644
--- a/tcl/chip/st/stm32/stm32_rcc.tcl
+++ b/tcl/chip/st/stm32/stm32_rcc.tcl
@@ -1,14 +1,14 @@
 
-set RCC_CR            [expr $RCC_BASE + 0x00]
-set RCC_CFGR          [expr $RCC_BASE + 0x04]
-set RCC_CIR           [expr $RCC_BASE + 0x08]
-set RCC_APB2RSTR      [expr $RCC_BASE + 0x0c]
-set RCC_APB1RSTR      [expr $RCC_BASE + 0x10]
-set RCC_AHBENR        [expr $RCC_BASE + 0x14]
-set RCC_APB2ENR       [expr $RCC_BASE + 0x18]
-set RCC_APB1ENR       [expr $RCC_BASE + 0x1c]
-set RCC_BDCR          [expr $RCC_BASE + 0x20]
-set RCC_CSR           [expr $RCC_BASE + 0x24]
+set RCC_CR            [expr {$RCC_BASE + 0x00}]
+set RCC_CFGR          [expr {$RCC_BASE + 0x04}]
+set RCC_CIR           [expr {$RCC_BASE + 0x08}]
+set RCC_APB2RSTR      [expr {$RCC_BASE + 0x0c}]
+set RCC_APB1RSTR      [expr {$RCC_BASE + 0x10}]
+set RCC_AHBENR        [expr {$RCC_BASE + 0x14}]
+set RCC_APB2ENR       [expr {$RCC_BASE + 0x18}]
+set RCC_APB1ENR       [expr {$RCC_BASE + 0x1c}]
+set RCC_BDCR          [expr {$RCC_BASE + 0x20}]
+set RCC_CSR           [expr {$RCC_BASE + 0x24}]
 
 
 proc show_RCC_CR { } {
diff --git a/tcl/chip/st/stm32/stm32_regs.tcl b/tcl/chip/st/stm32/stm32_regs.tcl
index 0c1f625..6ae2f63 100644
--- a/tcl/chip/st/stm32/stm32_regs.tcl
+++ b/tcl/chip/st/stm32/stm32_regs.tcl
@@ -11,78 +11,78 @@ set FSMC_R_BASE           0xA0000000
 
 # /*Peripheral memory map */
 set APB1PERIPH_BASE       [set PERIPH_BASE]
-set APB2PERIPH_BASE       [expr $PERIPH_BASE + 0x10000]
-set AHBPERIPH_BASE        [expr $PERIPH_BASE + 0x20000]
+set APB2PERIPH_BASE       [expr {$PERIPH_BASE + 0x10000}]
+set AHBPERIPH_BASE        [expr {$PERIPH_BASE + 0x20000}]
 
-set TIM2_BASE             [expr $APB1PERIPH_BASE + 0x0000]
-set TIM3_BASE             [expr $APB1PERIPH_BASE + 0x0400]
-set TIM4_BASE             [expr $APB1PERIPH_BASE + 0x0800]
-set TIM5_BASE             [expr $APB1PERIPH_BASE + 0x0C00]
-set TIM6_BASE             [expr $APB1PERIPH_BASE + 0x1000]
-set TIM7_BASE             [expr $APB1PERIPH_BASE + 0x1400]
-set RTC_BASE              [expr $APB1PERIPH_BASE + 0x2800]
-set WWDG_BASE             [expr $APB1PERIPH_BASE + 0x2C00]
-set IWDG_BASE             [expr $APB1PERIPH_BASE + 0x3000]
-set SPI2_BASE             [expr $APB1PERIPH_BASE + 0x3800]
-set SPI3_BASE             [expr $APB1PERIPH_BASE + 0x3C00]
-set USART2_BASE           [expr $APB1PERIPH_BASE + 0x4400]
-set USART3_BASE           [expr $APB1PERIPH_BASE + 0x4800]
-set UART4_BASE            [expr $APB1PERIPH_BASE + 0x4C00]
-set UART5_BASE            [expr $APB1PERIPH_BASE + 0x5000]
-set I2C1_BASE             [expr $APB1PERIPH_BASE + 0x5400]
-set I2C2_BASE             [expr $APB1PERIPH_BASE + 0x5800]
-set CAN_BASE              [expr $APB1PERIPH_BASE + 0x6400]
-set BKP_BASE              [expr $APB1PERIPH_BASE + 0x6C00]
-set PWR_BASE              [expr $APB1PERIPH_BASE + 0x7000]
-set DAC_BASE              [expr $APB1PERIPH_BASE + 0x7400]
+set TIM2_BASE             [expr {$APB1PERIPH_BASE + 0x0000}]
+set TIM3_BASE             [expr {$APB1PERIPH_BASE + 0x0400}]
+set TIM4_BASE             [expr {$APB1PERIPH_BASE + 0x0800}]
+set TIM5_BASE             [expr {$APB1PERIPH_BASE + 0x0C00}]
+set TIM6_BASE             [expr {$APB1PERIPH_BASE + 0x1000}]
+set TIM7_BASE             [expr {$APB1PERIPH_BASE + 0x1400}]
+set RTC_BASE              [expr {$APB1PERIPH_BASE + 0x2800}]
+set WWDG_BASE             [expr {$APB1PERIPH_BASE + 0x2C00}]
+set IWDG_BASE             [expr {$APB1PERIPH_BASE + 0x3000}]
+set SPI2_BASE             [expr {$APB1PERIPH_BASE + 0x3800}]
+set SPI3_BASE             [expr {$APB1PERIPH_BASE + 0x3C00}]
+set USART2_BASE           [expr {$APB1PERIPH_BASE + 0x4400}]
+set USART3_BASE           [expr {$APB1PERIPH_BASE + 0x4800}]
+set UART4_BASE            [expr {$APB1PERIPH_BASE + 0x4C00}]
+set UART5_BASE            [expr {$APB1PERIPH_BASE + 0x5000}]
+set I2C1_BASE             [expr {$APB1PERIPH_BASE + 0x5400}]
+set I2C2_BASE             [expr {$APB1PERIPH_BASE + 0x5800}]
+set CAN_BASE              [expr {$APB1PERIPH_BASE + 0x6400}]
+set BKP_BASE              [expr {$APB1PERIPH_BASE + 0x6C00}]
+set PWR_BASE              [expr {$APB1PERIPH_BASE + 0x7000}]
+set DAC_BASE              [expr {$APB1PERIPH_BASE + 0x7400}]
 
-set AFIO_BASE             [expr $APB2PERIPH_BASE + 0x0000]
-set EXTI_BASE             [expr $APB2PERIPH_BASE + 0x0400]
-set GPIOA_BASE            [expr $APB2PERIPH_BASE + 0x0800]
-set GPIOB_BASE            [expr $APB2PERIPH_BASE + 0x0C00]
-set GPIOC_BASE            [expr $APB2PERIPH_BASE + 0x1000]
-set GPIOD_BASE            [expr $APB2PERIPH_BASE + 0x1400]
-set GPIOE_BASE            [expr $APB2PERIPH_BASE + 0x1800]
-set GPIOF_BASE            [expr $APB2PERIPH_BASE + 0x1C00]
-set GPIOG_BASE            [expr $APB2PERIPH_BASE + 0x2000]
-set ADC1_BASE             [expr $APB2PERIPH_BASE + 0x2400]
-set ADC2_BASE             [expr $APB2PERIPH_BASE + 0x2800]
-set TIM1_BASE             [expr $APB2PERIPH_BASE + 0x2C00]
-set SPI1_BASE             [expr $APB2PERIPH_BASE + 0x3000]
-set TIM8_BASE             [expr $APB2PERIPH_BASE + 0x3400]
-set USART1_BASE           [expr $APB2PERIPH_BASE + 0x3800]
-set ADC3_BASE             [expr $APB2PERIPH_BASE + 0x3C00]
+set AFIO_BASE             [expr {$APB2PERIPH_BASE + 0x0000}]
+set EXTI_BASE             [expr {$APB2PERIPH_BASE + 0x0400}]
+set GPIOA_BASE            [expr {$APB2PERIPH_BASE + 0x0800}]
+set GPIOB_BASE            [expr {$APB2PERIPH_BASE + 0x0C00}]
+set GPIOC_BASE            [expr {$APB2PERIPH_BASE + 0x1000}]
+set GPIOD_BASE            [expr {$APB2PERIPH_BASE + 0x1400}]
+set GPIOE_BASE            [expr {$APB2PERIPH_BASE + 0x1800}]
+set GPIOF_BASE            [expr {$APB2PERIPH_BASE + 0x1C00}]
+set GPIOG_BASE            [expr {$APB2PERIPH_BASE + 0x2000}]
+set ADC1_BASE             [expr {$APB2PERIPH_BASE + 0x2400}]
+set ADC2_BASE             [expr {$APB2PERIPH_BASE + 0x2800}]
+set TIM1_BASE             [expr {$APB2PERIPH_BASE + 0x2C00}]
+set SPI1_BASE             [expr {$APB2PERIPH_BASE + 0x3000}]
+set TIM8_BASE             [expr {$APB2PERIPH_BASE + 0x3400}]
+set USART1_BASE           [expr {$APB2PERIPH_BASE + 0x3800}]
+set ADC3_BASE             [expr {$APB2PERIPH_BASE + 0x3C00}]
 
-set SDIO_BASE             [expr $PERIPH_BASE + 0x18000]
+set SDIO_BASE             [expr {$PERIPH_BASE + 0x18000}]
 
-set DMA1_BASE             [expr $AHBPERIPH_BASE + 0x0000]
-set DMA1_Channel1_BASE    [expr $AHBPERIPH_BASE + 0x0008]
-set DMA1_Channel2_BASE    [expr $AHBPERIPH_BASE + 0x001C]
-set DMA1_Channel3_BASE    [expr $AHBPERIPH_BASE + 0x0030]
-set DMA1_Channel4_BASE    [expr $AHBPERIPH_BASE + 0x0044]
-set DMA1_Channel5_BASE    [expr $AHBPERIPH_BASE + 0x0058]
-set DMA1_Channel6_BASE    [expr $AHBPERIPH_BASE + 0x006C]
-set DMA1_Channel7_BASE    [expr $AHBPERIPH_BASE + 0x0080]
-set DMA2_BASE             [expr $AHBPERIPH_BASE + 0x0400]
-set DMA2_Channel1_BASE    [expr $AHBPERIPH_BASE + 0x0408]
-set DMA2_Channel2_BASE    [expr $AHBPERIPH_BASE + 0x041C]
-set DMA2_Channel3_BASE    [expr $AHBPERIPH_BASE + 0x0430]
-set DMA2_Channel4_BASE    [expr $AHBPERIPH_BASE + 0x0444]
-set DMA2_Channel5_BASE    [expr $AHBPERIPH_BASE + 0x0458]
-set RCC_BASE              [expr $AHBPERIPH_BASE + 0x1000]
-set CRC_BASE              [expr $AHBPERIPH_BASE + 0x3000]
+set DMA1_BASE             [expr {$AHBPERIPH_BASE + 0x0000}]
+set DMA1_Channel1_BASE    [expr {$AHBPERIPH_BASE + 0x0008}]
+set DMA1_Channel2_BASE    [expr {$AHBPERIPH_BASE + 0x001C}]
+set DMA1_Channel3_BASE    [expr {$AHBPERIPH_BASE + 0x0030}]
+set DMA1_Channel4_BASE    [expr {$AHBPERIPH_BASE + 0x0044}]
+set DMA1_Channel5_BASE    [expr {$AHBPERIPH_BASE + 0x0058}]
+set DMA1_Channel6_BASE    [expr {$AHBPERIPH_BASE + 0x006C}]
+set DMA1_Channel7_BASE    [expr {$AHBPERIPH_BASE + 0x0080}]
+set DMA2_BASE             [expr {$AHBPERIPH_BASE + 0x0400}]
+set DMA2_Channel1_BASE    [expr {$AHBPERIPH_BASE + 0x0408}]
+set DMA2_Channel2_BASE    [expr {$AHBPERIPH_BASE + 0x041C}]
+set DMA2_Channel3_BASE    [expr {$AHBPERIPH_BASE + 0x0430}]
+set DMA2_Channel4_BASE    [expr {$AHBPERIPH_BASE + 0x0444}]
+set DMA2_Channel5_BASE    [expr {$AHBPERIPH_BASE + 0x0458}]
+set RCC_BASE              [expr {$AHBPERIPH_BASE + 0x1000}]
+set CRC_BASE              [expr {$AHBPERIPH_BASE + 0x3000}]
 
 # /*Flash registers base address */
-set FLASH_R_BASE          [expr $AHBPERIPH_BASE + 0x2000]
+set FLASH_R_BASE          [expr {$AHBPERIPH_BASE + 0x2000}]
 # /*Flash Option Bytes base address */
 set OB_BASE               0x1FFFF800
 
 # /*FSMC Bankx registers base address */
-set FSMC_Bank1_R_BASE     [expr $FSMC_R_BASE + 0x0000]
-set FSMC_Bank1E_R_BASE    [expr $FSMC_R_BASE + 0x0104]
-set FSMC_Bank2_R_BASE     [expr $FSMC_R_BASE + 0x0060]
-set FSMC_Bank3_R_BASE     [expr $FSMC_R_BASE + 0x0080]
-set FSMC_Bank4_R_BASE     [expr $FSMC_R_BASE + 0x00A0]
+set FSMC_Bank1_R_BASE     [expr {$FSMC_R_BASE + 0x0000}]
+set FSMC_Bank1E_R_BASE    [expr {$FSMC_R_BASE + 0x0104}]
+set FSMC_Bank2_R_BASE     [expr {$FSMC_R_BASE + 0x0060}]
+set FSMC_Bank3_R_BASE     [expr {$FSMC_R_BASE + 0x0080}]
+set FSMC_Bank4_R_BASE     [expr {$FSMC_R_BASE + 0x00A0}]
 
 # /*Debug MCU registers base address */
 set DBGMCU_BASE           0xE0042000
@@ -90,6 +90,6 @@ set DBGMCU_BASE           0xE0042000
 # /*System Control Space memory map */
 set SCS_BASE              0xE000E000
 
-set SysTick_BASE          [expr $SCS_BASE + 0x0010]
-set NVIC_BASE             [expr $SCS_BASE + 0x0100]
-set SCB_BASE              [expr $SCS_BASE + 0x0D00]
+set SysTick_BASE          [expr {$SCS_BASE + 0x0010}]
+set NVIC_BASE             [expr {$SCS_BASE + 0x0100}]
+set SCB_BASE              [expr {$SCS_BASE + 0x0D00}]