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| author | Jacek Wuwer <jacekmw8@gmail.com> | 2021-04-06 20:08:11 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2022-02-14 15:12:10 +0000 |
| commit | f998a2aaf19c14b46fd7f7dd50607a0904f40bd3 (patch) | |
| tree | e9f04aeb797d8e831de62a8fa5805eec9ebc24bb /tcl/board/vd_pulpissimo_jtag.cfg | |
| parent | 2a2636f138dc40be3fff06cb7bf1f126d906e0a1 (diff) | |
| download | riscv-openocd-f998a2aaf19c14b46fd7f7dd50607a0904f40bd3.zip riscv-openocd-f998a2aaf19c14b46fd7f7dd50607a0904f40bd3.tar.gz riscv-openocd-f998a2aaf19c14b46fd7f7dd50607a0904f40bd3.tar.bz2 | |
Cadence virtual debug interface (vdebug) integration
Change-Id: I1bc105b3addc3f34161c2356c482ff3011e3f2cc
Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6097
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'tcl/board/vd_pulpissimo_jtag.cfg')
| -rw-r--r-- | tcl/board/vd_pulpissimo_jtag.cfg | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/tcl/board/vd_pulpissimo_jtag.cfg b/tcl/board/vd_pulpissimo_jtag.cfg new file mode 100644 index 0000000..69dd9e6 --- /dev/null +++ b/tcl/board/vd_pulpissimo_jtag.cfg @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Cadence virtual debug interface +# RISCV Ibex core with Pulpissimo through JTAG + +source [find interface/vdebug.cfg] + +set _CHIPNAME ibex +set _HARTID 0x20 +set _CPUTAPID 0x249511c3 + +# vdebug select transport +#transport select jtag + +# JTAG reset config, frequency and reset delay +reset_config trst_and_srst +adapter speed 12500 +adapter srst delay 10 + +# BFM hierarchical path and input clk period +vdebug bfm_path tbench.u_vd_jtag_bfm 40ns + +# DMA Memories to access backdoor (up to 4) +vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2_pri\[0\].sram_i.mem_array 0x1c000000 0x8000 +vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2_pri\[1\].sram_i.mem_array 0x1c008000 0x8000 +vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2\[0\].sram_i.mem_array 0x1c010000 0x80000 + +# need to explicitly define riscv tap, autoprobing does not work for icapture != 0x01 +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x05 -irmask 0x1f -expected-id $_CPUTAPID + +jtag arp_init-reset + +source [find target/vd_riscv.cfg] |