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| author | Antonio Borneo <borneo.antonio@gmail.com> | 2021-04-10 18:28:52 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2021-05-08 09:49:08 +0100 |
| commit | 64d89d5ee1a554fbae8eb0a7231ccb2dc4428c1a (patch) | |
| tree | 27b37e970a5b140d3e15968773629edeefdee33d /tcl/board/at91sam9g20-ek.cfg | |
| parent | f855fdcf0d95ff9ba18a83f9a97d5368844d4f2c (diff) | |
| download | riscv-openocd-64d89d5ee1a554fbae8eb0a7231ccb2dc4428c1a.zip riscv-openocd-64d89d5ee1a554fbae8eb0a7231ccb2dc4428c1a.tar.gz riscv-openocd-64d89d5ee1a554fbae8eb0a7231ccb2dc4428c1a.tar.bz2 | |
tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change
Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.
Fix manually the remaining lines that don't match simple patterns
and would require dedicated boring scripting.
Remove the 'expr' command where appropriate.
Change-Id: Ia75210c8447f88d38515addab4a836af9103096d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6161
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'tcl/board/at91sam9g20-ek.cfg')
| -rw-r--r-- | tcl/board/at91sam9g20-ek.cfg | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg index 03296c5..59ee4d2 100644 --- a/tcl/board/at91sam9g20-ek.cfg +++ b/tcl/board/at91sam9g20-ek.cfg @@ -77,25 +77,25 @@ proc at91sam9g20_reset_init { } { # Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR. mww 0xfffffc20 0x00004001 - while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 } # Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43). # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable. mww 0xfffffc28 0x202a3f01 - while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 } # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR. # Wait for MCKRDY signal from PMC_SR to assert. mww 0xfffffc30 0x00000101 - while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 } # Now change PMC_MCKR register to select PLLA. # Wait for MCKRDY signal from PMC_SR to assert. mww 0xfffffc30 0x00001302 - while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 } + while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 } # Processor and master clocks are now operating and stable at maximum frequency possible: # -> MCLK = 132.096 MHz |