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| author | Evgeniy Naydanov <109669442+en-sc@users.noreply.github.com> | 2024-04-26 20:49:11 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-04-26 20:49:11 +0300 |
| commit | de03da8c2cd6f5bf5dcaff62387e9d3171c0f778 (patch) | |
| tree | 534df3a26c3373fe3bded404c85aacb8b639df50 /src | |
| parent | 5aac841f4a802f78da52d33969039fafea0c0d51 (diff) | |
| parent | 967510cb1ddebd379ae01b941038285077c5113f (diff) | |
| download | riscv-openocd-de03da8c2cd6f5bf5dcaff62387e9d3171c0f778.zip riscv-openocd-de03da8c2cd6f5bf5dcaff62387e9d3171c0f778.tar.gz riscv-openocd-de03da8c2cd6f5bf5dcaff62387e9d3171c0f778.tar.bz2 | |
Merge pull request #1046 from en-sc/en-sc/reg-rv011-segfault-propper
target/riscv/riscv-011.c: fix access to non-existent register
Diffstat (limited to 'src')
| -rw-r--r-- | src/target/riscv/riscv-011.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c index 1060294..64379dc 100644 --- a/src/target/riscv/riscv-011.c +++ b/src/target/riscv/riscv-011.c @@ -1771,10 +1771,10 @@ static riscv_error_t handle_halt_routine(struct target *target) reg = S0; break; case 31: - reg = CSR_DPC; + reg = GDB_REGNO_DPC; break; case 32: - reg = CSR_DCSR; + reg = GDB_REGNO_DCSR; break; default: assert(0); @@ -1808,8 +1808,8 @@ static riscv_error_t handle_halt_routine(struct target *target) } /* TODO: get rid of those 2 variables and talk to the cache directly. */ - info->dpc = reg_cache_get(target, CSR_DPC); - info->dcsr = reg_cache_get(target, CSR_DCSR); + info->dpc = reg_cache_get(target, GDB_REGNO_DPC); + info->dcsr = reg_cache_get(target, GDB_REGNO_DCSR); cache_invalidate(target); |