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authorArtemiy Volkov <artemiy@synopsys.com>2023-07-06 13:25:00 +0200
committerAntonio Borneo <borneo.antonio@gmail.com>2023-10-07 14:42:13 +0000
commitd20304b3fb0f27f62844144837ee5b99ee040bcd (patch)
tree4d8d11883c2ee40333712296edc7672f7eeb13fe /src
parentbdf73617e774b0791f9efec6659c78c1f60c03b5 (diff)
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target/arc: do not invalidate icache when (un)setting breakpoints
Currently, instruction cache is being invalidated in arc_{un,}set_breakpoint() regardless of whether the breakpoint's type is HW or SW. For SW breakpoints, this has no net effect as the caches are flushed as a by-product of overwriting instructions in main memory and is thus merely unnecessary; but for HW breakpoints this invalidation is not preceded by a flush and might lead to loss of data. This patch removes the invalidate() call altogether to correct this undesired behavior for HW breakpoints. With this patch applied, all supported HW breakpoint tests from the gdb testsuite are now passing with the arc-openocd backend. Change-Id: I3d252b97f01f1a1e2bf0eb8fb257bdab0c544bc2 Signed-off-by: Artemiy Volkov <artemiy@synopsys.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7767 Tested-by: jenkins Reviewed-by: Evgeniy Didin <didin@synopsys.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/target/arc.c6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/target/arc.c b/src/target/arc.c
index 2ca6be1..45005b2 100644
--- a/src/target/arc.c
+++ b/src/target/arc.c
@@ -1573,9 +1573,6 @@ static int arc_set_breakpoint(struct target *target,
return ERROR_FAIL;
}
- /* core instruction cache is now invalid. */
- CHECK_RETVAL(arc_cache_invalidate(target));
-
return ERROR_OK;
}
@@ -1658,9 +1655,6 @@ static int arc_unset_breakpoint(struct target *target,
return ERROR_FAIL;
}
- /* core instruction cache is now invalid. */
- CHECK_RETVAL(arc_cache_invalidate(target));
-
return retval;
}