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| author | Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> | 2024-04-23 16:20:05 +0300 |
|---|---|---|
| committer | Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> | 2024-04-23 16:42:55 +0300 |
| commit | 98ece6bac993c39d0a9fdcd9e0a81d007b960775 (patch) | |
| tree | c063ca28e39a420ad2c1ff779519975221616935 /src | |
| parent | 3991492cc101f4289be06ec7dc23c6ad7748a74a (diff) | |
| download | riscv-openocd-98ece6bac993c39d0a9fdcd9e0a81d007b960775.zip riscv-openocd-98ece6bac993c39d0a9fdcd9e0a81d007b960775.tar.gz riscv-openocd-98ece6bac993c39d0a9fdcd9e0a81d007b960775.tar.bz2 | |
target/riscv/riscv-011: pc and dpc should be cached at the same location
Prior to the commit, pc was cached at `info->dpc`, but dpc at register
cache.
Change-Id: I369788441dbe21bcf8fc360d2e97e98096b25e3a
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/target/riscv/riscv-011.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c index 88ae14d..1060294 100644 --- a/src/target/riscv/riscv-011.c +++ b/src/target/riscv/riscv-011.c @@ -1280,7 +1280,7 @@ static int register_write(struct target *target, unsigned int number, } else if (number <= GDB_REGNO_XPR31) { cache_set_load(target, 0, number - GDB_REGNO_ZERO, SLOT0); cache_set_jump(target, 1); - } else if (number == GDB_REGNO_PC) { + } else if (number == GDB_REGNO_PC || number == GDB_REGNO_DPC) { info->dpc = value; return ERROR_OK; } else if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) { @@ -1338,7 +1338,7 @@ static int get_register(struct target *target, riscv_reg_t *value, if (regid <= GDB_REGNO_XPR31) { *value = reg_cache_get(target, regid); - } else if (regid == GDB_REGNO_PC) { + } else if (regid == GDB_REGNO_PC || regid == GDB_REGNO_DPC) { *value = info->dpc; } else if (regid >= GDB_REGNO_FPR0 && regid <= GDB_REGNO_FPR31) { int result = update_mstatus_actual(target); |