portability fix: Switch binary literals to hex

Allows build with legacy toolchains which do not support
C23 nor GCC extension for binary literals.

Change-Id: I742d3a8a86bf16f81421d11c59d3cb155ee17aed
Signed-off-by: Sevan Janiyan <venture37@geeklan.co.uk>
Reviewed-on: https://review.openocd.org/c/openocd/+/8123
Tested-by: jenkins
Reviewed-by: Jörg Wunsch <openocd@uriah.heep.sax.de>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

3 files changed, 71 insertions, 71 deletions

diff --git a/src/flash/nor/xcf.c b/src/flash/nor/xcf.c
index c253b22..1d67b09 100644
--- a/src/flash/nor/xcf.c
+++ b/src/flash/nor/xcf.c
@@ -130,8 +130,8 @@ static struct xcf_status read_status(struct flash_bank *bank)
 	jtag_add_ir_scan(bank->target->tap, &scan, TAP_IDLE);
 	jtag_execute_queue();
 
-	ret.isc_error   = ((irdata[0] >> 7) & 3) == 0b01;
-	ret.prog_error  = ((irdata[0] >> 5) & 3) == 0b01;
+	ret.isc_error   = ((irdata[0] >> 7) & 3) == 1;
+	ret.prog_error  = ((irdata[0] >> 5) & 3) == 1;
 	ret.prog_busy   = ((irdata[0] >> 4) & 1) == 0;
 	ret.isc_mode    = ((irdata[0] >> 3) & 1) == 1;
 
@@ -528,7 +528,7 @@ static int isc_program_single_revision_btc(struct flash_bank *bank)
 {
 	uint8_t buf[4];
 	uint32_t btc = 0xFFFFFFFF;
-	btc &= ~0b1111;
+	btc &= ~0xF;
 	btc |= ((bank->num_sectors - 1) << 2);
 	btc &= ~(1 << 4);
 	h_u32_to_le(buf, btc);
diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c
index 552bcfa..8bb24f2 100644
--- a/src/target/armv8_dpm.c
+++ b/src/target/armv8_dpm.c
@@ -46,7 +46,7 @@ enum arm_state armv8_dpm_get_core_state(struct arm_dpm *dpm)
 	dpm->last_el = el;
 
 	/* In Debug state, each bit gives the current Execution state of each EL */
-	if ((rw >> el) & 0b1)
+	if ((rw >> el) & 1)
 		return ARM_STATE_AARCH64;
 
 	return ARM_STATE_ARM;
diff --git a/src/target/armv8_opcodes.h b/src/target/armv8_opcodes.h
index ddb0f9b..9200dac 100644
--- a/src/target/armv8_opcodes.h
+++ b/src/target/armv8_opcodes.h
@@ -26,80 +26,80 @@
 #define SYSTEM_AAR64_MODE_EL3T	0xC
 #define SYSTEM_AAR64_MODE_EL3H	0xd
 
-#define SYSTEM_DAIF			0b1101101000010001
+#define SYSTEM_DAIF			0xDA11
 #define SYSTEM_DAIF_MASK		0x3C0
 #define SYSTEM_DAIF_SHIFT		6
 
-#define SYSTEM_ELR_EL1			0b1100001000000001
-#define SYSTEM_ELR_EL2			0b1110001000000001
-#define SYSTEM_ELR_EL3			0b1111001000000001
-
-#define SYSTEM_SCTLR_EL1	0b1100000010000000
-#define SYSTEM_SCTLR_EL2	0b1110000010000000
-#define SYSTEM_SCTLR_EL3	0b1111000010000000
-
-#define SYSTEM_FPCR			0b1101101000100000
-#define SYSTEM_FPSR			0b1101101000100001
-#define SYSTEM_DAIF			0b1101101000010001
-#define SYSTEM_NZCV			0b1101101000010000
-#define SYSTEM_SP_EL0			0b1100001000001000
-#define SYSTEM_SP_EL1			0b1110001000001000
-#define SYSTEM_SP_EL2			0b1111001000001000
-#define SYSTEM_SP_SEL			0b1100001000010000
-#define SYSTEM_SPSR_ABT			0b1110001000011001
-#define SYSTEM_SPSR_FIQ			0b1110001000011011
-#define SYSTEM_SPSR_IRQ			0b1110001000011000
-#define SYSTEM_SPSR_UND			0b1110001000011010
-
-#define SYSTEM_SPSR_EL1			0b1100001000000000
-#define SYSTEM_SPSR_EL2			0b1110001000000000
-#define SYSTEM_SPSR_EL3			0b1111001000000000
-
-#define SYSTEM_ISR_EL1			0b1100011000001000
-
-#define SYSTEM_DBG_DSPSR_EL0    0b1101101000101000
-#define SYSTEM_DBG_DLR_EL0		0b1101101000101001
-#define SYSTEM_DBG_DTRRX_EL0	0b1001100000101000
-#define SYSTEM_DBG_DTRTX_EL0	0b1001100000101000
-#define SYSTEM_DBG_DBGDTR_EL0	0b1001100000100000
-
-#define SYSTEM_CCSIDR			0b1100100000000000
-#define SYSTEM_CLIDR			0b1100100000000001
-#define SYSTEM_CSSELR			0b1101000000000000
-#define SYSTEM_CTYPE			0b1101100000000001
-#define SYSTEM_CTR				0b1101100000000001
-
-#define SYSTEM_DCCISW			0b0100001111110010
-#define SYSTEM_DCCSW			0b0100001111010010
-#define SYSTEM_ICIVAU			0b0101101110101001
-#define SYSTEM_DCCVAU			0b0101101111011001
-#define SYSTEM_DCCIVAC			0b0101101111110001
-
-#define SYSTEM_MPIDR			0b1100000000000101
-
-#define SYSTEM_TCR_EL1			0b1100000100000010
-#define SYSTEM_TCR_EL2			0b1110000100000010
-#define SYSTEM_TCR_EL3			0b1111000100000010
-
-#define SYSTEM_TTBR0_EL1		0b1100000100000000
-#define SYSTEM_TTBR0_EL2		0b1110000100000000
-#define SYSTEM_TTBR0_EL3		0b1111000100000000
-#define SYSTEM_TTBR1_EL1		0b1100000100000001
+#define SYSTEM_ELR_EL1			0xC201
+#define SYSTEM_ELR_EL2			0xE201
+#define SYSTEM_ELR_EL3			0xF201
+
+#define SYSTEM_SCTLR_EL1	0xC080
+#define SYSTEM_SCTLR_EL2	0xE080
+#define SYSTEM_SCTLR_EL3	0xF080
+
+#define SYSTEM_FPCR		0xDA20
+#define SYSTEM_FPSR		0xDA21
+#define SYSTEM_DAIF		0xDA11
+#define SYSTEM_NZCV		0xDA10
+#define SYSTEM_SP_EL0		0xC208
+#define SYSTEM_SP_EL1		0xE208
+#define SYSTEM_SP_EL2		0xF208
+#define SYSTEM_SP_SEL		0xC210
+#define SYSTEM_SPSR_ABT		0xE219
+#define SYSTEM_SPSR_FIQ		0xE21B
+#define SYSTEM_SPSR_IRQ		0xE218
+#define SYSTEM_SPSR_UND		0xE21A
+
+#define SYSTEM_SPSR_EL1			0xC200
+#define SYSTEM_SPSR_EL2			0xE200
+#define SYSTEM_SPSR_EL3			0xF200
+
+#define SYSTEM_ISR_EL1			0xC608
+
+#define SYSTEM_DBG_DSPSR_EL0    0xDA28
+#define SYSTEM_DBG_DLR_EL0		0xDA29
+#define SYSTEM_DBG_DTRRX_EL0	0x9828
+#define SYSTEM_DBG_DTRTX_EL0	0x9828
+#define SYSTEM_DBG_DBGDTR_EL0	0x9820
+
+#define SYSTEM_CCSIDR			0xC800
+#define SYSTEM_CLIDR			0xC801
+#define SYSTEM_CSSELR			0xD000
+#define SYSTEM_CTYPE			0xD801
+#define SYSTEM_CTR			0xD801
+
+#define SYSTEM_DCCISW			0x43F2
+#define SYSTEM_DCCSW			0x43D2
+#define SYSTEM_ICIVAU			0x5BA9
+#define SYSTEM_DCCVAU			0x5BD9
+#define SYSTEM_DCCIVAC			0x5BF1
+
+#define SYSTEM_MPIDR			0xC005
+
+#define SYSTEM_TCR_EL1			0xC102
+#define SYSTEM_TCR_EL2			0xE102
+#define SYSTEM_TCR_EL3			0xF102
+
+#define SYSTEM_TTBR0_EL1		0xC100
+#define SYSTEM_TTBR0_EL2		0xE100
+#define SYSTEM_TTBR0_EL3		0xF100
+#define SYSTEM_TTBR1_EL1		0xC101
 
 /* ARMv8 address translation */
-#define SYSTEM_PAR_EL1			0b1100001110100000
-#define SYSTEM_ATS12E0R			0b0110001111000110
-#define SYSTEM_ATS12E1R			0b0110001111000100
-#define SYSTEM_ATS1E2R			0b0110001111000000
-#define SYSTEM_ATS1E3R			0b0111001111000000
+#define SYSTEM_PAR_EL1			0xC3A0
+#define SYSTEM_ATS12E0R			0x63C6
+#define SYSTEM_ATS12E1R			0x63C4
+#define SYSTEM_ATS1E2R			0x63C0
+#define SYSTEM_ATS1E3R			0x73C0
 
 /* fault status and fault address */
-#define SYSTEM_FAR_EL1			0b1100001100000000
-#define SYSTEM_FAR_EL2			0b1110001100000000
-#define SYSTEM_FAR_EL3			0b1111001100000000
-#define SYSTEM_ESR_EL1			0b1100001010010000
-#define SYSTEM_ESR_EL2			0b1110001010010000
-#define SYSTEM_ESR_EL3			0b1111001010010000
+#define SYSTEM_FAR_EL1			0xC300
+#define SYSTEM_FAR_EL2			0xE300
+#define SYSTEM_FAR_EL3			0xF300
+#define SYSTEM_ESR_EL1			0xC290
+#define SYSTEM_ESR_EL2			0xE290
+#define SYSTEM_ESR_EL3			0xF290
 
 #define ARMV8_MRS_DSPSR(rt)	(0xd53b4500 | (rt))
 #define ARMV8_MSR_DSPSR(rt)	(0xd51b4500 | (rt))