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author | Kevin Burke <kevinb@os.amperecomputing.com> | 2021-08-14 18:55:28 +0200 |
---|---|---|
committer | Antonio Borneo <borneo.antonio@gmail.com> | 2022-06-24 21:37:00 +0000 |
commit | 62058c0a32e0e98db39087f8c1e29085e611f2b8 (patch) | |
tree | eebacde1e8e258537d106167c613922ecd45c94c /src | |
parent | 8f8fb0fa79742c5e6357e9a2a1609d0500d91293 (diff) | |
download | riscv-openocd-62058c0a32e0e98db39087f8c1e29085e611f2b8.zip riscv-openocd-62058c0a32e0e98db39087f8c1e29085e611f2b8.tar.gz riscv-openocd-62058c0a32e0e98db39087f8c1e29085e611f2b8.tar.bz2 |
adi_v5_jtag: extend memaccess_tck to every AP access
ADIv5 reports:
Accessing AP registers or debug resources in connected
device through an AP can be subjected to other variable
response delays in the system. A debugger that can adapt
to these delays and avoid wasting WAIT scans operates more
efficiently and provides higher maximum data throughput.
The existing code in OpenOCD uses extra tck only for accessing
resources through an AP.
Extend the use of extra tck also for accessing an AP register.
Split from change https://review.openocd.org/6077/
Change-Id: I2082362e098d09f4ba0668e01f5196afc965c8f3
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6460
Tested-by: jenkins
Diffstat (limited to 'src')
-rw-r--r-- | src/target/adi_v5_jtag.c | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c index 810a5ab..67ad0b1 100644 --- a/src/target/adi_v5_jtag.c +++ b/src/target/adi_v5_jtag.c @@ -284,17 +284,14 @@ static int adi_jtag_dp_scan_cmd(struct adiv5_dap *dap, struct dap_cmd *cmd, uint jtag_add_dr_scan(tap, 2, cmd->fields, TAP_IDLE); - /* Add specified number of tck clocks after starting memory bus - * access, giving the hardware time to complete the access. + /* Add specified number of tck clocks after starting AP register + * access or memory bus access, giving the hardware time to complete + * the access. * They provide more time for the (MEM) AP to complete the read ... * See "Minimum Response Time" for JTAG-DP, in the ADIv5/ADIv6 spec. */ - if (cmd->instr == JTAG_DP_APACC) { - if ((cmd->reg_addr == MEM_AP_REG_DRW(dap) || - (cmd->reg_addr & 0xFF0) == MEM_AP_REG_BD0(dap)) && - cmd->memaccess_tck != 0) - jtag_add_runtest(cmd->memaccess_tck, TAP_IDLE); - } + if (cmd->instr == JTAG_DP_APACC && cmd->memaccess_tck != 0) + jtag_add_runtest(cmd->memaccess_tck, TAP_IDLE); return ERROR_OK; } |