diff options
| author | Mark Zhuang <mark.zhuang@spacemit.com> | 2025-05-15 14:58:07 +0800 |
|---|---|---|
| committer | Mark Zhuang <mark.zhuang@spacemit.com> | 2025-06-12 22:25:24 +0800 |
| commit | 5a39519f39501552e98fa2fe4cbfea2276d55e9f (patch) | |
| tree | 57a4a0a936b455c60544b96e68cd7d9e41fc7b22 /src | |
| parent | fc0b7e368b119136fba1e6a94b06d53eee352573 (diff) | |
| download | riscv-openocd-5a39519f39501552e98fa2fe4cbfea2276d55e9f.zip riscv-openocd-5a39519f39501552e98fa2fe4cbfea2276d55e9f.tar.gz riscv-openocd-5a39519f39501552e98fa2fe4cbfea2276d55e9f.tar.bz2 | |
target/riscv: check nextdm address in abits range
When abits not correctly configured, we hope to detect it
as soon as possible.
Diffstat (limited to 'src')
| -rw-r--r-- | src/target/riscv/riscv-013.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 46c61ca..b5c6bfb 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -538,6 +538,7 @@ static bool check_dbgbase_exists(struct target *target) { uint32_t next_dm = 0; unsigned int count = 1; + riscv013_info_t *info = get_info(target); LOG_TARGET_DEBUG(target, "Searching for DM with DMI base address (dbgbase) = 0x%x", target->dbgbase); while (1) { @@ -552,6 +553,12 @@ static bool check_dbgbase_exists(struct target *target) LOG_TARGET_ERROR(target, "Reached the end of DM chain (detected %u DMs in total).", count); break; } + if (next_dm >> info->abits) { + LOG_TARGET_ERROR(target, "The address of the next Debug Module does not fit into %u bits, " + "which is the width of the DMI bus address. This is a HW bug", + info->abits); + break; + } /* Safety: Avoid looping forever in case of buggy nextdm values in the hardware. */ if (count++ > RISCV_MAX_DMS) { LOG_TARGET_ERROR(target, "Supporting no more than %d DMs on a DMI bus. Aborting", RISCV_MAX_DMS); |