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| author | Phil Kirkpatrick <p.kirkpatrick@reflexaerospace.com> | 2023-05-09 11:04:24 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2023-05-18 10:23:18 +0000 |
| commit | 30b0e9af8d1e68ee051ac62dd0e27c920fb396bd (patch) | |
| tree | b1fdb30c3f41bcc768fbf97acce7095d4f70b26d /src | |
| parent | d4225192df17687f82fa35e5aaec6bed533a8f1f (diff) | |
| download | riscv-openocd-30b0e9af8d1e68ee051ac62dd0e27c920fb396bd.zip riscv-openocd-30b0e9af8d1e68ee051ac62dd0e27c920fb396bd.tar.gz riscv-openocd-30b0e9af8d1e68ee051ac62dd0e27c920fb396bd.tar.bz2 | |
tcl/target: Add support for TMS570LC43xx
Added support for TMS570LC43xx series parts. This uses the pre-existing
ti_tms570.cfg parent config. In ti_tms570.cfg, dbgbase was changed.
Note 1: Based on the following TI E2E post, the previous dbgbase was wrong
and the new value isn't due to a difference in parts.
Link: https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1106954/tms570ls3137-debugging-with-openocd
Note 2: Both the previous dbgbase and the one suggested in the TI E2E post
have the 2 LSB set. In the current version of OpenOCD, this will cause
cortex_a_read_cpu_memory_fast and cortex_a_write_cpu_memory_fast to fail
due to an alignment checks in
mem_ap_<read/write>_buf_noincr()->mem_ap_<read/write>().
In all other uses of dbgbase for arm cortex parts, the 2 LSB are masked
and ignored.
Change-Id: Ic936722e5a4cfc7161b0df1fe3325ee12fd901c6
Signed-off-by: Phil Kirkpatrick <p.kirkpatrick@reflexaerospace.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7682
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'src')
0 files changed, 0 insertions, 0 deletions