nds32: support multi-target debugging

Change-Id: If767f646b234dbcdb01946e5d13a3a6a29df2d78
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1581
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>

12 files changed, 822 insertions, 745 deletions

diff --git a/src/jtag/aice/aice_interface.c b/src/jtag/aice/aice_interface.c
index bad3c3d..aede83a 100644
--- a/src/jtag/aice/aice_interface.c
+++ b/src/jtag/aice/aice_interface.c
@@ -50,24 +50,28 @@ static int aice_khz_to_speed_map[AICE_KHZ_TO_SPEED_MAP_SIZE] = {
 	375,
 };
 
-static struct aice_port_s aice;
+static const struct aice_port *aice_port;
+static struct aice_port_param_s param;
+static uint32_t retry_times;
+static uint32_t count_to_check_dbger;
 
 /***************************************************************************/
 /* External interface implementation */
-#define AICE_MAX_TARGET_ID_CODES	0x10
-static uint32_t aice_target_id_codes[AICE_MAX_TARGET_ID_CODES];
+static uint32_t aice_target_id_codes[AICE_MAX_NUM_CORE];
 static uint8_t aice_num_of_target_id_codes;
 
 /***************************************************************************/
 /* AICE operations */
-int aice_init_target(struct target *t)
+int aice_init_targets(void)
 {
 	int res;
+	struct target *target;
+	struct aice_port_s *aice;
 
-	LOG_DEBUG("aice_init_target");
+	LOG_DEBUG("aice_init_targets");
 
 	if (aice_num_of_target_id_codes == 0) {
-		res = aice.port->api->idcode(aice_target_id_codes, &aice_num_of_target_id_codes);
+		res = aice_port->api->idcode(aice_target_id_codes, &aice_num_of_target_id_codes);
 		if (res != ERROR_OK) {
 			LOG_ERROR("<-- TARGET ERROR! Failed to identify AndesCore "
 					"JTAG Manufacture ID in the JTAG scan chain. "
@@ -76,30 +80,36 @@ int aice_init_target(struct target *t)
 		}
 	}
 
-	t->tap->idcode = aice_target_id_codes[t->tap->abs_chain_position];
+	for (target = all_targets; target; target = target->next) {
+		target->tap->idcode = aice_target_id_codes[target->tap->abs_chain_position];
 
-	unsigned ii, limit = t->tap->expected_ids_cnt;
-	int found = 0;
+		unsigned ii, limit = target->tap->expected_ids_cnt;
+		int found = 0;
 
-	for (ii = 0; ii < limit; ii++) {
-		uint32_t expected = t->tap->expected_ids[ii];
+		for (ii = 0; ii < limit; ii++) {
+			uint32_t expected = target->tap->expected_ids[ii];
 
-		/* treat "-expected-id 0" as a "don't-warn" wildcard */
-		if (!expected || (t->tap->idcode == expected)) {
-			found = 1;
-			break;
+			/* treat "-expected-id 0" as a "don't-warn" wildcard */
+			if (!expected || (target->tap->idcode == expected)) {
+				found = 1;
+				break;
+			}
 		}
-	}
 
-	if (found == 0) {
-		LOG_ERROR
-			("aice_init_target: target not found: idcode: %x ",
-			 t->tap->idcode);
-		return ERROR_FAIL;
-	}
+		if (found == 0) {
+			LOG_ERROR
+				("aice_init_targets: target not found: idcode: %x ",
+				 target->tap->idcode);
+			return ERROR_FAIL;
+		}
+
+		aice = calloc(1, sizeof(struct aice_port_s));
+		aice->port = aice_port;
+		aice->coreid = target->tap->abs_chain_position;
 
-	t->tap->priv = &aice;
-	t->tap->hasidcode = 1;
+		target->tap->priv = aice;
+		target->tap->hasidcode = 1;
+	}
 
 	return ERROR_OK;
 }
@@ -114,14 +124,14 @@ int aice_init_target(struct target *t)
  */
 static int aice_init(void)
 {
-	if (ERROR_OK != aice.port->api->open(&(aice.param))) {
+	if (ERROR_OK != aice_port->api->open(&param)) {
 		LOG_ERROR("Cannot find AICE Interface! Please check "
 				"connection and permissions.");
 		return ERROR_JTAG_INIT_FAILED;
 	}
 
-	aice.port->api->set_retry_times(aice.retry_times);
-	aice.port->api->set_count_to_check_dbger(aice.count_to_check_dbger);
+	aice_port->api->set_retry_times(retry_times);
+	aice_port->api->set_count_to_check_dbger(count_to_check_dbger);
 
 	LOG_INFO("AICE JTAG Interface ready");
 
@@ -133,7 +143,7 @@ static int aice_init(void)
  */
 static int aice_quit(void)
 {
-	aice.port->api->close();
+	aice_port->api->close();
 	return ERROR_OK;
 }
 
@@ -146,7 +156,7 @@ static int aice_execute_reset(struct jtag_command *cmd)
 
 	if (cmd->cmd.reset->trst != last_trst) {
 		if (cmd->cmd.reset->trst)
-			retval = aice.port->api->reset();
+			retval = aice_port->api->reset();
 
 		last_trst = cmd->cmd.reset->trst;
 	}
@@ -191,7 +201,7 @@ static int aice_execute_queue(void)
 /* set jtag frequency(base frequency/frequency divider) to your jtag adapter */
 static int aice_speed(int speed)
 {
-	return aice.port->api->set_jtag_clock(speed);
+	return aice_port->api->set_jtag_clock(speed);
 }
 
 /* convert jtag adapter frequency(base frequency/frequency divider) to
@@ -237,10 +247,10 @@ COMMAND_HANDLER(aice_handle_aice_info_command)
 {
 	LOG_DEBUG("aice_handle_aice_info_command");
 
-	command_print(CMD_CTX, "Description: %s", aice.param.device_desc);
-	command_print(CMD_CTX, "Serial number: %s", aice.param.serial);
-	if (strncmp(aice.port->name, "aice_pipe", 9) == 0)
-		command_print(CMD_CTX, "Adapter: %s", aice.param.adapter_name);
+	command_print(CMD_CTX, "Description: %s", param.device_desc);
+	command_print(CMD_CTX, "Serial number: %s", param.serial);
+	if (strncmp(aice_port->name, "aice_pipe", 9) == 0)
+		command_print(CMD_CTX, "Adapter: %s", param.adapter_name);
 
 	return ERROR_OK;
 }
@@ -256,7 +266,7 @@ COMMAND_HANDLER(aice_handle_aice_port_command)
 
 	for (const struct aice_port *l = aice_port_get_list(); l->name; l++) {
 		if (strcmp(l->name, CMD_ARGV[0]) == 0) {
-			aice.port = l;
+			aice_port = l;
 			return ERROR_OK;
 		}
 	}
@@ -270,7 +280,7 @@ COMMAND_HANDLER(aice_handle_aice_desc_command)
 	LOG_DEBUG("aice_handle_aice_desc_command");
 
 	if (CMD_ARGC == 1)
-		aice.param.device_desc = strdup(CMD_ARGV[0]);
+		param.device_desc = strdup(CMD_ARGV[0]);
 	else
 		LOG_ERROR("expected exactly one argument to aice desc <description>");
 
@@ -282,7 +292,7 @@ COMMAND_HANDLER(aice_handle_aice_serial_command)
 	LOG_DEBUG("aice_handle_aice_serial_command");
 
 	if (CMD_ARGC == 1)
-		aice.param.serial = strdup(CMD_ARGV[0]);
+		param.serial = strdup(CMD_ARGV[0]);
 	else
 		LOG_ERROR("expected exactly one argument to aice serial <serial-number>");
 
@@ -298,8 +308,8 @@ COMMAND_HANDLER(aice_handle_aice_vid_pid_command)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
-	COMMAND_PARSE_NUMBER(u16, CMD_ARGV[0], aice.param.vid);
-	COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], aice.param.pid);
+	COMMAND_PARSE_NUMBER(u16, CMD_ARGV[0], param.vid);
+	COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], param.pid);
 
 	return ERROR_OK;
 }
@@ -309,7 +319,7 @@ COMMAND_HANDLER(aice_handle_aice_adapter_command)
 	LOG_DEBUG("aice_handle_aice_adapter_command");
 
 	if (CMD_ARGC == 1)
-		aice.param.adapter_name = strdup(CMD_ARGV[0]);
+		param.adapter_name = strdup(CMD_ARGV[0]);
 	else
 		LOG_ERROR("expected exactly one argument to aice adapter <adapter-name>");
 
@@ -321,7 +331,7 @@ COMMAND_HANDLER(aice_handle_aice_retry_times_command)
 	LOG_DEBUG("aice_handle_aice_retry_times_command");
 
 	if (CMD_ARGC == 1)
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], aice.retry_times);
+		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], retry_times);
 	else
 		LOG_ERROR("expected exactly one argument to aice retry_times <num_of_retry>");
 
@@ -333,7 +343,7 @@ COMMAND_HANDLER(aice_handle_aice_count_to_check_dbger_command)
 	LOG_DEBUG("aice_handle_aice_count_to_check_dbger_command");
 
 	if (CMD_ARGC == 1)
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], aice.count_to_check_dbger);
+		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], count_to_check_dbger);
 	else
 		LOG_ERROR("expected exactly one argument to aice count_to_check_dbger "
 				"<count_of_checking>");
@@ -346,7 +356,7 @@ COMMAND_HANDLER(aice_handle_aice_custom_srst_script_command)
 	LOG_DEBUG("aice_handle_aice_custom_srst_script_command");
 
 	if (CMD_ARGC > 0) {
-		aice.port->api->set_custom_srst_script(CMD_ARGV[0]);
+		aice_port->api->set_custom_srst_script(CMD_ARGV[0]);
 		return ERROR_OK;
 	}
 
@@ -358,7 +368,7 @@ COMMAND_HANDLER(aice_handle_aice_custom_trst_script_command)
 	LOG_DEBUG("aice_handle_aice_custom_trst_script_command");
 
 	if (CMD_ARGC > 0) {
-		aice.port->api->set_custom_trst_script(CMD_ARGV[0]);
+		aice_port->api->set_custom_trst_script(CMD_ARGV[0]);
 		return ERROR_OK;
 	}
 
@@ -370,7 +380,7 @@ COMMAND_HANDLER(aice_handle_aice_custom_restart_script_command)
 	LOG_DEBUG("aice_handle_aice_custom_restart_script_command");
 
 	if (CMD_ARGC > 0) {
-		aice.port->api->set_custom_restart_script(CMD_ARGV[0]);
+		aice_port->api->set_custom_restart_script(CMD_ARGV[0]);
 		return ERROR_OK;
 	}
 
@@ -381,7 +391,7 @@ COMMAND_HANDLER(aice_handle_aice_reset_command)
 {
 	LOG_DEBUG("aice_handle_aice_reset_command");
 
-	return aice.port->api->reset();
+	return aice_port->api->reset();
 }
 
 
@@ -497,4 +507,3 @@ struct jtag_interface aice_interface = {
 	.speed_div = aice_speed_div,	/* return readable value */
 	.khz = aice_khz,		/* convert khz to interface speed value */
 };
-
diff --git a/src/jtag/aice/aice_interface.h b/src/jtag/aice/aice_interface.h
index e7077a7..c7b896c 100644
--- a/src/jtag/aice/aice_interface.h
+++ b/src/jtag/aice/aice_interface.h
@@ -31,6 +31,6 @@ struct aice_interface_param_s {
 	uint16_t pid;
 };
 
-int aice_init_target(struct target *t);
+int aice_init_targets(void);
 
 #endif
diff --git a/src/jtag/aice/aice_pipe.c b/src/jtag/aice/aice_pipe.c
index 02caa3f..44eade2 100644
--- a/src/jtag/aice/aice_pipe.c
+++ b/src/jtag/aice/aice_pipe.c
@@ -348,7 +348,7 @@ static int aice_pipe_idcode(uint32_t *idcode, uint8_t *num_of_idcode)
 	return ERROR_OK;
 }
 
-static int aice_pipe_state(enum aice_target_state_s *state)
+static int aice_pipe_state(uint32_t coreid, enum aice_target_state_s *state)
 {
 	char line[AICE_PIPE_MAXLINE];
 	char command[AICE_PIPE_MAXLINE];
@@ -385,7 +385,7 @@ static int aice_pipe_reset(void)
 		return ERROR_FAIL;
 }
 
-static int aice_pipe_assert_srst(enum aice_srst_type_s srst)
+static int aice_pipe_assert_srst(uint32_t coreid, enum aice_srst_type_s srst)
 {
 	char line[AICE_PIPE_MAXLINE];
 	char command[AICE_PIPE_MAXLINE];
@@ -405,7 +405,7 @@ static int aice_pipe_assert_srst(enum aice_srst_type_s srst)
 		return ERROR_FAIL;
 }
 
-static int aice_pipe_run(void)
+static int aice_pipe_run(uint32_t coreid)
 {
 	char line[AICE_PIPE_MAXLINE];
 	char command[AICE_PIPE_MAXLINE];
@@ -424,7 +424,7 @@ static int aice_pipe_run(void)
 		return ERROR_FAIL;
 }
 
-static int aice_pipe_halt(void)
+static int aice_pipe_halt(uint32_t coreid)
 {
 	char line[AICE_PIPE_MAXLINE];
 	char command[AICE_PIPE_MAXLINE];
@@ -443,7 +443,7 @@ static int aice_pipe_halt(void)
 		return ERROR_FAIL;
 }
 
-static int aice_pipe_read_reg(uint32_t num, uint32_t *val)
+static int aice_pipe_read_reg(uint32_t coreid, uint32_t num, uint32_t *val)
 {
 	char line[AICE_PIPE_MAXLINE];
 	char command[AICE_PIPE_MAXLINE];
@@ -462,7 +462,7 @@ static int aice_pipe_read_reg(uint32_t num, uint32_t *val)
 	return ERROR_OK;
 }
 
-static int aice_pipe_write_reg(uint32_t num, uint32_t val)
+static int aice_pipe_write_reg(uint32_t coreid, uint32_t num, uint32_t val)
 {
 	char line[AICE_PIPE_MAXLINE];
 	char command[AICE_PIPE_MAXLINE];
@@ -483,7 +483,7 @@ static int aice_pipe_write_reg(uint32_t num, uint32_t val)
 		return ERROR_FAIL;
 }
 
-static int aice_pipe_read_reg_64(uint32_t num, uint64_t *val)
+static int aice_pipe_read_reg_64(uint32_t coreid, uint32_t num, uint64_t *val)
 {
 	char line[AICE_PIPE_MAXLINE];
 	char command[AICE_PIPE_MAXLINE];
@@ -502,7 +502,7 @@ static int aice_pipe_read_reg_64(uint32_t num, uint64_t *val)
 	return ERROR_OK;
 }
 
-static int aice_pipe_write_reg_64(uint32_t num, uint64_t val)
+static int aice_pipe_write_reg_64(uint32_t coreid, uint32_t num, uint64_t val)
 {
 	char line[AICE_PIPE_MAXLINE];
 	char command[AICE_PIPE_MAXLINE];
@@ -524,7 +524,7 @@ static int aice_pipe_write_reg_64(uint32_t num, uint64_t val)
 		return ERROR_FAIL;
 }
 
-static int aice_pipe_step(void)
+static int aice_pipe_step(uint32_t coreid)
 {
 	char line[AICE_PIPE_MAXLINE];
 	char command[AICE_PIPE_MAXLINE];
@@ -543,7 +543,7 @@ static int aice_pipe_step(void)
 		return ERROR_FAIL;
 }
 
-static int aice_pipe_read_mem_unit(uint32_t addr, uint32_t size,
+static int aice_pipe_read_mem_unit(uint32_t coreid, uint32_t addr, uint32_t size,
 		uint32_t count, uint8_t *buffer)
 {
 	char command[AICE_PIPE_MAXLINE];
@@ -562,7 +562,7 @@ static int aice_pipe_read_mem_unit(uint32_t addr, uint32_t size,
 	return ERROR_OK;
 }
 
-static int aice_pipe_write_mem_unit(uint32_t addr, uint32_t size,
+static int aice_pipe_write_mem_unit(uint32_t coreid, uint32_t addr, uint32_t size,
 		uint32_t count, const uint8_t *buffer)
 {
 	char line[AICE_PIPE_MAXLINE];
@@ -590,7 +590,8 @@ static int aice_pipe_write_mem_unit(uint32_t addr, uint32_t size,
 	return ERROR_OK;
 }
 
-static int aice_pipe_read_mem_bulk(uint32_t addr, uint32_t length, uint8_t *buffer)
+static int aice_pipe_read_mem_bulk(uint32_t coreid, uint32_t addr,
+		uint32_t length, uint8_t *buffer)
 {
 	char line[AICE_PIPE_MAXLINE + 1];
 	char command[AICE_PIPE_MAXLINE];
@@ -636,7 +637,8 @@ static int aice_pipe_read_mem_bulk(uint32_t addr, uint32_t length, uint8_t *buff
 	return ERROR_OK;
 }
 
-static int aice_pipe_write_mem_bulk(uint32_t addr, uint32_t length, const uint8_t *buffer)
+static int aice_pipe_write_mem_bulk(uint32_t coreid, uint32_t addr,
+		uint32_t length, const uint8_t *buffer)
 {
 	char line[AICE_PIPE_MAXLINE];
 	char command[AICE_PIPE_MAXLINE + 4];
@@ -686,7 +688,7 @@ static int aice_pipe_write_mem_bulk(uint32_t addr, uint32_t length, const uint8_
 		return ERROR_FAIL;
 }
 
-static int aice_pipe_read_debug_reg(uint32_t addr, uint32_t *val)
+static int aice_pipe_read_debug_reg(uint32_t coreid, uint32_t addr, uint32_t *val)
 {
 	char line[AICE_PIPE_MAXLINE];
 	char command[AICE_PIPE_MAXLINE];
@@ -705,7 +707,7 @@ static int aice_pipe_read_debug_reg(uint32_t addr, uint32_t *val)
 	return ERROR_OK;
 }
 
-static int aice_pipe_write_debug_reg(uint32_t addr, const uint32_t val)
+static int aice_pipe_write_debug_reg(uint32_t coreid, uint32_t addr, const uint32_t val)
 {
 	char line[AICE_PIPE_MAXLINE];
 	char command[AICE_PIPE_MAXLINE];
@@ -746,27 +748,7 @@ static int aice_pipe_set_jtag_clock(uint32_t a_clock)
 		return ERROR_FAIL;
 }
 
-static int aice_pipe_select_target(uint32_t target_id)
-{
-	char line[AICE_PIPE_MAXLINE];
-	char command[AICE_PIPE_MAXLINE];
-
-	command[0] = AICE_SELECT_TARGET;
-	set_u32(command + 1, target_id);
-
-	if (aice_pipe_write(command, 5) != 5)
-		return ERROR_FAIL;
-
-	if (aice_pipe_read(line, AICE_PIPE_MAXLINE) < 0)
-		return ERROR_FAIL;
-
-	if (line[0] == AICE_OK)
-		return ERROR_OK;
-	else
-		return ERROR_FAIL;
-}
-
-static int aice_pipe_memory_access(enum nds_memory_access access_channel)
+static int aice_pipe_memory_access(uint32_t coreid, enum nds_memory_access access_channel)
 {
 	char line[AICE_PIPE_MAXLINE];
 	char command[AICE_PIPE_MAXLINE];
@@ -786,7 +768,7 @@ static int aice_pipe_memory_access(enum nds_memory_access access_channel)
 		return ERROR_FAIL;
 }
 
-static int aice_pipe_memory_mode(enum nds_memory_select mem_select)
+static int aice_pipe_memory_mode(uint32_t coreid, enum nds_memory_select mem_select)
 {
 	char line[AICE_PIPE_MAXLINE];
 	char command[AICE_PIPE_MAXLINE];
@@ -806,7 +788,8 @@ static int aice_pipe_memory_mode(enum nds_memory_select mem_select)
 		return ERROR_FAIL;
 }
 
-static int aice_pipe_read_tlb(uint32_t virtual_address, uint32_t *physical_address)
+static int aice_pipe_read_tlb(uint32_t coreid, uint32_t virtual_address,
+		uint32_t *physical_address)
 {
 	char line[AICE_PIPE_MAXLINE];
 	char command[AICE_PIPE_MAXLINE];
@@ -827,7 +810,7 @@ static int aice_pipe_read_tlb(uint32_t virtual_address, uint32_t *physical_addre
 		return ERROR_FAIL;
 }
 
-static int aice_pipe_cache_ctl(uint32_t subtype, uint32_t address)
+static int aice_pipe_cache_ctl(uint32_t coreid, uint32_t subtype, uint32_t address)
 {
 	char line[AICE_PIPE_MAXLINE];
 	char command[AICE_PIPE_MAXLINE];
@@ -862,6 +845,8 @@ struct aice_port_api_s aice_pipe = {
 	/** */
 	.idcode = aice_pipe_idcode,
 	/** */
+	.set_jtag_clock = aice_pipe_set_jtag_clock,
+	/** */
 	.state = aice_pipe_state,
 	/** */
 	.reset = aice_pipe_reset,
@@ -895,11 +880,6 @@ struct aice_port_api_s aice_pipe = {
 	.write_debug_reg = aice_pipe_write_debug_reg,
 
 	/** */
-	.set_jtag_clock = aice_pipe_set_jtag_clock,
-	/** */
-	.select_target = aice_pipe_select_target,
-
-	/** */
 	.memory_access = aice_pipe_memory_access,
 	/** */
 	.memory_mode = aice_pipe_memory_mode,
diff --git a/src/jtag/aice/aice_port.h b/src/jtag/aice/aice_port.h
index 35bc61c..241f8b8 100644
--- a/src/jtag/aice/aice_port.h
+++ b/src/jtag/aice/aice_port.h
@@ -22,6 +22,8 @@
 
 #include <target/nds32_edm.h>
 
+#define AICE_MAX_NUM_CORE      (0x10)
+
 #define ERROR_AICE_DISCONNECT  (-200)
 #define ERROR_AICE_TIMEOUT     (-201)
 
@@ -49,6 +51,8 @@ enum aice_api_s {
 	AICE_OPEN = 0x0,
 	AICE_CLOSE,
 	AICE_RESET,
+	AICE_IDCODE,
+	AICE_SET_JTAG_CLOCK,
 	AICE_ASSERT_SRST,
 	AICE_RUN,
 	AICE_HALT,
@@ -63,10 +67,7 @@ enum aice_api_s {
 	AICE_WRITE_MEM_BULK,
 	AICE_READ_DEBUG_REG,
 	AICE_WRITE_DEBUG_REG,
-	AICE_IDCODE,
 	AICE_STATE,
-	AICE_SET_JTAG_CLOCK,
-	AICE_SELECT_TARGET,
 	AICE_MEMORY_ACCESS,
 	AICE_MEMORY_MODE,
 	AICE_READ_TLB,
@@ -118,13 +119,9 @@ struct aice_port_param_s {
 
 struct aice_port_s {
 	/** */
-	struct aice_port_param_s param;
+	uint32_t coreid;
 	/** */
 	const struct aice_port *port;
-	/** */
-	uint32_t retry_times;
-	/** */
-	uint32_t count_to_check_dbger;
 };
 
 /** */
@@ -139,70 +136,67 @@ struct aice_port_api_s {
 	/** */
 	int (*reset)(void);
 	/** */
-	int (*assert_srst)(enum aice_srst_type_s srst);
+	int (*idcode)(uint32_t *idcode, uint8_t *num_of_idcode);
 	/** */
-	int (*run)(void);
+	int (*set_jtag_clock)(uint32_t a_clock);
 	/** */
-	int (*halt)(void);
+	int (*assert_srst)(uint32_t coreid, enum aice_srst_type_s srst);
 	/** */
-	int (*step)(void);
+	int (*run)(uint32_t coreid);
 	/** */
-	int (*read_reg)(uint32_t num, uint32_t *val);
+	int (*halt)(uint32_t coreid);
 	/** */
-	int (*write_reg)(uint32_t num, uint32_t val);
+	int (*step)(uint32_t coreid);
 	/** */
-	int (*read_reg_64)(uint32_t num, uint64_t *val);
+	int (*read_reg)(uint32_t coreid, uint32_t num, uint32_t *val);
 	/** */
-	int (*write_reg_64)(uint32_t num, uint64_t val);
+	int (*write_reg)(uint32_t coreid, uint32_t num, uint32_t val);
 	/** */
-	int (*read_mem_unit)(uint32_t addr, uint32_t size, uint32_t count,
-			uint8_t *buffer);
+	int (*read_reg_64)(uint32_t coreid, uint32_t num, uint64_t *val);
 	/** */
-	int (*write_mem_unit)(uint32_t addr, uint32_t size, uint32_t count,
-			const uint8_t *buffer);
+	int (*write_reg_64)(uint32_t coreid, uint32_t num, uint64_t val);
 	/** */
-	int (*read_mem_bulk)(uint32_t addr, uint32_t length,
-			uint8_t *buffer);
+	int (*read_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
+			uint32_t count, uint8_t *buffer);
 	/** */
-	int (*write_mem_bulk)(uint32_t addr, uint32_t length,
-			const uint8_t *buffer);
+	int (*write_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
+			uint32_t count, const uint8_t *buffer);
 	/** */
-	int (*read_debug_reg)(uint32_t addr, uint32_t *val);
+	int (*read_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
+			uint8_t *buffer);
 	/** */
-	int (*write_debug_reg)(uint32_t addr, const uint32_t val);
-
+	int (*write_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
+			const uint8_t *buffer);
 	/** */
-	int (*idcode)(uint32_t *idcode, uint8_t *num_of_idcode);
+	int (*read_debug_reg)(uint32_t coreid, uint32_t addr, uint32_t *val);
 	/** */
-	int (*state)(enum aice_target_state_s *state);
+	int (*write_debug_reg)(uint32_t coreid, uint32_t addr, const uint32_t val);
 
 	/** */
-	int (*set_jtag_clock)(uint32_t a_clock);
-	/** */
-	int (*select_target)(uint32_t target_id);
+	int (*state)(uint32_t coreid, enum aice_target_state_s *state);
 
 	/** */
-	int (*memory_access)(enum nds_memory_access a_access);
+	int (*memory_access)(uint32_t coreid, enum nds_memory_access a_access);
 	/** */
-	int (*memory_mode)(enum nds_memory_select mem_select);
+	int (*memory_mode)(uint32_t coreid, enum nds_memory_select mem_select);
 
 	/** */
-	int (*read_tlb)(uint32_t virtual_address, uint32_t *physical_address);
+	int (*read_tlb)(uint32_t coreid, uint32_t virtual_address, uint32_t *physical_address);
 
 	/** */
-	int (*cache_ctl)(uint32_t subtype, uint32_t address);
+	int (*cache_ctl)(uint32_t coreid, uint32_t subtype, uint32_t address);
 
 	/** */
 	int (*set_retry_times)(uint32_t a_retry_times);
 
 	/** */
-	int (*program_edm)(char *command_sequence);
+	int (*program_edm)(uint32_t coreid, char *command_sequence);
 
 	/** */
 	int (*set_command_mode)(enum aice_command_mode command_mode);
 
 	/** */
-	int (*execute)(uint32_t *instructions, uint32_t instruction_num);
+	int (*execute)(uint32_t coreid, uint32_t *instructions, uint32_t instruction_num);
 
 	/** */
 	int (*set_custom_srst_script)(const char *script);
@@ -217,10 +211,10 @@ struct aice_port_api_s {
 	int (*set_count_to_check_dbger)(uint32_t count_to_check);
 
 	/** */
-	int (*set_data_endian)(enum aice_target_endian target_data_endian);
+	int (*set_data_endian)(uint32_t coreid, enum aice_target_endian target_data_endian);
 
 	/** */
-	int (*profiling)(uint32_t interval, uint32_t iteration,
+	int (*profiling)(uint32_t coreid, uint32_t interval, uint32_t iteration,
 		uint32_t reg_no, uint32_t *samples, uint32_t *num_samples);
 };
 
@@ -235,7 +229,7 @@ struct aice_port {
 	/** */
 	int type;
 	/** */
-	struct aice_port_api_s *api;
+	struct aice_port_api_s *const api;
 };
 
 /** */
diff --git a/src/jtag/aice/aice_transport.c b/src/jtag/aice/aice_transport.c
index 3add3d9..0c208bf 100644
--- a/src/jtag/aice/aice_transport.c
+++ b/src/jtag/aice/aice_transport.c
@@ -351,7 +351,7 @@ static int aice_transport_init(struct command_context *cmd_ctx)
 
 	LOG_DEBUG("current transport %s", transport->name);
 
-	return aice_init_target(t);
+	return aice_init_targets();
 }
 
 /* */
diff --git a/src/jtag/aice/aice_usb.c b/src/jtag/aice/aice_usb.c
index 6bd9c19..ccd6997 100644
--- a/src/jtag/aice/aice_usb.c
+++ b/src/jtag/aice/aice_usb.c
@@ -34,7 +34,6 @@
 /* Global USB buffers */
 static uint8_t usb_in_buffer[AICE_IN_BUFFER_SIZE];
 static uint8_t usb_out_buffer[AICE_OUT_BUFFER_SIZE];
-static uint8_t current_target_id;
 static uint32_t jtag_clock;
 static struct aice_usb_handler_s aice_handler;
 /* AICE max retry times. If AICE command timeout, retry it. */
@@ -487,7 +486,7 @@ static int aice_usb_packet_append(uint8_t *out_buffer, int out_length, int in_le
 
 /***************************************************************************/
 /* AICE commands */
-static int aice_edm_reset(void)
+static int aice_reset_box(void)
 {
 	if (aice_write_ctrl(AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS, 0x1) != ERROR_OK)
 		return ERROR_FAIL;
@@ -533,27 +532,28 @@ static int aice_scan_chain(uint32_t *id_codes, uint8_t *num_of_ids)
 		aice_unpack_dtha_multiple_data(&cmd_ack_code, num_of_ids, id_codes,
 				0x10, AICE_LITTLE_ENDIAN);
 
-		LOG_DEBUG("SCAN_CHAIN response, # of IDs: %d", *num_of_ids);
-
 		if (cmd_ack_code != AICE_CMD_SCAN_CHAIN) {
-			LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
-					AICE_CMD_SCAN_CHAIN, cmd_ack_code);
 
-			if (retry_times > aice_max_retry_times)
+			if (retry_times > aice_max_retry_times) {
+				LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
+						AICE_CMD_SCAN_CHAIN, cmd_ack_code);
 				return ERROR_FAIL;
+			}
 
 			/* clear timeout and retry */
-			if (aice_edm_reset() != ERROR_OK)
+			if (aice_reset_box() != ERROR_OK)
 				return ERROR_FAIL;
 
 			retry_times++;
 			continue;
 		}
 
+		LOG_DEBUG("SCAN_CHAIN response, # of IDs: %d", *num_of_ids);
+
 		if (*num_of_ids == 0xFF) {
 			LOG_ERROR("No target connected");
 			return ERROR_FAIL;
-		} else if (*num_of_ids == 0x10) {
+		} else if (*num_of_ids == AICE_MAX_NUM_CORE) {
 			LOG_INFO("The ice chain over 16 targets");
 		} else {
 			(*num_of_ids)++;
@@ -654,7 +654,7 @@ int aice_read_dtr(uint8_t target_id, uint32_t *data)
 
 		aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA);
 
-		LOG_DEBUG("READ_DTR");
+		LOG_DEBUG("READ_DTR, COREID: %d", target_id);
 
 		result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
 		if (AICE_FORMAT_DTHMA != result) {
@@ -669,19 +669,19 @@ int aice_read_dtr(uint8_t target_id, uint32_t *data)
 		aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length,
 				data, AICE_LITTLE_ENDIAN);
 
-		LOG_DEBUG("READ_DTR response, data: 0x%x", *data);
-
 		if (cmd_ack_code == AICE_CMD_T_READ_DTR) {
+			LOG_DEBUG("READ_DTR response, data: 0x%x", *data);
 			break;
 		} else {
-			LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
-					AICE_CMD_T_READ_DTR, cmd_ack_code);
 
-			if (retry_times > aice_max_retry_times)
+			if (retry_times > aice_max_retry_times) {
+				LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
+						AICE_CMD_T_READ_DTR, cmd_ack_code);
 				return ERROR_FAIL;
+			}
 
 			/* clear timeout and retry */
-			if (aice_edm_reset() != ERROR_OK)
+			if (aice_reset_box() != ERROR_OK)
 				return ERROR_FAIL;
 
 			retry_times++;
@@ -709,7 +709,7 @@ int aice_read_dtr_to_buffer(uint8_t target_id, uint32_t buffer_idx)
 
 		aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA);
 
-		LOG_DEBUG("READ_DTR_TO_BUFFER");
+		LOG_DEBUG("READ_DTR_TO_BUFFER, COREID: %d", target_id);
 
 		result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
 		if (AICE_FORMAT_DTHMB != result) {
@@ -725,13 +725,15 @@ int aice_read_dtr_to_buffer(uint8_t target_id, uint32_t buffer_idx)
 		if (cmd_ack_code == AICE_CMD_READ_DTR_TO_BUFFER) {
 			break;
 		} else {
-			LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)", AICE_CMD_READ_DTR_TO_BUFFER, cmd_ack_code);
+			if (retry_times > aice_max_retry_times) {
+				LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
+						AICE_CMD_READ_DTR_TO_BUFFER, cmd_ack_code);
 
-			if (retry_times > aice_max_retry_times)
 				return ERROR_FAIL;
+			}
 
 			/* clear timeout and retry */
-			if (aice_edm_reset() != ERROR_OK)
+			if (aice_reset_box() != ERROR_OK)
 				return ERROR_FAIL;
 
 			retry_times++;
@@ -759,7 +761,7 @@ int aice_write_dtr(uint8_t target_id, uint32_t data)
 
 		aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC);
 
-		LOG_DEBUG("WRITE_DTR, data: 0x%x", data);
+		LOG_DEBUG("WRITE_DTR, COREID: %d, data: 0x%x", target_id, data);
 
 		result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
 		if (AICE_FORMAT_DTHMB != result) {
@@ -772,18 +774,19 @@ int aice_write_dtr(uint8_t target_id, uint32_t data)
 		uint8_t res_target_id;
 		aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
 
-		LOG_DEBUG("WRITE_DTR response");
-
 		if (cmd_ack_code == AICE_CMD_T_WRITE_DTR) {
+			LOG_DEBUG("WRITE_DTR response");
 			break;
 		} else {
-			LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)", AICE_CMD_T_WRITE_DTR, cmd_ack_code);
+			if (retry_times > aice_max_retry_times) {
+				LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
+						AICE_CMD_T_WRITE_DTR, cmd_ack_code);
 
-			if (retry_times > aice_max_retry_times)
 				return ERROR_FAIL;
+			}
 
 			/* clear timeout and retry */
-			if (aice_edm_reset() != ERROR_OK)
+			if (aice_reset_box() != ERROR_OK)
 				return ERROR_FAIL;
 
 			retry_times++;
@@ -811,7 +814,7 @@ int aice_write_dtr_from_buffer(uint8_t target_id, uint32_t buffer_idx)
 
 		aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA);
 
-		LOG_DEBUG("WRITE_DTR_FROM_BUFFER");
+		LOG_DEBUG("WRITE_DTR_FROM_BUFFER, COREID: %d", target_id);
 
 		result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
 		if (AICE_FORMAT_DTHMB != result) {
@@ -827,14 +830,15 @@ int aice_write_dtr_from_buffer(uint8_t target_id, uint32_t buffer_idx)
 		if (cmd_ack_code == AICE_CMD_WRITE_DTR_FROM_BUFFER) {
 			break;
 		} else {
-			LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
-					AICE_CMD_WRITE_DTR_FROM_BUFFER, cmd_ack_code);
+			if (retry_times > aice_max_retry_times) {
+				LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
+						AICE_CMD_WRITE_DTR_FROM_BUFFER, cmd_ack_code);
 
-			if (retry_times > aice_max_retry_times)
 				return ERROR_FAIL;
+			}
 
 			/* clear timeout and retry */
-			if (aice_edm_reset() != ERROR_OK)
+			if (aice_reset_box() != ERROR_OK)
 				return ERROR_FAIL;
 
 			retry_times++;
@@ -858,7 +862,7 @@ int aice_read_misc(uint8_t target_id, uint32_t address, uint32_t *data)
 
 		aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA);
 
-		LOG_DEBUG("READ_MISC, address: 0x%x", address);
+		LOG_DEBUG("READ_MISC, COREID: %d, address: 0x%x", target_id, address);
 
 		result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
 		if (AICE_FORMAT_DTHMA != result) {
@@ -873,19 +877,18 @@ int aice_read_misc(uint8_t target_id, uint32_t address, uint32_t *data)
 		aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length,
 				data, AICE_LITTLE_ENDIAN);
 
-		LOG_DEBUG("READ_MISC response, data: 0x%x", *data);
-
 		if (cmd_ack_code == AICE_CMD_T_READ_MISC) {
+			LOG_DEBUG("READ_MISC response, data: 0x%x", *data);
 			break;
 		} else {
-			LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
-					AICE_CMD_T_READ_MISC, cmd_ack_code);
-
-			if (retry_times > aice_max_retry_times)
+			if (retry_times > aice_max_retry_times) {
+				LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
+						AICE_CMD_T_READ_MISC, cmd_ack_code);
 				return ERROR_FAIL;
+			}
 
 			/* clear timeout and retry */
-			if (aice_edm_reset() != ERROR_OK)
+			if (aice_reset_box() != ERROR_OK)
 				return ERROR_FAIL;
 
 			retry_times++;
@@ -915,7 +918,8 @@ int aice_write_misc(uint8_t target_id, uint32_t address, uint32_t data)
 
 		aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC);
 
-		LOG_DEBUG("WRITE_MISC, address: 0x%x, data: 0x%x", address, data);
+		LOG_DEBUG("WRITE_MISC, COREID: %d, address: 0x%x, data: 0x%x",
+				target_id, address, data);
 
 		result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
 		if (AICE_FORMAT_DTHMB != result) {
@@ -929,19 +933,19 @@ int aice_write_misc(uint8_t target_id, uint32_t address, uint32_t data)
 		uint8_t res_target_id;
 		aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
 
-		LOG_DEBUG("WRITE_MISC response");
-
 		if (cmd_ack_code == AICE_CMD_T_WRITE_MISC) {
+			LOG_DEBUG("WRITE_MISC response");
 			break;
 		} else {
-			LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
-					AICE_CMD_T_WRITE_MISC, cmd_ack_code);
+			if (retry_times > aice_max_retry_times) {
+				LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
+						AICE_CMD_T_WRITE_MISC, cmd_ack_code);
 
-			if (retry_times > aice_max_retry_times)
 				return ERROR_FAIL;
+			}
 
 			/* clear timeout and retry */
-			if (aice_edm_reset() != ERROR_OK)
+			if (aice_reset_box() != ERROR_OK)
 				return ERROR_FAIL;
 
 			retry_times++;
@@ -965,7 +969,7 @@ int aice_read_edmsr(uint8_t target_id, uint32_t address, uint32_t *data)
 
 		aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMA);
 
-		LOG_DEBUG("READ_EDMSR, address: 0x%x", address);
+		LOG_DEBUG("READ_EDMSR, COREID: %d, address: 0x%x", target_id, address);
 
 		result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
 		if (AICE_FORMAT_DTHMA != result) {
@@ -980,19 +984,19 @@ int aice_read_edmsr(uint8_t target_id, uint32_t address, uint32_t *data)
 		aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length,
 				data, AICE_LITTLE_ENDIAN);
 
-		LOG_DEBUG("READ_EDMSR response, data: 0x%x", *data);
-
 		if (cmd_ack_code == AICE_CMD_T_READ_EDMSR) {
+			LOG_DEBUG("READ_EDMSR response, data: 0x%x", *data);
 			break;
 		} else {
-			LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
-					AICE_CMD_T_READ_EDMSR, cmd_ack_code);
+			if (retry_times > aice_max_retry_times) {
+				LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
+						AICE_CMD_T_READ_EDMSR, cmd_ack_code);
 
-			if (retry_times > aice_max_retry_times)
 				return ERROR_FAIL;
+			}
 
 			/* clear timeout and retry */
-			if (aice_edm_reset() != ERROR_OK)
+			if (aice_reset_box() != ERROR_OK)
 				return ERROR_FAIL;
 
 			retry_times++;
@@ -1022,7 +1026,8 @@ int aice_write_edmsr(uint8_t target_id, uint32_t address, uint32_t data)
 
 		aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC);
 
-		LOG_DEBUG("WRITE_EDMSR, address: 0x%x, data: 0x%x", address, data);
+		LOG_DEBUG("WRITE_EDMSR, COREID: %d, address: 0x%x, data: 0x%x",
+				target_id, address, data);
 
 		result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
 		if (AICE_FORMAT_DTHMB != result) {
@@ -1036,19 +1041,19 @@ int aice_write_edmsr(uint8_t target_id, uint32_t address, uint32_t data)
 		uint8_t res_target_id;
 		aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
 
-		LOG_DEBUG("WRITE_EDMSR response");
-
 		if (cmd_ack_code == AICE_CMD_T_WRITE_EDMSR) {
+			LOG_DEBUG("WRITE_EDMSR response");
 			break;
 		} else {
-			LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
-					AICE_CMD_T_WRITE_EDMSR, cmd_ack_code);
+			if (retry_times > aice_max_retry_times) {
+				LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
+						AICE_CMD_T_WRITE_EDMSR, cmd_ack_code);
 
-			if (retry_times > aice_max_retry_times)
 				return ERROR_FAIL;
+			}
 
 			/* clear timeout and retry */
-			if (aice_edm_reset() != ERROR_OK)
+			if (aice_reset_box() != ERROR_OK)
 				return ERROR_FAIL;
 
 			retry_times++;
@@ -1100,8 +1105,12 @@ static int aice_write_dim(uint8_t target_id, uint32_t *word, uint8_t num_of_word
 
 		aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC + (num_of_words - 1) * 4);
 
-		LOG_DEBUG("WRITE_DIM, data: 0x%08x, 0x%08x, 0x%08x, 0x%08x", big_endian_word[0],
-				big_endian_word[1], big_endian_word[2], big_endian_word[3]);
+		LOG_DEBUG("WRITE_DIM, COREID: %d, data: 0x%08x, 0x%08x, 0x%08x, 0x%08x",
+				target_id,
+				big_endian_word[0],
+				big_endian_word[1],
+				big_endian_word[2],
+				big_endian_word[3]);
 
 		result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
 		if (AICE_FORMAT_DTHMB != result) {
@@ -1114,18 +1123,19 @@ static int aice_write_dim(uint8_t target_id, uint32_t *word, uint8_t num_of_word
 		uint8_t res_target_id;
 		aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
 
-		LOG_DEBUG("WRITE_DIM response");
 
 		if (cmd_ack_code == AICE_CMD_T_WRITE_DIM) {
+			LOG_DEBUG("WRITE_DIM response");
 			break;
 		} else {
-			LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)", AICE_CMD_T_WRITE_DIM, cmd_ack_code);
+			if (retry_times > aice_max_retry_times) {
+				LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)", AICE_CMD_T_WRITE_DIM, cmd_ack_code);
 
-			if (retry_times > aice_max_retry_times)
 				return ERROR_FAIL;
+			}
 
 			/* clear timeout and retry */
-			if (aice_edm_reset() != ERROR_OK)
+			if (aice_reset_box() != ERROR_OK)
 				return ERROR_FAIL;
 
 			retry_times++;
@@ -1154,7 +1164,7 @@ static int aice_do_execute(uint8_t target_id)
 
 		aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMC);
 
-		LOG_DEBUG("EXECUTE");
+		LOG_DEBUG("EXECUTE, COREID: %d", target_id);
 
 		result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
 		if (AICE_FORMAT_DTHMB != result) {
@@ -1168,19 +1178,19 @@ static int aice_do_execute(uint8_t target_id)
 		uint8_t res_target_id;
 		aice_unpack_dthmb(&cmd_ack_code, &res_target_id, &extra_length);
 
-		LOG_DEBUG("EXECUTE response");
-
 		if (cmd_ack_code == AICE_CMD_T_EXECUTE) {
+			LOG_DEBUG("EXECUTE response");
 			break;
 		} else {
-			LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
-					AICE_CMD_T_EXECUTE, cmd_ack_code);
+			if (retry_times > aice_max_retry_times) {
+				LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
+						AICE_CMD_T_EXECUTE, cmd_ack_code);
 
-			if (retry_times > aice_max_retry_times)
 				return ERROR_FAIL;
+			}
 
 			/* clear timeout and retry */
-			if (aice_edm_reset() != ERROR_OK)
+			if (aice_reset_box() != ERROR_OK)
 				return ERROR_FAIL;
 
 			retry_times++;
@@ -1195,7 +1205,8 @@ int aice_write_mem_b(uint8_t target_id, uint32_t address, uint32_t data)
 	int result;
 	int retry_times = 0;
 
-	LOG_DEBUG("WRITE_MEM_B, ADDRESS %08" PRIx32 "  VALUE %08" PRIx32,
+	LOG_DEBUG("WRITE_MEM_B, COREID: %d, ADDRESS %08" PRIx32 "  VALUE %08" PRIx32,
+			target_id,
 			address,
 			data);
 
@@ -1225,13 +1236,15 @@ int aice_write_mem_b(uint8_t target_id, uint32_t address, uint32_t data)
 			if (cmd_ack_code == AICE_CMD_T_WRITE_MEM_B) {
 				break;
 			} else {
-				LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)", AICE_CMD_T_WRITE_MEM_B, cmd_ack_code);
+				if (retry_times > aice_max_retry_times) {
+					LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
+							AICE_CMD_T_WRITE_MEM_B, cmd_ack_code);
 
-				if (retry_times > aice_max_retry_times)
 					return ERROR_FAIL;
+				}
 
 				/* clear timeout and retry */
-				if (aice_edm_reset() != ERROR_OK)
+				if (aice_reset_box() != ERROR_OK)
 					return ERROR_FAIL;
 
 				retry_times++;
@@ -1247,7 +1260,8 @@ int aice_write_mem_h(uint8_t target_id, uint32_t address, uint32_t data)
 	int result;
 	int retry_times = 0;
 
-	LOG_DEBUG("WRITE_MEM_H, ADDRESS %08" PRIx32 "  VALUE %08" PRIx32,
+	LOG_DEBUG("WRITE_MEM_H, COREID: %d, ADDRESS %08" PRIx32 "  VALUE %08" PRIx32,
+			target_id,
 			address,
 			data);
 
@@ -1278,14 +1292,15 @@ int aice_write_mem_h(uint8_t target_id, uint32_t address, uint32_t data)
 			if (cmd_ack_code == AICE_CMD_T_WRITE_MEM_H) {
 				break;
 			} else {
-				LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
-						AICE_CMD_T_WRITE_MEM_H, cmd_ack_code);
+				if (retry_times > aice_max_retry_times) {
+					LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
+							AICE_CMD_T_WRITE_MEM_H, cmd_ack_code);
 
-				if (retry_times > aice_max_retry_times)
 					return ERROR_FAIL;
+				}
 
 				/* clear timeout and retry */
-				if (aice_edm_reset() != ERROR_OK)
+				if (aice_reset_box() != ERROR_OK)
 					return ERROR_FAIL;
 
 				retry_times++;
@@ -1301,7 +1316,8 @@ int aice_write_mem(uint8_t target_id, uint32_t address, uint32_t data)
 	int result;
 	int retry_times = 0;
 
-	LOG_DEBUG("WRITE_MEM, ADDRESS %08" PRIx32 "  VALUE %08" PRIx32,
+	LOG_DEBUG("WRITE_MEM, COREID: %d, ADDRESS %08" PRIx32 "  VALUE %08" PRIx32,
+			target_id,
 			address,
 			data);
 
@@ -1332,14 +1348,15 @@ int aice_write_mem(uint8_t target_id, uint32_t address, uint32_t data)
 			if (cmd_ack_code == AICE_CMD_T_WRITE_MEM) {
 				break;
 			} else {
-				LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
-						AICE_CMD_T_WRITE_MEM, cmd_ack_code);
+				if (retry_times > aice_max_retry_times) {
+					LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
+							AICE_CMD_T_WRITE_MEM, cmd_ack_code);
 
-				if (retry_times > aice_max_retry_times)
 					return ERROR_FAIL;
+				}
 
 				/* clear timeout and retry */
-				if (aice_edm_reset() != ERROR_OK)
+				if (aice_reset_box() != ERROR_OK)
 					return ERROR_FAIL;
 
 				retry_times++;
@@ -1364,7 +1381,8 @@ int aice_fastread_mem(uint8_t target_id, uint8_t *word, uint32_t num_of_words)
 
 		aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMB);
 
-		LOG_DEBUG("FASTREAD_MEM, # of DATA %08" PRIx32, num_of_words);
+		LOG_DEBUG("FASTREAD_MEM, COREID: %d, # of DATA %08" PRIx32,
+				target_id, num_of_words);
 
 		result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA + (num_of_words - 1) * 4);
 		if (result < 0) {
@@ -1382,14 +1400,15 @@ int aice_fastread_mem(uint8_t target_id, uint8_t *word, uint32_t num_of_words)
 		if (cmd_ack_code == AICE_CMD_T_FASTREAD_MEM) {
 			break;
 		} else {
-			LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
-					AICE_CMD_T_FASTREAD_MEM, cmd_ack_code);
+			if (retry_times > aice_max_retry_times) {
+				LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
+						AICE_CMD_T_FASTREAD_MEM, cmd_ack_code);
 
-			if (retry_times > aice_max_retry_times)
 				return ERROR_FAIL;
+			}
 
 			/* clear timeout and retry */
-			if (aice_edm_reset() != ERROR_OK)
+			if (aice_reset_box() != ERROR_OK)
 				return ERROR_FAIL;
 
 			retry_times++;
@@ -1420,7 +1439,8 @@ int aice_fastwrite_mem(uint8_t target_id, const uint8_t *word, uint32_t num_of_w
 
 		aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMD + (num_of_words - 1) * 4);
 
-		LOG_DEBUG("FASTWRITE_MEM, # of DATA %08" PRIx32, num_of_words);
+		LOG_DEBUG("FASTWRITE_MEM, COREID: %d, # of DATA %08" PRIx32,
+				target_id, num_of_words);
 
 		result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMB);
 		if (AICE_FORMAT_DTHMB != result) {
@@ -1437,14 +1457,15 @@ int aice_fastwrite_mem(uint8_t target_id, const uint8_t *word, uint32_t num_of_w
 		if (cmd_ack_code == AICE_CMD_T_FASTWRITE_MEM) {
 			break;
 		} else {
-			LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
-					AICE_CMD_T_FASTWRITE_MEM, cmd_ack_code);
+			if (retry_times > aice_max_retry_times) {
+				LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
+						AICE_CMD_T_FASTWRITE_MEM, cmd_ack_code);
 
-			if (retry_times > aice_max_retry_times)
 				return ERROR_FAIL;
+			}
 
 			/* clear timeout and retry */
-			if (aice_edm_reset() != ERROR_OK)
+			if (aice_reset_box() != ERROR_OK)
 				return ERROR_FAIL;
 
 			retry_times++;
@@ -1468,7 +1489,7 @@ int aice_read_mem_b(uint8_t target_id, uint32_t address, uint32_t *data)
 
 		aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMB);
 
-		LOG_DEBUG("READ_MEM_B");
+		LOG_DEBUG("READ_MEM_B, COREID: %d", target_id);
 
 		result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
 		if (AICE_FORMAT_DTHMA != result) {
@@ -1483,19 +1504,19 @@ int aice_read_mem_b(uint8_t target_id, uint32_t address, uint32_t *data)
 		aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length,
 				data, data_endian);
 
-		LOG_DEBUG("READ_MEM_B response, data: 0x%x", *data);
-
 		if (cmd_ack_code == AICE_CMD_T_READ_MEM_B) {
+			LOG_DEBUG("READ_MEM_B response, data: 0x%02x", *data);
 			break;
 		} else {
-			LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
-					AICE_CMD_T_READ_MEM_B, cmd_ack_code);
+			if (retry_times > aice_max_retry_times) {
+				LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
+						AICE_CMD_T_READ_MEM_B, cmd_ack_code);
 
-			if (retry_times > aice_max_retry_times)
 				return ERROR_FAIL;
+			}
 
 			/* clear timeout and retry */
-			if (aice_edm_reset() != ERROR_OK)
+			if (aice_reset_box() != ERROR_OK)
 				return ERROR_FAIL;
 
 			retry_times++;
@@ -1519,7 +1540,7 @@ int aice_read_mem_h(uint8_t target_id, uint32_t address, uint32_t *data)
 
 		aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMB);
 
-		LOG_DEBUG("READ_MEM_H");
+		LOG_DEBUG("READ_MEM_H, CORE_ID: %d", target_id);
 
 		result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
 		if (AICE_FORMAT_DTHMA != result) {
@@ -1534,19 +1555,19 @@ int aice_read_mem_h(uint8_t target_id, uint32_t address, uint32_t *data)
 		aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length,
 				data, data_endian);
 
-		LOG_DEBUG("READ_MEM_H response, data: 0x%x", *data);
-
 		if (cmd_ack_code == AICE_CMD_T_READ_MEM_H) {
+			LOG_DEBUG("READ_MEM_H response, data: 0x%x", *data);
 			break;
 		} else {
-			LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
-					AICE_CMD_T_READ_MEM_H, cmd_ack_code);
+			if (retry_times > aice_max_retry_times) {
+				LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
+						AICE_CMD_T_READ_MEM_H, cmd_ack_code);
 
-			if (retry_times > aice_max_retry_times)
 				return ERROR_FAIL;
+			}
 
 			/* clear timeout and retry */
-			if (aice_edm_reset() != ERROR_OK)
+			if (aice_reset_box() != ERROR_OK)
 				return ERROR_FAIL;
 
 			retry_times++;
@@ -1571,7 +1592,7 @@ int aice_read_mem(uint8_t target_id, uint32_t address, uint32_t *data)
 
 		aice_usb_write(usb_out_buffer, AICE_FORMAT_HTDMB);
 
-		LOG_DEBUG("READ_MEM");
+		LOG_DEBUG("READ_MEM, COREID: %d", target_id);
 
 		result = aice_usb_read(usb_in_buffer, AICE_FORMAT_DTHMA);
 		if (AICE_FORMAT_DTHMA != result) {
@@ -1586,19 +1607,19 @@ int aice_read_mem(uint8_t target_id, uint32_t address, uint32_t *data)
 		aice_unpack_dthma(&cmd_ack_code, &res_target_id, &extra_length,
 				data, data_endian);
 
-		LOG_DEBUG("READ_MEM response, data: 0x%x", *data);
-
 		if (cmd_ack_code == AICE_CMD_T_READ_MEM) {
+			LOG_DEBUG("READ_MEM response, data: 0x%x", *data);
 			break;
 		} else {
-			LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
-					AICE_CMD_T_READ_MEM, cmd_ack_code);
+			if (retry_times > aice_max_retry_times) {
+				LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
+						AICE_CMD_T_READ_MEM, cmd_ack_code);
 
-			if (retry_times > aice_max_retry_times)
 				return ERROR_FAIL;
+			}
 
 			/* clear timeout and retry */
-			if (aice_edm_reset() != ERROR_OK)
+			if (aice_reset_box() != ERROR_OK)
 				return ERROR_FAIL;
 
 			retry_times++;
@@ -1636,14 +1657,15 @@ int aice_batch_buffer_read(uint8_t buf_index, uint32_t *word, uint32_t num_of_wo
 		if (cmd_ack_code == AICE_CMD_BATCH_BUFFER_READ) {
 			break;
 		} else {
-			LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
-					AICE_CMD_BATCH_BUFFER_READ, cmd_ack_code);
+			if (retry_times > aice_max_retry_times) {
+				LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
+						AICE_CMD_BATCH_BUFFER_READ, cmd_ack_code);
 
-			if (retry_times > aice_max_retry_times)
 				return ERROR_FAIL;
+			}
 
 			/* clear timeout and retry */
-			if (aice_edm_reset() != ERROR_OK)
+			if (aice_reset_box() != ERROR_OK)
 				return ERROR_FAIL;
 
 			retry_times++;
@@ -1688,14 +1710,15 @@ int aice_batch_buffer_write(uint8_t buf_index, const uint8_t *word, uint32_t num
 		if (cmd_ack_code == AICE_CMD_BATCH_BUFFER_WRITE) {
 			break;
 		} else {
-			LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
-					AICE_CMD_BATCH_BUFFER_WRITE, cmd_ack_code);
+			if (retry_times > aice_max_retry_times) {
+				LOG_ERROR("aice command timeout (command=0x%x, response=0x%x)",
+						AICE_CMD_BATCH_BUFFER_WRITE, cmd_ack_code);
 
-			if (retry_times > aice_max_retry_times)
 				return ERROR_FAIL;
+			}
 
 			/* clear timeout and retry */
-			if (aice_edm_reset() != ERROR_OK)
+			if (aice_reset_box() != ERROR_OK)
 				return ERROR_FAIL;
 
 			retry_times++;
@@ -1708,43 +1731,21 @@ int aice_batch_buffer_write(uint8_t buf_index, const uint8_t *word, uint32_t num
 /***************************************************************************/
 /* End of AICE commands */
 
-typedef int (*read_mem_func_t)(uint32_t address, uint32_t *data);
-typedef int (*write_mem_func_t)(uint32_t address, uint32_t data);
-struct cache_info {
-	uint32_t set;
-	uint32_t way;
-	uint32_t line_size;
+typedef int (*read_mem_func_t)(uint32_t coreid, uint32_t address, uint32_t *data);
+typedef int (*write_mem_func_t)(uint32_t coreid, uint32_t address, uint32_t data);
 
-	uint32_t log2_set;
-	uint32_t log2_line_size;
-};
+struct aice_nds32_info core_info[AICE_MAX_NUM_CORE];
+static uint8_t total_num_of_core;
 
-static uint32_t r0_backup;
-static uint32_t r1_backup;
-static uint32_t host_dtr_backup;
-static uint32_t target_dtr_backup;
-static uint32_t edmsw_backup;
-static uint32_t edm_ctl_backup;
-static bool debug_under_dex_on;
-static bool dex_use_psw_on;
-static bool host_dtr_valid;
-static bool target_dtr_valid;
-static enum nds_memory_access access_channel = NDS_MEMORY_ACC_CPU;
-static enum nds_memory_select memory_select = NDS_MEMORY_SELECT_AUTO;
-static enum aice_target_state_s core_state = AICE_TARGET_UNKNOWN;
-static uint32_t edm_version;
-static struct cache_info icache = {0, 0, 0, 0, 0};
-static struct cache_info dcache = {0, 0, 0, 0, 0};
-static bool cache_init;
 static char *custom_srst_script;
 static char *custom_trst_script;
 static char *custom_restart_script;
 static uint32_t aice_count_to_check_dbger = 30;
 
-static int aice_read_reg(uint32_t num, uint32_t *val);
-static int aice_write_reg(uint32_t num, uint32_t val);
+static int aice_read_reg(uint32_t coreid, uint32_t num, uint32_t *val);
+static int aice_write_reg(uint32_t coreid, uint32_t num, uint32_t val);
 
-static int check_suppressed_exception(uint32_t dbger_value)
+static int check_suppressed_exception(uint32_t coreid, uint32_t dbger_value)
 {
 	uint32_t ir4_value;
 	uint32_t ir6_value;
@@ -1758,9 +1759,9 @@ static int check_suppressed_exception(uint32_t dbger_value)
 		LOG_ERROR("<-- TARGET WARNING! Exception is detected and suppressed. -->");
 		handling_suppressed_exception = true;
 
-		aice_read_reg(IR4, &ir4_value);
+		aice_read_reg(coreid, IR4, &ir4_value);
 		/* Clear IR6.SUPRS_EXC, IR6.IMP_EXC */
-		aice_read_reg(IR6, &ir6_value);
+		aice_read_reg(coreid, IR6, &ir6_value);
 		/*
 		 * For MCU version(MSC_CFG.MCU == 1) like V3m
 		 *  | SWID[30:16] | Reserved[15:10] | SUPRS_EXC[9]  | IMP_EXC[8]
@@ -1775,7 +1776,7 @@ static int check_suppressed_exception(uint32_t dbger_value)
 
 		ir6_value = ir6_value & (~0x300); /* for MCU */
 		ir6_value = ir6_value & (~0x3000); /* for non-MCU */
-		aice_write_reg(IR6, ir6_value);
+		aice_write_reg(coreid, IR6, ir6_value);
 
 		handling_suppressed_exception = false;
 	}
@@ -1783,14 +1784,14 @@ static int check_suppressed_exception(uint32_t dbger_value)
 	return ERROR_OK;
 }
 
-static int check_privilege(uint32_t dbger_value)
+static int check_privilege(uint32_t coreid, uint32_t dbger_value)
 {
 	if ((dbger_value & NDS_DBGER_ILL_SEC_ACC) == NDS_DBGER_ILL_SEC_ACC) {
 		LOG_ERROR("<-- TARGET ERROR! Insufficient security privilege "
 				"to execute the debug operations. -->");
 
 		/* Clear DBGER.ILL_SEC_ACC */
-		if (aice_write_misc(current_target_id, NDS_EDM_MISC_DBGER,
+		if (aice_write_misc(coreid, NDS_EDM_MISC_DBGER,
 					NDS_DBGER_ILL_SEC_ACC) != ERROR_OK)
 			return ERROR_FAIL;
 	}
@@ -1798,18 +1799,18 @@ static int check_privilege(uint32_t dbger_value)
 	return ERROR_OK;
 }
 
-static int aice_check_dbger(uint32_t expect_status)
+static int aice_check_dbger(uint32_t coreid, uint32_t expect_status)
 {
 	uint32_t i = 0;
 	uint32_t value_dbger;
 
 	while (1) {
-		aice_read_misc(current_target_id, NDS_EDM_MISC_DBGER, &value_dbger);
+		aice_read_misc(coreid, NDS_EDM_MISC_DBGER, &value_dbger);
 
 		if ((value_dbger & expect_status) == expect_status) {
-			if (ERROR_OK != check_suppressed_exception(value_dbger))
+			if (ERROR_OK != check_suppressed_exception(coreid, value_dbger))
 				return ERROR_FAIL;
-			if (ERROR_OK != check_privilege(value_dbger))
+			if (ERROR_OK != check_privilege(coreid, value_dbger))
 				return ERROR_FAIL;
 			return ERROR_OK;
 		}
@@ -1833,22 +1834,22 @@ static int aice_check_dbger(uint32_t expect_status)
 	return ERROR_FAIL;
 }
 
-static int aice_execute_dim(uint32_t *insts, uint8_t n_inst)
+static int aice_execute_dim(uint32_t coreid, uint32_t *insts, uint8_t n_inst)
 {
 	/** fill DIM */
-	if (aice_write_dim(current_target_id, insts, n_inst) != ERROR_OK)
+	if (aice_write_dim(coreid, insts, n_inst) != ERROR_OK)
 		return ERROR_FAIL;
 
 	/** clear DBGER.DPED */
-	if (aice_write_misc(current_target_id, NDS_EDM_MISC_DBGER, NDS_DBGER_DPED) != ERROR_OK)
+	if (aice_write_misc(coreid, NDS_EDM_MISC_DBGER, NDS_DBGER_DPED) != ERROR_OK)
 		return ERROR_FAIL;
 
 	/** execute DIM */
-	if (aice_do_execute(current_target_id) != ERROR_OK)
+	if (aice_do_execute(coreid) != ERROR_OK)
 		return ERROR_FAIL;
 
 	/** read DBGER.DPED */
-	if (aice_check_dbger(NDS_DBGER_DPED) != ERROR_OK) {
+	if (aice_check_dbger(coreid, NDS_DBGER_DPED) != ERROR_OK) {
 		LOG_ERROR("<-- TARGET ERROR! Debug operations do not finish properly: "
 				"0x%08x 0x%08x 0x%08x 0x%08x. -->",
 				insts[0],
@@ -1861,7 +1862,7 @@ static int aice_execute_dim(uint32_t *insts, uint8_t n_inst)
 	return ERROR_OK;
 }
 
-static int aice_read_reg(uint32_t num, uint32_t *val)
+static int aice_read_reg(uint32_t coreid, uint32_t num, uint32_t *val)
 {
 	LOG_DEBUG("aice_read_reg, reg_no: 0x%08x", num);
 
@@ -1920,12 +1921,12 @@ static int aice_read_reg(uint32_t num, uint32_t *val)
 		instructions[3] = BEQ_MINUS_12;
 	}
 
-	aice_execute_dim(instructions, 4);
+	aice_execute_dim(coreid, instructions, 4);
 
 	uint32_t value_edmsw;
-	aice_read_edmsr(current_target_id, NDS_EDM_SR_EDMSW, &value_edmsw);
+	aice_read_edmsr(coreid, NDS_EDM_SR_EDMSW, &value_edmsw);
 	if (value_edmsw & NDS_EDMSW_WDV)
-		aice_read_dtr(current_target_id, val);
+		aice_read_dtr(coreid, val);
 	else {
 		LOG_ERROR("<-- TARGET ERROR! The debug target failed to update "
 				"the DTR register. -->");
@@ -1935,42 +1936,42 @@ static int aice_read_reg(uint32_t num, uint32_t *val)
 	return ERROR_OK;
 }
 
-static int aice_usb_read_reg(uint32_t num, uint32_t *val)
+static int aice_usb_read_reg(uint32_t coreid, uint32_t num, uint32_t *val)
 {
 	LOG_DEBUG("aice_usb_read_reg");
 
 	if (num == R0) {
-		*val = r0_backup;
+		*val = core_info[coreid].r0_backup;
 	} else if (num == R1) {
-		*val = r1_backup;
+		*val = core_info[coreid].r1_backup;
 	} else if (num == DR41) {
 		/* As target is halted, OpenOCD will backup DR41/DR42/DR43.
 		 * As user wants to read these registers, OpenOCD should return
 		 * the backup values, instead of reading the real values.
 		 * As user wants to write these registers, OpenOCD should write
 		 * to the backup values, instead of writing to real registers. */
-		*val = edmsw_backup;
+		*val = core_info[coreid].edmsw_backup;
 	} else if (num == DR42) {
-		*val = edm_ctl_backup;
-	} else if ((target_dtr_valid == true) && (num == DR43)) {
-		*val = target_dtr_backup;
+		*val = core_info[coreid].edm_ctl_backup;
+	} else if ((core_info[coreid].target_dtr_valid == true) && (num == DR43)) {
+		*val = core_info[coreid].target_dtr_backup;
 	} else {
-		if (ERROR_OK != aice_read_reg(num, val))
+		if (ERROR_OK != aice_read_reg(coreid, num, val))
 			*val = 0xBBADBEEF;
 	}
 
 	return ERROR_OK;
 }
 
-static int aice_write_reg(uint32_t num, uint32_t val)
+static int aice_write_reg(uint32_t coreid, uint32_t num, uint32_t val)
 {
 	LOG_DEBUG("aice_write_reg, reg_no: 0x%08x, value: 0x%08x", num, val);
 
 	uint32_t instructions[4]; /** execute instructions in DIM */
 	uint32_t value_edmsw;
 
-	aice_write_dtr(current_target_id, val);
-	aice_read_edmsr(current_target_id, NDS_EDM_SR_EDMSW, &value_edmsw);
+	aice_write_dtr(coreid, val);
+	aice_read_edmsr(coreid, NDS_EDM_SR_EDMSW, &value_edmsw);
 	if (0 == (value_edmsw & NDS_EDMSW_RDV)) {
 		LOG_ERROR("<-- TARGET ERROR! AICE failed to write to the DTR register. -->");
 		return ERROR_FAIL;
@@ -2026,28 +2027,28 @@ static int aice_write_reg(uint32_t num, uint32_t val)
 		instructions[3] = BEQ_MINUS_12;
 	}
 
-	return aice_execute_dim(instructions, 4);
+	return aice_execute_dim(coreid, instructions, 4);
 }
 
-static int aice_usb_write_reg(uint32_t num, uint32_t val)
+static int aice_usb_write_reg(uint32_t coreid, uint32_t num, uint32_t val)
 {
 	LOG_DEBUG("aice_usb_write_reg");
 
 	if (num == R0)
-		r0_backup = val;
+		core_info[coreid].r0_backup = val;
 	else if (num == R1)
-		r1_backup = val;
+		core_info[coreid].r1_backup = val;
 	else if (num == DR42)
 		/* As target is halted, OpenOCD will backup DR41/DR42/DR43.
 		 * As user wants to read these registers, OpenOCD should return
 		 * the backup values, instead of reading the real values.
 		 * As user wants to write these registers, OpenOCD should write
 		 * to the backup values, instead of writing to real registers. */
-		edm_ctl_backup = val;
-	else if ((target_dtr_valid == true) && (num == DR43))
-		target_dtr_backup = val;
+		core_info[coreid].edm_ctl_backup = val;
+	else if ((core_info[coreid].target_dtr_valid == true) && (num == DR43))
+		core_info[coreid].target_dtr_backup = val;
 	else
-		return aice_write_reg(num, val);
+		return aice_write_reg(coreid, num, val);
 
 	return ERROR_OK;
 }
@@ -2110,17 +2111,17 @@ static int aice_usb_open(struct aice_port_param_s *param)
 	return ERROR_OK;
 }
 
-static int aice_usb_read_reg_64(uint32_t num, uint64_t *val)
+static int aice_usb_read_reg_64(uint32_t coreid, uint32_t num, uint64_t *val)
 {
 	LOG_DEBUG("aice_usb_read_reg_64, %s", nds32_reg_simple_name(num));
 
 	uint32_t value;
 	uint32_t high_value;
 
-	if (ERROR_OK != aice_read_reg(num, &value))
+	if (ERROR_OK != aice_read_reg(coreid, num, &value))
 		value = 0xBBADBEEF;
 
-	aice_read_reg(R1, &high_value);
+	aice_read_reg(coreid, R1, &high_value);
 
 	LOG_DEBUG("low: 0x%08x, high: 0x%08x\n", value, high_value);
 
@@ -2132,7 +2133,7 @@ static int aice_usb_read_reg_64(uint32_t num, uint64_t *val)
 	return ERROR_OK;
 }
 
-static int aice_usb_write_reg_64(uint32_t num, uint64_t val)
+static int aice_usb_write_reg_64(uint32_t coreid, uint32_t num, uint64_t val)
 {
 	uint32_t value;
 	uint32_t high_value;
@@ -2148,8 +2149,8 @@ static int aice_usb_write_reg_64(uint32_t num, uint64_t val)
 	LOG_DEBUG("aice_usb_write_reg_64, %s, low: 0x%08x, high: 0x%08x\n",
 			nds32_reg_simple_name(num), value, high_value);
 
-	aice_write_reg(R1, high_value);
-	return aice_write_reg(num, value);
+	aice_write_reg(coreid, R1, high_value);
+	return aice_write_reg(coreid, num, value);
 }
 
 static int aice_get_version_info(void)
@@ -2294,39 +2295,40 @@ static int aice_usb_set_clock(int set_clock)
 	return ERROR_OK;
 }
 
-static int aice_edm_init(void)
+static int aice_edm_init(uint32_t coreid)
 {
-	aice_write_edmsr(current_target_id, NDS_EDM_SR_DIMBR, 0xFFFF0000);
+	aice_write_edmsr(coreid, NDS_EDM_SR_DIMBR, 0xFFFF0000);
+	aice_write_misc(coreid, NDS_EDM_MISC_DIMIR, 0);
 
 	/* unconditionally try to turn on V3_EDM_MODE */
 	uint32_t edm_ctl_value;
-	aice_read_edmsr(current_target_id, NDS_EDM_SR_EDM_CTL, &edm_ctl_value);
-	aice_write_edmsr(current_target_id, NDS_EDM_SR_EDM_CTL, edm_ctl_value | 0x00000040);
+	aice_read_edmsr(coreid, NDS_EDM_SR_EDM_CTL, &edm_ctl_value);
+	aice_write_edmsr(coreid, NDS_EDM_SR_EDM_CTL, edm_ctl_value | 0x00000040);
 
-	aice_write_misc(current_target_id, NDS_EDM_MISC_DBGER,
+	/* clear DBGER */
+	aice_write_misc(coreid, NDS_EDM_MISC_DBGER,
 			NDS_DBGER_DPED | NDS_DBGER_CRST | NDS_DBGER_AT_MAX);
-	aice_write_misc(current_target_id, NDS_EDM_MISC_DIMIR, 0);
 
 	/* get EDM version */
 	uint32_t value_edmcfg;
-	aice_read_edmsr(current_target_id, NDS_EDM_SR_EDM_CFG, &value_edmcfg);
-	edm_version = (value_edmcfg >> 16) & 0xFFFF;
+	aice_read_edmsr(coreid, NDS_EDM_SR_EDM_CFG, &value_edmcfg);
+	core_info[coreid].edm_version = (value_edmcfg >> 16) & 0xFFFF;
 
 	return ERROR_OK;
 }
 
-static bool is_v2_edm(void)
+static bool is_v2_edm(uint32_t coreid)
 {
-	if ((edm_version & 0x1000) == 0)
+	if ((core_info[coreid].edm_version & 0x1000) == 0)
 		return true;
 	else
 		return false;
 }
 
-static int aice_init_edm_registers(bool clear_dex_use_psw)
+static int aice_init_edm_registers(uint32_t coreid, bool clear_dex_use_psw)
 {
 	/* enable DEH_SEL & MAX_STOP & V3_EDM_MODE & DBGI_MASK */
-	uint32_t host_edm_ctl = edm_ctl_backup | 0xA000004F;
+	uint32_t host_edm_ctl = core_info[coreid].edm_ctl_backup | 0xA000004F;
 	if (clear_dex_use_psw)
 		/* After entering debug mode, OpenOCD may set
 		 * DEX_USE_PSW accidentally through backup value
@@ -2336,7 +2338,7 @@ static int aice_init_edm_registers(bool clear_dex_use_psw)
 
 	LOG_DEBUG("aice_init_edm_registers - EDM_CTL: 0x%08x", host_edm_ctl);
 
-	int result = aice_write_edmsr(current_target_id, NDS_EDM_SR_EDM_CTL, host_edm_ctl);
+	int result = aice_write_edmsr(coreid, NDS_EDM_SR_EDM_CTL, host_edm_ctl);
 
 	return result;
 }
@@ -2353,9 +2355,10 @@ static int aice_init_edm_registers(bool clear_dex_use_psw)
  * running. The difference of these two scenarios is EDM_CTL.DEH_SEL
  * is on for scenario 1, and off for scenario 2.
  */
-static int aice_backup_edm_registers(void)
+static int aice_backup_edm_registers(uint32_t coreid)
 {
-	int result = aice_read_edmsr(current_target_id, NDS_EDM_SR_EDM_CTL, &edm_ctl_backup);
+	int result = aice_read_edmsr(coreid, NDS_EDM_SR_EDM_CTL,
+			&core_info[coreid].edm_ctl_backup);
 
 	/* To call aice_backup_edm_registers() after DEX on, DEX_USE_PSW
 	 * may be not correct.  (For example, hit breakpoint, then backup
@@ -2363,48 +2366,49 @@ static int aice_backup_edm_registers(void)
 	 * interrupt will clear DEX_USE_PSW, DEX_USE_PSW is always off after
 	 * DEX is on.  It only backups correct value before OpenOCD issues DBGI.
 	 * (Backup EDM_CTL, then issue DBGI actively (refer aice_usb_halt())) */
-	if (edm_ctl_backup & 0x40000000)
-		dex_use_psw_on = true;
+	if (core_info[coreid].edm_ctl_backup & 0x40000000)
+		core_info[coreid].dex_use_psw_on = true;
 	else
-		dex_use_psw_on = false;
+		core_info[coreid].dex_use_psw_on = false;
 
 	LOG_DEBUG("aice_backup_edm_registers - EDM_CTL: 0x%08x, DEX_USE_PSW: %s",
-			edm_ctl_backup, dex_use_psw_on ? "on" : "off");
+			core_info[coreid].edm_ctl_backup,
+			core_info[coreid].dex_use_psw_on ? "on" : "off");
 
 	return result;
 }
 
-static int aice_restore_edm_registers(void)
+static int aice_restore_edm_registers(uint32_t coreid)
 {
 	LOG_DEBUG("aice_restore_edm_registers -");
 
 	/* set DEH_SEL, because target still under EDM control */
-	int result = aice_write_edmsr(current_target_id, NDS_EDM_SR_EDM_CTL,
-			edm_ctl_backup | 0x80000000);
+	int result = aice_write_edmsr(coreid, NDS_EDM_SR_EDM_CTL,
+			core_info[coreid].edm_ctl_backup | 0x80000000);
 
 	return result;
 }
 
-static int aice_backup_tmp_registers(void)
+static int aice_backup_tmp_registers(uint32_t coreid)
 {
 	LOG_DEBUG("backup_tmp_registers -");
 
 	/* backup target DTR first(if the target DTR is valid) */
 	uint32_t value_edmsw;
-	aice_read_edmsr(current_target_id, NDS_EDM_SR_EDMSW, &value_edmsw);
-	edmsw_backup = value_edmsw;
+	aice_read_edmsr(coreid, NDS_EDM_SR_EDMSW, &value_edmsw);
+	core_info[coreid].edmsw_backup = value_edmsw;
 	if (value_edmsw & 0x1) { /* EDMSW.WDV == 1 */
-		aice_read_dtr(current_target_id, &target_dtr_backup);
-		target_dtr_valid = true;
+		aice_read_dtr(coreid, &core_info[coreid].target_dtr_backup);
+		core_info[coreid].target_dtr_valid = true;
 
-		LOG_DEBUG("Backup target DTR: 0x%08x", target_dtr_backup);
+		LOG_DEBUG("Backup target DTR: 0x%08x", core_info[coreid].target_dtr_backup);
 	} else {
-		target_dtr_valid = false;
+		core_info[coreid].target_dtr_valid = false;
 	}
 
 	/* Target DTR has been backup, then backup $R0 and $R1 */
-	aice_read_reg(R0, &r0_backup);
-	aice_read_reg(R1, &r1_backup);
+	aice_read_reg(coreid, R0, &core_info[coreid].r0_backup);
+	aice_read_reg(coreid, R1, &core_info[coreid].r1_backup);
 
 	/* backup host DTR(if the host DTR is valid) */
 	if (value_edmsw & 0x2) { /* EDMSW.RDV == 1*/
@@ -2416,50 +2420,52 @@ static int aice_backup_tmp_registers(void)
 			MTSR_DTR(R0),
 			BEQ_MINUS_12
 		};
-		aice_execute_dim(instructions, 4);
+		aice_execute_dim(coreid, instructions, 4);
 
-		aice_read_dtr(current_target_id, &host_dtr_backup);
-		host_dtr_valid = true;
+		aice_read_dtr(coreid, &core_info[coreid].host_dtr_backup);
+		core_info[coreid].host_dtr_valid = true;
 
-		LOG_DEBUG("Backup host DTR: 0x%08x", host_dtr_backup);
+		LOG_DEBUG("Backup host DTR: 0x%08x", core_info[coreid].host_dtr_backup);
 	} else {
-		host_dtr_valid = false;
+		core_info[coreid].host_dtr_valid = false;
 	}
 
-	LOG_DEBUG("r0: 0x%08x, r1: 0x%08x", r0_backup, r1_backup);
+	LOG_DEBUG("r0: 0x%08x, r1: 0x%08x",
+			core_info[coreid].r0_backup, core_info[coreid].r1_backup);
 
 	return ERROR_OK;
 }
 
-static int aice_restore_tmp_registers(void)
+static int aice_restore_tmp_registers(uint32_t coreid)
 {
-	LOG_DEBUG("restore_tmp_registers - r0: 0x%08x, r1: 0x%08x", r0_backup, r1_backup);
+	LOG_DEBUG("restore_tmp_registers - r0: 0x%08x, r1: 0x%08x",
+			core_info[coreid].r0_backup, core_info[coreid].r1_backup);
 
-	if (target_dtr_valid) {
+	if (core_info[coreid].target_dtr_valid) {
 		uint32_t instructions[4] = {
-			SETHI(R0, target_dtr_backup >> 12),
-			ORI(R0, R0, target_dtr_backup & 0x00000FFF),
+			SETHI(R0, core_info[coreid].target_dtr_backup >> 12),
+			ORI(R0, R0, core_info[coreid].target_dtr_backup & 0x00000FFF),
 			NOP,
 			BEQ_MINUS_12
 		};
-		aice_execute_dim(instructions, 4);
+		aice_execute_dim(coreid, instructions, 4);
 
 		instructions[0] = MTSR_DTR(R0);
 		instructions[1] = DSB;
 		instructions[2] = NOP;
 		instructions[3] = BEQ_MINUS_12;
-		aice_execute_dim(instructions, 4);
+		aice_execute_dim(coreid, instructions, 4);
 
-		LOG_DEBUG("Restore target DTR: 0x%08x", target_dtr_backup);
+		LOG_DEBUG("Restore target DTR: 0x%08x", core_info[coreid].target_dtr_backup);
 	}
 
-	aice_write_reg(R0, r0_backup);
-	aice_write_reg(R1, r1_backup);
+	aice_write_reg(coreid, R0, core_info[coreid].r0_backup);
+	aice_write_reg(coreid, R1, core_info[coreid].r1_backup);
 
-	if (host_dtr_valid) {
-		aice_write_dtr(current_target_id, host_dtr_backup);
+	if (core_info[coreid].host_dtr_valid) {
+		aice_write_dtr(coreid, core_info[coreid].host_dtr_backup);
 
-		LOG_DEBUG("Restore host DTR: 0x%08x", host_dtr_backup);
+		LOG_DEBUG("Restore host DTR: 0x%08x", core_info[coreid].host_dtr_backup);
 	}
 
 	return ERROR_OK;
@@ -2478,13 +2484,8 @@ static int aice_open_device(struct aice_port_param_s *param)
 	LOG_INFO("AICE initialization started");
 
 	/* attempt to reset Andes EDM */
-	if (ERROR_FAIL == aice_edm_reset()) {
-		LOG_ERROR("Cannot initial AICE Interface!");
-		return ERROR_FAIL;
-	}
-
-	if (ERROR_OK != aice_edm_init()) {
-		LOG_ERROR("Cannot initial EDM!");
+	if (ERROR_FAIL == aice_reset_box()) {
+		LOG_ERROR("Cannot initial AICE box!");
 		return ERROR_FAIL;
 	}
 
@@ -2519,14 +2520,34 @@ static int aice_usb_close(void)
 	return ERROR_OK;
 }
 
+static int aice_core_init(uint32_t coreid)
+{
+	core_info[coreid].access_channel = NDS_MEMORY_ACC_CPU;
+	core_info[coreid].memory_select = NDS_MEMORY_SELECT_AUTO;
+	core_info[coreid].core_state = AICE_TARGET_UNKNOWN;
+
+	return ERROR_OK;
+}
+
 static int aice_usb_idcode(uint32_t *idcode, uint8_t *num_of_idcode)
 {
-	return aice_scan_chain(idcode, num_of_idcode);
+	int retval;
+
+	retval = aice_scan_chain(idcode, num_of_idcode);
+	if (ERROR_OK == retval) {
+		for (int i = 0; i < *num_of_idcode; i++) {
+			aice_core_init(i);
+			aice_edm_init(i);
+		}
+		total_num_of_core = *num_of_idcode;
+	}
+
+	return retval;
 }
 
-static int aice_usb_halt(void)
+static int aice_usb_halt(uint32_t coreid)
 {
-	if (core_state == AICE_TARGET_HALTED) {
+	if (core_info[coreid].core_state == AICE_TARGET_HALTED) {
 		LOG_DEBUG("aice_usb_halt check halted");
 		return ERROR_OK;
 	}
@@ -2534,54 +2555,54 @@ static int aice_usb_halt(void)
 	LOG_DEBUG("aice_usb_halt");
 
 	/** backup EDM registers */
-	aice_backup_edm_registers();
+	aice_backup_edm_registers(coreid);
 	/** init EDM for host debugging */
 	/** no need to clear dex_use_psw, because dbgi will clear it */
-	aice_init_edm_registers(false);
+	aice_init_edm_registers(coreid, false);
 
 	/** Clear EDM_CTL.DBGIM & EDM_CTL.DBGACKM */
 	uint32_t edm_ctl_value;
-	aice_read_edmsr(current_target_id, NDS_EDM_SR_EDM_CTL, &edm_ctl_value);
+	aice_read_edmsr(coreid, NDS_EDM_SR_EDM_CTL, &edm_ctl_value);
 	if (edm_ctl_value & 0x3)
-		aice_write_edmsr(current_target_id, NDS_EDM_SR_EDM_CTL, edm_ctl_value & ~(0x3));
+		aice_write_edmsr(coreid, NDS_EDM_SR_EDM_CTL, edm_ctl_value & ~(0x3));
 
 	uint32_t dbger;
 	uint32_t acc_ctl_value;
 
-	debug_under_dex_on = false;
-	aice_read_misc(current_target_id, NDS_EDM_MISC_DBGER, &dbger);
+	core_info[coreid].debug_under_dex_on = false;
+	aice_read_misc(coreid, NDS_EDM_MISC_DBGER, &dbger);
 
 	if (dbger & NDS_DBGER_AT_MAX)
 		LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level. -->");
 
 	if (dbger & NDS_DBGER_DEX) {
-		if (is_v2_edm() == false) {
+		if (is_v2_edm(coreid) == false) {
 			/** debug 'debug mode'. use force_debug to issue dbgi */
-			aice_read_misc(current_target_id, NDS_EDM_MISC_ACC_CTL, &acc_ctl_value);
+			aice_read_misc(coreid, NDS_EDM_MISC_ACC_CTL, &acc_ctl_value);
 			acc_ctl_value |= 0x8;
-			aice_write_misc(current_target_id, NDS_EDM_MISC_ACC_CTL, acc_ctl_value);
-			debug_under_dex_on = true;
+			aice_write_misc(coreid, NDS_EDM_MISC_ACC_CTL, acc_ctl_value);
+			core_info[coreid].debug_under_dex_on = true;
 
-			aice_write_misc(current_target_id, NDS_EDM_MISC_EDM_CMDR, 0);
+			aice_write_misc(coreid, NDS_EDM_MISC_EDM_CMDR, 0);
 			/* If CPU stalled due to AT_MAX, clear AT_MAX status. */
 			if (dbger & NDS_DBGER_AT_MAX)
-				aice_write_misc(current_target_id, NDS_EDM_MISC_DBGER, NDS_DBGER_AT_MAX);
+				aice_write_misc(coreid, NDS_EDM_MISC_DBGER, NDS_DBGER_AT_MAX);
 		}
 	} else {
 		/** Issue DBGI normally */
-		aice_write_misc(current_target_id, NDS_EDM_MISC_EDM_CMDR, 0);
+		aice_write_misc(coreid, NDS_EDM_MISC_EDM_CMDR, 0);
 		/* If CPU stalled due to AT_MAX, clear AT_MAX status. */
 		if (dbger & NDS_DBGER_AT_MAX)
-			aice_write_misc(current_target_id, NDS_EDM_MISC_DBGER, NDS_DBGER_AT_MAX);
+			aice_write_misc(coreid, NDS_EDM_MISC_DBGER, NDS_DBGER_AT_MAX);
 	}
 
-	if (aice_check_dbger(NDS_DBGER_DEX) != ERROR_OK) {
+	if (aice_check_dbger(coreid, NDS_DBGER_DEX) != ERROR_OK) {
 		LOG_ERROR("<-- TARGET ERROR! Unable to stop the debug target through DBGI. -->");
 		return ERROR_FAIL;
 	}
 
-	if (debug_under_dex_on) {
-		if (dex_use_psw_on == false) {
+	if (core_info[coreid].debug_under_dex_on) {
+		if (core_info[coreid].dex_use_psw_on == false) {
 			/* under debug 'debug mode', force $psw to 'debug mode' bahavior */
 			/* !!!NOTICE!!! this is workaround for debug 'debug mode'.
 			 * it is only for debugging 'debug exception handler' purpose.
@@ -2589,30 +2610,30 @@ static int aice_usb_halt(void)
 			 * undefined. */
 			uint32_t ir0_value;
 			uint32_t debug_mode_ir0_value;
-			aice_read_reg(IR0, &ir0_value);
+			aice_read_reg(coreid, IR0, &ir0_value);
 			debug_mode_ir0_value = ir0_value | 0x408; /* turn on DEX, set POM = 1 */
 			debug_mode_ir0_value &= ~(0x000000C1); /* turn off DT/IT/GIE */
-			aice_write_reg(IR0, debug_mode_ir0_value);
+			aice_write_reg(coreid, IR0, debug_mode_ir0_value);
 		}
 	}
 
 	/** set EDM_CTL.DBGIM & EDM_CTL.DBGACKM after halt */
 	if (edm_ctl_value & 0x3)
-		aice_write_edmsr(current_target_id, NDS_EDM_SR_EDM_CTL, edm_ctl_value);
+		aice_write_edmsr(coreid, NDS_EDM_SR_EDM_CTL, edm_ctl_value);
 
 	/* backup r0 & r1 */
-	aice_backup_tmp_registers();
-	core_state = AICE_TARGET_HALTED;
+	aice_backup_tmp_registers(coreid);
+	core_info[coreid].core_state = AICE_TARGET_HALTED;
 
 	return ERROR_OK;
 }
 
-static int aice_usb_state(enum aice_target_state_s *state)
+static int aice_usb_state(uint32_t coreid, enum aice_target_state_s *state)
 {
 	uint32_t dbger_value;
 	uint32_t ice_state;
 
-	int result = aice_read_misc(current_target_id, NDS_EDM_MISC_DBGER, &dbger_value);
+	int result = aice_read_misc(coreid, NDS_EDM_MISC_DBGER, &dbger_value);
 
 	if (ERROR_AICE_TIMEOUT == result) {
 		if (aice_read_ctrl(AICE_READ_CTRL_GET_ICE_STATE, &ice_state) != ERROR_OK) {
@@ -2635,17 +2656,17 @@ static int aice_usb_state(enum aice_target_state_s *state)
 		LOG_ERROR("<-- TARGET ERROR! Insufficient security privilege. -->");
 
 		/* Clear ILL_SEC_ACC */
-		aice_write_misc(current_target_id, NDS_EDM_MISC_DBGER, NDS_DBGER_ILL_SEC_ACC);
+		aice_write_misc(coreid, NDS_EDM_MISC_DBGER, NDS_DBGER_ILL_SEC_ACC);
 
 		*state = AICE_TARGET_RUNNING;
-		core_state = AICE_TARGET_RUNNING;
+		core_info[coreid].core_state = AICE_TARGET_RUNNING;
 	} else if ((dbger_value & NDS_DBGER_AT_MAX) == NDS_DBGER_AT_MAX) {
 		/* Issue DBGI to exit cpu stall */
-		aice_usb_halt();
+		aice_usb_halt(coreid);
 
 		/* Read OIPC to find out the trigger point */
 		uint32_t ir11_value;
-		aice_read_reg(IR11, &ir11_value);
+		aice_read_reg(coreid, IR11, &ir11_value);
 
 		LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level; "
 				"CPU is stalled at 0x%08x for debugging. -->", ir11_value);
@@ -2655,27 +2676,27 @@ static int aice_usb_state(enum aice_target_state_s *state)
 		LOG_DEBUG("DBGER.CRST is on.");
 
 		*state = AICE_TARGET_RESET;
-		core_state = AICE_TARGET_RUNNING;
+		core_info[coreid].core_state = AICE_TARGET_RUNNING;
 
 		/* Clear CRST */
-		aice_write_misc(current_target_id, NDS_EDM_MISC_DBGER, NDS_DBGER_CRST);
+		aice_write_misc(coreid, NDS_EDM_MISC_DBGER, NDS_DBGER_CRST);
 	} else if ((dbger_value & NDS_DBGER_DEX) == NDS_DBGER_DEX) {
-		if (AICE_TARGET_RUNNING == core_state) {
+		if (AICE_TARGET_RUNNING == core_info[coreid].core_state) {
 			/* enter debug mode, init EDM registers */
 			/* backup EDM registers */
-			aice_backup_edm_registers();
+			aice_backup_edm_registers(coreid);
 			/* init EDM for host debugging */
-			aice_init_edm_registers(true);
-			aice_backup_tmp_registers();
-			core_state = AICE_TARGET_HALTED;
-		} else if (AICE_TARGET_UNKNOWN == core_state) {
+			aice_init_edm_registers(coreid, true);
+			aice_backup_tmp_registers(coreid);
+			core_info[coreid].core_state = AICE_TARGET_HALTED;
+		} else if (AICE_TARGET_UNKNOWN == core_info[coreid].core_state) {
 			/* debug 'debug mode', use force debug to halt core */
-			aice_usb_halt();
+			aice_usb_halt(coreid);
 		}
 		*state = AICE_TARGET_HALTED;
 	} else {
 		*state = AICE_TARGET_RUNNING;
-		core_state = AICE_TARGET_RUNNING;
+		core_info[coreid].core_state = AICE_TARGET_RUNNING;
 	}
 
 	return ERROR_OK;
@@ -2683,7 +2704,7 @@ static int aice_usb_state(enum aice_target_state_s *state)
 
 static int aice_usb_reset(void)
 {
-	if (aice_edm_reset() != ERROR_OK)
+	if (aice_reset_box() != ERROR_OK)
 		return ERROR_FAIL;
 
 	/* issue TRST */
@@ -2703,12 +2724,12 @@ static int aice_usb_reset(void)
 	return ERROR_OK;
 }
 
-static int aice_issue_srst(void)
+static int aice_issue_srst(uint32_t coreid)
 {
 	LOG_DEBUG("aice_issue_srst");
 
 	/* After issuing srst, target will be running. So we need to restore EDM_CTL. */
-	aice_restore_edm_registers();
+	aice_restore_edm_registers(coreid);
 
 	if (custom_srst_script == NULL) {
 		if (aice_write_ctrl(AICE_WRITE_CTRL_JTAG_PIN_CONTROL,
@@ -2724,7 +2745,7 @@ static int aice_issue_srst(void)
 	uint32_t dbger_value;
 	int i = 0;
 	while (1) {
-		if (aice_read_misc(current_target_id,
+		if (aice_read_misc(coreid,
 					NDS_EDM_MISC_DBGER, &dbger_value) != ERROR_OK)
 			return ERROR_FAIL;
 
@@ -2736,14 +2757,14 @@ static int aice_issue_srst(void)
 		i++;
 	}
 
-	host_dtr_valid = false;
-	target_dtr_valid = false;
+	core_info[coreid].host_dtr_valid = false;
+	core_info[coreid].target_dtr_valid = false;
 
-	core_state = AICE_TARGET_RUNNING;
+	core_info[coreid].core_state = AICE_TARGET_RUNNING;
 	return ERROR_OK;
 }
 
-static int aice_issue_reset_hold(void)
+static int aice_issue_reset_hold(uint32_t coreid)
 {
 	LOG_DEBUG("aice_issue_reset_hold");
 
@@ -2764,9 +2785,9 @@ static int aice_issue_reset_hold(void)
 			return ERROR_FAIL;
 	}
 
-	if (aice_check_dbger(NDS_DBGER_CRST | NDS_DBGER_DEX) == ERROR_OK) {
-		aice_backup_tmp_registers();
-		core_state = AICE_TARGET_HALTED;
+	if (aice_check_dbger(coreid, NDS_DBGER_CRST | NDS_DBGER_DEX) == ERROR_OK) {
+		aice_backup_tmp_registers(coreid);
+		core_info[coreid].core_state = AICE_TARGET_HALTED;
 
 		return ERROR_OK;
 	} else {
@@ -2784,58 +2805,89 @@ static int aice_issue_reset_hold(void)
 				return ERROR_FAIL;
 		}
 
-		if (aice_check_dbger(NDS_DBGER_CRST | NDS_DBGER_DEX) == ERROR_OK) {
-			aice_backup_tmp_registers();
-			core_state = AICE_TARGET_HALTED;
+		if (aice_check_dbger(coreid, NDS_DBGER_CRST | NDS_DBGER_DEX) == ERROR_OK) {
+			aice_backup_tmp_registers(coreid);
+			core_info[coreid].core_state = AICE_TARGET_HALTED;
 
 			return ERROR_OK;
 		}
 
 		/* do software reset-and-hold */
-		aice_issue_srst();
-		aice_usb_halt();
+		aice_issue_srst(coreid);
+		aice_usb_halt(coreid);
 
 		uint32_t value_ir3;
-		aice_read_reg(IR3, &value_ir3);
-		aice_write_reg(PC, value_ir3 & 0xFFFF0000);
+		aice_read_reg(coreid, IR3, &value_ir3);
+		aice_write_reg(coreid, PC, value_ir3 & 0xFFFF0000);
 	}
 
 	return ERROR_FAIL;
 }
 
-static int aice_usb_assert_srst(enum aice_srst_type_s srst)
+static int aice_issue_reset_hold_multi(void)
+{
+	uint32_t write_ctrl_value = 0;
+
+	/* set SRST */
+	write_ctrl_value = AICE_CUSTOM_DELAY_SET_SRST;
+	write_ctrl_value |= (0x200 << 16);
+	if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY,
+				write_ctrl_value) != ERROR_OK)
+		return ERROR_FAIL;
+
+	for (uint8_t i = 0 ; i < total_num_of_core ; i++)
+		aice_write_misc(i, NDS_EDM_MISC_EDM_CMDR, 0);
+
+	/* clear SRST */
+	write_ctrl_value = AICE_CUSTOM_DELAY_CLEAN_SRST;
+	write_ctrl_value |= (0x200 << 16);
+	if (aice_write_ctrl(AICE_WRITE_CTRL_CUSTOM_DELAY,
+				write_ctrl_value) != ERROR_OK)
+		return ERROR_FAIL;
+
+	for (uint8_t i = 0; i < total_num_of_core; i++)
+		aice_edm_init(i);
+
+	return ERROR_FAIL;
+}
+
+static int aice_usb_assert_srst(uint32_t coreid, enum aice_srst_type_s srst)
 {
 	if ((AICE_SRST != srst) && (AICE_RESET_HOLD != srst))
 		return ERROR_FAIL;
 
 	/* clear DBGER */
-	if (aice_write_misc(current_target_id, NDS_EDM_MISC_DBGER,
+	if (aice_write_misc(coreid, NDS_EDM_MISC_DBGER,
 				NDS_DBGER_CLEAR_ALL) != ERROR_OK)
 		return ERROR_FAIL;
 
 	int result = ERROR_OK;
 	if (AICE_SRST == srst)
-		result = aice_issue_srst();
-	else
-		result = aice_issue_reset_hold();
+		result = aice_issue_srst(coreid);
+	else {
+		if (1 == total_num_of_core)
+			result = aice_issue_reset_hold(coreid);
+		else
+			result = aice_issue_reset_hold_multi();
+	}
 
 	/* Clear DBGER.CRST after reset to avoid 'core-reset checking' errors.
 	 * assert_srst is user-intentional reset behavior, so we could
 	 * clear DBGER.CRST safely.
 	 */
-	if (aice_write_misc(current_target_id,
+	if (aice_write_misc(coreid,
 				NDS_EDM_MISC_DBGER, NDS_DBGER_CRST) != ERROR_OK)
 		return ERROR_FAIL;
 
 	return result;
 }
 
-static int aice_usb_run(void)
+static int aice_usb_run(uint32_t coreid)
 {
 	LOG_DEBUG("aice_usb_run");
 
 	uint32_t dbger_value;
-	if (aice_read_misc(current_target_id,
+	if (aice_read_misc(coreid,
 				NDS_EDM_MISC_DBGER, &dbger_value) != ERROR_OK)
 		return ERROR_FAIL;
 
@@ -2846,11 +2898,11 @@ static int aice_usb_run(void)
 	}
 
 	/* restore r0 & r1 before free run */
-	aice_restore_tmp_registers();
-	core_state = AICE_TARGET_RUNNING;
+	aice_restore_tmp_registers(coreid);
+	core_info[coreid].core_state = AICE_TARGET_RUNNING;
 
 	/* clear DBGER */
-	aice_write_misc(current_target_id, NDS_EDM_MISC_DBGER,
+	aice_write_misc(coreid, NDS_EDM_MISC_DBGER,
 			NDS_DBGER_CLEAR_ALL);
 
 	/** restore EDM registers */
@@ -2861,7 +2913,7 @@ static int aice_usb_run(void)
 	 *        slli $p0, $p0, 1
 	 *        slri $p0, $p0, 31
 	 */
-	aice_restore_edm_registers();
+	aice_restore_edm_registers(coreid);
 
 	/** execute instructions in DIM */
 	uint32_t instructions[4] = {
@@ -2870,40 +2922,40 @@ static int aice_usb_run(void)
 		NOP,
 		IRET
 	};
-	int result = aice_execute_dim(instructions, 4);
+	int result = aice_execute_dim(coreid, instructions, 4);
 
 	return result;
 }
 
-static int aice_usb_step(void)
+static int aice_usb_step(uint32_t coreid)
 {
 	LOG_DEBUG("aice_usb_step");
 
 	uint32_t ir0_value;
 	uint32_t ir0_reg_num;
 
-	if (is_v2_edm() == true)
+	if (is_v2_edm(coreid) == true)
 		/* V2 EDM will push interrupt stack as debug exception */
 		ir0_reg_num = IR1;
 	else
 		ir0_reg_num = IR0;
 
 	/** enable HSS */
-	aice_read_reg(ir0_reg_num, &ir0_value);
+	aice_read_reg(coreid, ir0_reg_num, &ir0_value);
 	if ((ir0_value & 0x800) == 0) {
 		/** set PSW.HSS */
 		ir0_value |= (0x01 << 11);
-		aice_write_reg(ir0_reg_num, ir0_value);
+		aice_write_reg(coreid, ir0_reg_num, ir0_value);
 	}
 
-	if (ERROR_FAIL == aice_usb_run())
+	if (ERROR_FAIL == aice_usb_run(coreid))
 		return ERROR_FAIL;
 
 	int i = 0;
 	enum aice_target_state_s state;
 	while (1) {
 		/* read DBGER */
-		if (aice_usb_state(&state) != ERROR_OK)
+		if (aice_usb_state(coreid, &state) != ERROR_OK)
 			return ERROR_FAIL;
 
 		if (AICE_TARGET_HALTED == state)
@@ -2923,29 +2975,29 @@ static int aice_usb_step(void)
 	}
 
 	/** disable HSS */
-	aice_read_reg(ir0_reg_num, &ir0_value);
+	aice_read_reg(coreid, ir0_reg_num, &ir0_value);
 	ir0_value &= ~(0x01 << 11);
-	aice_write_reg(ir0_reg_num, ir0_value);
+	aice_write_reg(coreid, ir0_reg_num, ir0_value);
 
 	return ERROR_OK;
 }
 
-static int aice_usb_read_mem_b_bus(uint32_t address, uint32_t *data)
+static int aice_usb_read_mem_b_bus(uint32_t coreid, uint32_t address, uint32_t *data)
 {
-	return aice_read_mem_b(current_target_id, address, data);
+	return aice_read_mem_b(coreid, address, data);
 }
 
-static int aice_usb_read_mem_h_bus(uint32_t address, uint32_t *data)
+static int aice_usb_read_mem_h_bus(uint32_t coreid, uint32_t address, uint32_t *data)
 {
-	return aice_read_mem_h(current_target_id, address, data);
+	return aice_read_mem_h(coreid, address, data);
 }
 
-static int aice_usb_read_mem_w_bus(uint32_t address, uint32_t *data)
+static int aice_usb_read_mem_w_bus(uint32_t coreid, uint32_t address, uint32_t *data)
 {
-	return aice_read_mem(current_target_id, address, data);
+	return aice_read_mem(coreid, address, data);
 }
 
-static int aice_usb_read_mem_b_dim(uint32_t address, uint32_t *data)
+static int aice_usb_read_mem_b_dim(uint32_t coreid, uint32_t address, uint32_t *data)
 {
 	uint32_t value;
 	uint32_t instructions[4] = {
@@ -2955,15 +3007,15 @@ static int aice_usb_read_mem_b_dim(uint32_t address, uint32_t *data)
 		BEQ_MINUS_12
 	};
 
-	aice_execute_dim(instructions, 4);
+	aice_execute_dim(coreid, instructions, 4);
 
-	aice_read_dtr(current_target_id, &value);
+	aice_read_dtr(coreid, &value);
 	*data = value & 0xFF;
 
 	return ERROR_OK;
 }
 
-static int aice_usb_read_mem_h_dim(uint32_t address, uint32_t *data)
+static int aice_usb_read_mem_h_dim(uint32_t coreid, uint32_t address, uint32_t *data)
 {
 	uint32_t value;
 	uint32_t instructions[4] = {
@@ -2973,15 +3025,15 @@ static int aice_usb_read_mem_h_dim(uint32_t address, uint32_t *data)
 		BEQ_MINUS_12
 	};
 
-	aice_execute_dim(instructions, 4);
+	aice_execute_dim(coreid, instructions, 4);
 
-	aice_read_dtr(current_target_id, &value);
+	aice_read_dtr(coreid, &value);
 	*data = value & 0xFFFF;
 
 	return ERROR_OK;
 }
 
-static int aice_usb_read_mem_w_dim(uint32_t address, uint32_t *data)
+static int aice_usb_read_mem_w_dim(uint32_t coreid, uint32_t address, uint32_t *data)
 {
 	uint32_t instructions[4] = {
 		LWI_BI(R1, R0),
@@ -2990,14 +3042,14 @@ static int aice_usb_read_mem_w_dim(uint32_t address, uint32_t *data)
 		BEQ_MINUS_12
 	};
 
-	aice_execute_dim(instructions, 4);
+	aice_execute_dim(coreid, instructions, 4);
 
-	aice_read_dtr(current_target_id, data);
+	aice_read_dtr(coreid, data);
 
 	return ERROR_OK;
 }
 
-static int aice_usb_set_address_dim(uint32_t address)
+static int aice_usb_set_address_dim(uint32_t coreid, uint32_t address)
 {
 	uint32_t instructions[4] = {
 		SETHI(R0, address >> 12),
@@ -3006,17 +3058,17 @@ static int aice_usb_set_address_dim(uint32_t address)
 		BEQ_MINUS_12
 	};
 
-	return aice_execute_dim(instructions, 4);
+	return aice_execute_dim(coreid, instructions, 4);
 }
 
-static int aice_usb_read_memory_unit(uint32_t addr, uint32_t size,
+static int aice_usb_read_memory_unit(uint32_t coreid, uint32_t addr, uint32_t size,
 		uint32_t count, uint8_t *buffer)
 {
 	LOG_DEBUG("aice_usb_read_memory_unit, addr: 0x%08x, size: %d, count: %d",
 			addr, size, count);
 
-	if (NDS_MEMORY_ACC_CPU == access_channel)
-		aice_usb_set_address_dim(addr);
+	if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel)
+		aice_usb_set_address_dim(coreid, addr);
 
 	uint32_t value;
 	size_t i;
@@ -3024,25 +3076,25 @@ static int aice_usb_read_memory_unit(uint32_t addr, uint32_t size,
 
 	switch (size) {
 		case 1:
-			if (NDS_MEMORY_ACC_BUS == access_channel)
+			if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel)
 				read_mem_func = aice_usb_read_mem_b_bus;
 			else
 				read_mem_func = aice_usb_read_mem_b_dim;
 
 			for (i = 0; i < count; i++) {
-				read_mem_func(addr, &value);
+				read_mem_func(coreid, addr, &value);
 				*buffer++ = (uint8_t)value;
 				addr++;
 			}
 			break;
 		case 2:
-			if (NDS_MEMORY_ACC_BUS == access_channel)
+			if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel)
 				read_mem_func = aice_usb_read_mem_h_bus;
 			else
 				read_mem_func = aice_usb_read_mem_h_dim;
 
 			for (i = 0; i < count; i++) {
-				read_mem_func(addr, &value);
+				read_mem_func(coreid, addr, &value);
 				uint16_t svalue = value;
 				memcpy(buffer, &svalue, sizeof(uint16_t));
 				buffer += 2;
@@ -3050,13 +3102,13 @@ static int aice_usb_read_memory_unit(uint32_t addr, uint32_t size,
 			}
 			break;
 		case 4:
-			if (NDS_MEMORY_ACC_BUS == access_channel)
+			if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel)
 				read_mem_func = aice_usb_read_mem_w_bus;
 			else
 				read_mem_func = aice_usb_read_mem_w_dim;
 
 			for (i = 0; i < count; i++) {
-				read_mem_func(addr, &value);
+				read_mem_func(coreid, addr, &value);
 				memcpy(buffer, &value, sizeof(uint32_t));
 				buffer += 4;
 				addr += 4;
@@ -3067,22 +3119,22 @@ static int aice_usb_read_memory_unit(uint32_t addr, uint32_t size,
 	return ERROR_OK;
 }
 
-static int aice_usb_write_mem_b_bus(uint32_t address, uint32_t data)
+static int aice_usb_write_mem_b_bus(uint32_t coreid, uint32_t address, uint32_t data)
 {
-	return aice_write_mem_b(current_target_id, address, data);
+	return aice_write_mem_b(coreid, address, data);
 }
 
-static int aice_usb_write_mem_h_bus(uint32_t address, uint32_t data)
+static int aice_usb_write_mem_h_bus(uint32_t coreid, uint32_t address, uint32_t data)
 {
-	return aice_write_mem_h(current_target_id, address, data);
+	return aice_write_mem_h(coreid, address, data);
 }
 
-static int aice_usb_write_mem_w_bus(uint32_t address, uint32_t data)
+static int aice_usb_write_mem_w_bus(uint32_t coreid, uint32_t address, uint32_t data)
 {
-	return aice_write_mem(current_target_id, address, data);
+	return aice_write_mem(coreid, address, data);
 }
 
-static int aice_usb_write_mem_b_dim(uint32_t address, uint32_t data)
+static int aice_usb_write_mem_b_dim(uint32_t coreid, uint32_t address, uint32_t data)
 {
 	uint32_t instructions[4] = {
 		MFSR_DTR(R1),
@@ -3091,13 +3143,13 @@ static int aice_usb_write_mem_b_dim(uint32_t address, uint32_t data)
 		BEQ_MINUS_12
 	};
 
-	aice_write_dtr(current_target_id, data & 0xFF);
-	aice_execute_dim(instructions, 4);
+	aice_write_dtr(coreid, data & 0xFF);
+	aice_execute_dim(coreid, instructions, 4);
 
 	return ERROR_OK;
 }
 
-static int aice_usb_write_mem_h_dim(uint32_t address, uint32_t data)
+static int aice_usb_write_mem_h_dim(uint32_t coreid, uint32_t address, uint32_t data)
 {
 	uint32_t instructions[4] = {
 		MFSR_DTR(R1),
@@ -3106,13 +3158,13 @@ static int aice_usb_write_mem_h_dim(uint32_t address, uint32_t data)
 		BEQ_MINUS_12
 	};
 
-	aice_write_dtr(current_target_id, data & 0xFFFF);
-	aice_execute_dim(instructions, 4);
+	aice_write_dtr(coreid, data & 0xFFFF);
+	aice_execute_dim(coreid, instructions, 4);
 
 	return ERROR_OK;
 }
 
-static int aice_usb_write_mem_w_dim(uint32_t address, uint32_t data)
+static int aice_usb_write_mem_w_dim(uint32_t coreid, uint32_t address, uint32_t data)
 {
 	uint32_t instructions[4] = {
 		MFSR_DTR(R1),
@@ -3121,39 +3173,39 @@ static int aice_usb_write_mem_w_dim(uint32_t address, uint32_t data)
 		BEQ_MINUS_12
 	};
 
-	aice_write_dtr(current_target_id, data);
-	aice_execute_dim(instructions, 4);
+	aice_write_dtr(coreid, data);
+	aice_execute_dim(coreid, instructions, 4);
 
 	return ERROR_OK;
 }
 
-static int aice_usb_write_memory_unit(uint32_t addr, uint32_t size,
+static int aice_usb_write_memory_unit(uint32_t coreid, uint32_t addr, uint32_t size,
 		uint32_t count, const uint8_t *buffer)
 {
 	LOG_DEBUG("aice_usb_write_memory_unit, addr: 0x%08x, size: %d, count: %d",
 			addr, size, count);
 
-	if (NDS_MEMORY_ACC_CPU == access_channel)
-		aice_usb_set_address_dim(addr);
+	if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel)
+		aice_usb_set_address_dim(coreid, addr);
 
 	size_t i;
 	write_mem_func_t write_mem_func;
 
 	switch (size) {
 		case 1:
-			if (NDS_MEMORY_ACC_BUS == access_channel)
+			if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel)
 				write_mem_func = aice_usb_write_mem_b_bus;
 			else
 				write_mem_func = aice_usb_write_mem_b_dim;
 
 			for (i = 0; i < count; i++) {
-				write_mem_func(addr, *buffer);
+				write_mem_func(coreid, addr, *buffer);
 				buffer++;
 				addr++;
 			}
 			break;
 		case 2:
-			if (NDS_MEMORY_ACC_BUS == access_channel)
+			if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel)
 				write_mem_func = aice_usb_write_mem_h_bus;
 			else
 				write_mem_func = aice_usb_write_mem_h_dim;
@@ -3162,13 +3214,13 @@ static int aice_usb_write_memory_unit(uint32_t addr, uint32_t size,
 				uint16_t value;
 				memcpy(&value, buffer, sizeof(uint16_t));
 
-				write_mem_func(addr, value);
+				write_mem_func(coreid, addr, value);
 				buffer += 2;
 				addr += 2;
 			}
 			break;
 		case 4:
-			if (NDS_MEMORY_ACC_BUS == access_channel)
+			if (NDS_MEMORY_ACC_BUS == core_info[coreid].access_channel)
 				write_mem_func = aice_usb_write_mem_w_bus;
 			else
 				write_mem_func = aice_usb_write_mem_w_dim;
@@ -3177,7 +3229,7 @@ static int aice_usb_write_memory_unit(uint32_t addr, uint32_t size,
 				uint32_t value;
 				memcpy(&value, buffer, sizeof(uint32_t));
 
-				write_mem_func(addr, value);
+				write_mem_func(coreid, addr, value);
 				buffer += 4;
 				addr += 4;
 			}
@@ -3187,7 +3239,8 @@ static int aice_usb_write_memory_unit(uint32_t addr, uint32_t size,
 	return ERROR_OK;
 }
 
-static int aice_bulk_read_mem(uint32_t addr, uint32_t count, uint8_t *buffer)
+static int aice_bulk_read_mem(uint32_t coreid, uint32_t addr, uint32_t count,
+		uint8_t *buffer)
 {
 	uint32_t packet_size;
 
@@ -3196,10 +3249,10 @@ static int aice_bulk_read_mem(uint32_t addr, uint32_t count, uint8_t *buffer)
 
 		/** set address */
 		addr &= 0xFFFFFFFC;
-		if (aice_write_misc(current_target_id, NDS_EDM_MISC_SBAR, addr) != ERROR_OK)
+		if (aice_write_misc(coreid, NDS_EDM_MISC_SBAR, addr) != ERROR_OK)
 			return ERROR_FAIL;
 
-		if (aice_fastread_mem(current_target_id, buffer,
+		if (aice_fastread_mem(coreid, buffer,
 					packet_size) != ERROR_OK)
 			return ERROR_FAIL;
 
@@ -3211,7 +3264,8 @@ static int aice_bulk_read_mem(uint32_t addr, uint32_t count, uint8_t *buffer)
 	return ERROR_OK;
 }
 
-static int aice_bulk_write_mem(uint32_t addr, uint32_t count, const uint8_t *buffer)
+static int aice_bulk_write_mem(uint32_t coreid, uint32_t addr, uint32_t count,
+		const uint8_t *buffer)
 {
 	uint32_t packet_size;
 
@@ -3220,10 +3274,10 @@ static int aice_bulk_write_mem(uint32_t addr, uint32_t count, const uint8_t *buf
 
 		/** set address */
 		addr &= 0xFFFFFFFC;
-		if (aice_write_misc(current_target_id, NDS_EDM_MISC_SBAR, addr | 1) != ERROR_OK)
+		if (aice_write_misc(coreid, NDS_EDM_MISC_SBAR, addr | 1) != ERROR_OK)
 			return ERROR_FAIL;
 
-		if (aice_fastwrite_mem(current_target_id, buffer,
+		if (aice_fastwrite_mem(coreid, buffer,
 					packet_size) != ERROR_OK)
 			return ERROR_FAIL;
 
@@ -3235,109 +3289,105 @@ static int aice_bulk_write_mem(uint32_t addr, uint32_t count, const uint8_t *buf
 	return ERROR_OK;
 }
 
-static int aice_usb_bulk_read_mem(uint32_t addr, uint32_t length, uint8_t *buffer)
+static int aice_usb_bulk_read_mem(uint32_t coreid, uint32_t addr,
+		uint32_t length, uint8_t *buffer)
 {
 	LOG_DEBUG("aice_usb_bulk_read_mem, addr: 0x%08x, length: 0x%08x", addr, length);
 
 	int retval;
 
-	if (NDS_MEMORY_ACC_CPU == access_channel)
-		aice_usb_set_address_dim(addr);
+	if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel)
+		aice_usb_set_address_dim(coreid, addr);
 
-	if (NDS_MEMORY_ACC_CPU == access_channel)
-		retval = aice_usb_read_memory_unit(addr, 4, length / 4, buffer);
+	if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel)
+		retval = aice_usb_read_memory_unit(coreid, addr, 4, length / 4, buffer);
 	else
-		retval = aice_bulk_read_mem(addr, length / 4, buffer);
+		retval = aice_bulk_read_mem(coreid, addr, length / 4, buffer);
 
 	return retval;
 }
 
-static int aice_usb_bulk_write_mem(uint32_t addr, uint32_t length, const uint8_t *buffer)
+static int aice_usb_bulk_write_mem(uint32_t coreid, uint32_t addr,
+		uint32_t length, const uint8_t *buffer)
 {
 	LOG_DEBUG("aice_usb_bulk_write_mem, addr: 0x%08x, length: 0x%08x", addr, length);
 
 	int retval;
 
-	if (NDS_MEMORY_ACC_CPU == access_channel)
-		aice_usb_set_address_dim(addr);
+	if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel)
+		aice_usb_set_address_dim(coreid, addr);
 
-	if (NDS_MEMORY_ACC_CPU == access_channel)
-		retval = aice_usb_write_memory_unit(addr, 4, length / 4, buffer);
+	if (NDS_MEMORY_ACC_CPU == core_info[coreid].access_channel)
+		retval = aice_usb_write_memory_unit(coreid, addr, 4, length / 4, buffer);
 	else
-		retval = aice_bulk_write_mem(addr, length / 4, buffer);
+		retval = aice_bulk_write_mem(coreid, addr, length / 4, buffer);
 
 	return retval;
 }
 
-static int aice_usb_read_debug_reg(uint32_t addr, uint32_t *val)
+static int aice_usb_read_debug_reg(uint32_t coreid, uint32_t addr, uint32_t *val)
 {
-	if (AICE_TARGET_HALTED == core_state) {
+	if (AICE_TARGET_HALTED == core_info[coreid].core_state) {
 		if (NDS_EDM_SR_EDMSW == addr) {
-			*val = edmsw_backup;
+			*val = core_info[coreid].edmsw_backup;
 		} else if (NDS_EDM_SR_EDM_DTR == addr) {
-			if (target_dtr_valid) {
+			if (core_info[coreid].target_dtr_valid) {
 				/* if EDM_DTR has read out, clear it. */
-				*val = target_dtr_backup;
-				edmsw_backup &= (~0x1);
-				target_dtr_valid = false;
+				*val = core_info[coreid].target_dtr_backup;
+				core_info[coreid].edmsw_backup &= (~0x1);
+				core_info[coreid].target_dtr_valid = false;
 			} else {
 				*val = 0;
 			}
 		}
 	}
 
-	return aice_read_edmsr(current_target_id, addr, val);
+	return aice_read_edmsr(coreid, addr, val);
 }
 
-static int aice_usb_write_debug_reg(uint32_t addr, const uint32_t val)
+static int aice_usb_write_debug_reg(uint32_t coreid, uint32_t addr, const uint32_t val)
 {
-	if (AICE_TARGET_HALTED == core_state) {
+	if (AICE_TARGET_HALTED == core_info[coreid].core_state) {
 		if (NDS_EDM_SR_EDM_DTR == addr) {
-			host_dtr_backup = val;
-			edmsw_backup |= 0x2;
-			host_dtr_valid = true;
+			core_info[coreid].host_dtr_backup = val;
+			core_info[coreid].edmsw_backup |= 0x2;
+			core_info[coreid].host_dtr_valid = true;
 		}
 	}
 
-	return aice_write_edmsr(current_target_id, addr, val);
+	return aice_write_edmsr(coreid, addr, val);
 }
 
-static int aice_usb_select_target(uint32_t target_id)
-{
-	current_target_id = target_id;
-
-	return ERROR_OK;
-}
-
-static int aice_usb_memory_access(enum nds_memory_access channel)
+static int aice_usb_memory_access(uint32_t coreid, enum nds_memory_access channel)
 {
 	LOG_DEBUG("aice_usb_memory_access, access channel: %d", channel);
 
-	access_channel = channel;
+	core_info[coreid].access_channel = channel;
 
 	return ERROR_OK;
 }
 
-static int aice_usb_memory_mode(enum nds_memory_select mem_select)
+static int aice_usb_memory_mode(uint32_t coreid, enum nds_memory_select mem_select)
 {
-	if (memory_select == mem_select)
+	if (core_info[coreid].memory_select == mem_select)
 		return ERROR_OK;
 
 	LOG_DEBUG("aice_usb_memory_mode, memory select: %d", mem_select);
 
-	memory_select = mem_select;
+	core_info[coreid].memory_select = mem_select;
 
-	if (NDS_MEMORY_SELECT_AUTO != memory_select)
-		aice_write_misc(current_target_id, NDS_EDM_MISC_ACC_CTL,
-				memory_select - 1);
+	if (NDS_MEMORY_SELECT_AUTO != core_info[coreid].memory_select)
+		aice_write_misc(coreid, NDS_EDM_MISC_ACC_CTL,
+				core_info[coreid].memory_select - 1);
 	else
-		aice_write_misc(current_target_id, NDS_EDM_MISC_ACC_CTL,
+		aice_write_misc(coreid, NDS_EDM_MISC_ACC_CTL,
 				NDS_MEMORY_SELECT_MEM - 1);
 
 	return ERROR_OK;
 }
 
-static int aice_usb_read_tlb(uint32_t virtual_address, uint32_t *physical_address)
+static int aice_usb_read_tlb(uint32_t coreid, uint32_t virtual_address,
+		uint32_t *physical_address)
 {
 	LOG_DEBUG("aice_usb_read_tlb, virtual address: 0x%08x", virtual_address);
 
@@ -3349,33 +3399,33 @@ static int aice_usb_read_tlb(uint32_t virtual_address, uint32_t *physical_addres
 	uint32_t virtual_offset;
 	uint32_t physical_page_number;
 
-	aice_write_dtr(current_target_id, virtual_address);
+	aice_write_dtr(coreid, virtual_address);
 
 	/* probe TLB first */
 	instructions[0] = MFSR_DTR(R0);
 	instructions[1] = TLBOP_TARGET_PROBE(R1, R0);
 	instructions[2] = DSB;
 	instructions[3] = BEQ_MINUS_12;
-	aice_execute_dim(instructions, 4);
+	aice_execute_dim(coreid, instructions, 4);
 
-	aice_read_reg(R1, &probe_result);
+	aice_read_reg(coreid, R1, &probe_result);
 
 	if (probe_result & 0x80000000)
 		return ERROR_FAIL;
 
 	/* read TLB entry */
-	aice_write_dtr(current_target_id, probe_result & 0x7FF);
+	aice_write_dtr(coreid, probe_result & 0x7FF);
 
 	/* probe TLB first */
 	instructions[0] = MFSR_DTR(R0);
 	instructions[1] = TLBOP_TARGET_READ(R0);
 	instructions[2] = DSB;
 	instructions[3] = BEQ_MINUS_12;
-	aice_execute_dim(instructions, 4);
+	aice_execute_dim(coreid, instructions, 4);
 
 	/* TODO: it should backup mr3, mr4 */
-	aice_read_reg(MR3, &value_mr3);
-	aice_read_reg(MR4, &value_mr4);
+	aice_read_reg(coreid, MR3, &value_mr3);
+	aice_read_reg(coreid, MR4, &value_mr4);
 
 	access_page_size = value_mr4 & 0xF;
 	if (0 == access_page_size) { /* 4K page */
@@ -3396,56 +3446,60 @@ static int aice_usb_read_tlb(uint32_t virtual_address, uint32_t *physical_addres
 	return ERROR_OK;
 }
 
-static int aice_usb_init_cache(void)
+static int aice_usb_init_cache(uint32_t coreid)
 {
 	LOG_DEBUG("aice_usb_init_cache");
 
 	uint32_t value_cr1;
 	uint32_t value_cr2;
 
-	aice_read_reg(CR1, &value_cr1);
-	aice_read_reg(CR2, &value_cr2);
-
-	icache.set = value_cr1 & 0x7;
-	icache.log2_set = icache.set + 6;
-	icache.set = 64 << icache.set;
-	icache.way = ((value_cr1 >> 3) & 0x7) + 1;
-	icache.line_size = (value_cr1 >> 6) & 0x7;
-	if (icache.line_size != 0) {
-		icache.log2_line_size = icache.line_size + 2;
-		icache.line_size = 8 << (icache.line_size - 1);
+	aice_read_reg(coreid, CR1, &value_cr1);
+	aice_read_reg(coreid, CR2, &value_cr2);
+
+	struct cache_info *icache = &core_info[coreid].icache;
+
+	icache->set = value_cr1 & 0x7;
+	icache->log2_set = icache->set + 6;
+	icache->set = 64 << icache->set;
+	icache->way = ((value_cr1 >> 3) & 0x7) + 1;
+	icache->line_size = (value_cr1 >> 6) & 0x7;
+	if (icache->line_size != 0) {
+		icache->log2_line_size = icache->line_size + 2;
+		icache->line_size = 8 << (icache->line_size - 1);
 	} else {
-		icache.log2_line_size = 0;
+		icache->log2_line_size = 0;
 	}
 
 	LOG_DEBUG("\ticache set: %d, way: %d, line size: %d, "
 			"log2(set): %d, log2(line_size): %d",
-			icache.set, icache.way, icache.line_size,
-			icache.log2_set, icache.log2_line_size);
-
-	dcache.set = value_cr2 & 0x7;
-	dcache.log2_set = dcache.set + 6;
-	dcache.set = 64 << dcache.set;
-	dcache.way = ((value_cr2 >> 3) & 0x7) + 1;
-	dcache.line_size = (value_cr2 >> 6) & 0x7;
-	if (dcache.line_size != 0) {
-		dcache.log2_line_size = dcache.line_size + 2;
-		dcache.line_size = 8 << (dcache.line_size - 1);
+			icache->set, icache->way, icache->line_size,
+			icache->log2_set, icache->log2_line_size);
+
+	struct cache_info *dcache = &core_info[coreid].dcache;
+
+	dcache->set = value_cr2 & 0x7;
+	dcache->log2_set = dcache->set + 6;
+	dcache->set = 64 << dcache->set;
+	dcache->way = ((value_cr2 >> 3) & 0x7) + 1;
+	dcache->line_size = (value_cr2 >> 6) & 0x7;
+	if (dcache->line_size != 0) {
+		dcache->log2_line_size = dcache->line_size + 2;
+		dcache->line_size = 8 << (dcache->line_size - 1);
 	} else {
-		dcache.log2_line_size = 0;
+		dcache->log2_line_size = 0;
 	}
 
 	LOG_DEBUG("\tdcache set: %d, way: %d, line size: %d, "
 			"log2(set): %d, log2(line_size): %d",
-			dcache.set, dcache.way, dcache.line_size,
-			dcache.log2_set, dcache.log2_line_size);
+			dcache->set, dcache->way, dcache->line_size,
+			dcache->log2_set, dcache->log2_line_size);
 
-	cache_init = true;
+	core_info[coreid].cache_init = true;
 
 	return ERROR_OK;
 }
 
-static int aice_usb_dcache_inval_all(void)
+static int aice_usb_dcache_inval_all(uint32_t coreid)
 {
 	LOG_DEBUG("aice_usb_dcache_inval_all");
 
@@ -3459,15 +3513,17 @@ static int aice_usb_dcache_inval_all(void)
 	instructions[2] = DSB;
 	instructions[3] = BEQ_MINUS_12;
 
-	for (set_index = 0; set_index < dcache.set; set_index++) {
-		for (way_index = 0; way_index < dcache.way; way_index++) {
-			cache_index = (way_index << (dcache.log2_set + dcache.log2_line_size)) |
-				(set_index << dcache.log2_line_size);
+	struct cache_info *dcache = &core_info[coreid].dcache;
+
+	for (set_index = 0; set_index < dcache->set; set_index++) {
+		for (way_index = 0; way_index < dcache->way; way_index++) {
+			cache_index = (way_index << (dcache->log2_set + dcache->log2_line_size)) |
+				(set_index << dcache->log2_line_size);
 
-			if (ERROR_OK != aice_write_dtr(current_target_id, cache_index))
+			if (ERROR_OK != aice_write_dtr(coreid, cache_index))
 				return ERROR_FAIL;
 
-			if (ERROR_OK != aice_execute_dim(instructions, 4))
+			if (ERROR_OK != aice_execute_dim(coreid, instructions, 4))
 				return ERROR_FAIL;
 		}
 	}
@@ -3475,23 +3531,23 @@ static int aice_usb_dcache_inval_all(void)
 	return ERROR_OK;
 }
 
-static int aice_usb_dcache_va_inval(uint32_t address)
+static int aice_usb_dcache_va_inval(uint32_t coreid, uint32_t address)
 {
 	LOG_DEBUG("aice_usb_dcache_va_inval");
 
 	uint32_t instructions[4];
 
-	aice_write_dtr(current_target_id, address);
+	aice_write_dtr(coreid, address);
 
 	instructions[0] = MFSR_DTR(R0);
 	instructions[1] = L1D_VA_INVAL(R0);
 	instructions[2] = DSB;
 	instructions[3] = BEQ_MINUS_12;
 
-	return aice_execute_dim(instructions, 4);
+	return aice_execute_dim(coreid, instructions, 4);
 }
 
-static int aice_usb_dcache_wb_all(void)
+static int aice_usb_dcache_wb_all(uint32_t coreid)
 {
 	LOG_DEBUG("aice_usb_dcache_wb_all");
 
@@ -3505,15 +3561,17 @@ static int aice_usb_dcache_wb_all(void)
 	instructions[2] = DSB;
 	instructions[3] = BEQ_MINUS_12;
 
-	for (set_index = 0; set_index < dcache.set; set_index++) {
-		for (way_index = 0; way_index < dcache.way; way_index++) {
-			cache_index = (way_index << (dcache.log2_set + dcache.log2_line_size)) |
-				(set_index << dcache.log2_line_size);
+	struct cache_info *dcache = &core_info[coreid].dcache;
+
+	for (set_index = 0; set_index < dcache->set; set_index++) {
+		for (way_index = 0; way_index < dcache->way; way_index++) {
+			cache_index = (way_index << (dcache->log2_set + dcache->log2_line_size)) |
+				(set_index << dcache->log2_line_size);
 
-			if (ERROR_OK != aice_write_dtr(current_target_id, cache_index))
+			if (ERROR_OK != aice_write_dtr(coreid, cache_index))
 				return ERROR_FAIL;
 
-			if (ERROR_OK != aice_execute_dim(instructions, 4))
+			if (ERROR_OK != aice_execute_dim(coreid, instructions, 4))
 				return ERROR_FAIL;
 		}
 	}
@@ -3521,23 +3579,23 @@ static int aice_usb_dcache_wb_all(void)
 	return ERROR_OK;
 }
 
-static int aice_usb_dcache_va_wb(uint32_t address)
+static int aice_usb_dcache_va_wb(uint32_t coreid, uint32_t address)
 {
 	LOG_DEBUG("aice_usb_dcache_va_wb");
 
 	uint32_t instructions[4];
 
-	aice_write_dtr(current_target_id, address);
+	aice_write_dtr(coreid, address);
 
 	instructions[0] = MFSR_DTR(R0);
 	instructions[1] = L1D_VA_WB(R0);
 	instructions[2] = DSB;
 	instructions[3] = BEQ_MINUS_12;
 
-	return aice_execute_dim(instructions, 4);
+	return aice_execute_dim(coreid, instructions, 4);
 }
 
-static int aice_usb_icache_inval_all(void)
+static int aice_usb_icache_inval_all(uint32_t coreid)
 {
 	LOG_DEBUG("aice_usb_icache_inval_all");
 
@@ -3551,15 +3609,17 @@ static int aice_usb_icache_inval_all(void)
 	instructions[2] = ISB;
 	instructions[3] = BEQ_MINUS_12;
 
-	for (set_index = 0; set_index < icache.set; set_index++) {
-		for (way_index = 0; way_index < icache.way; way_index++) {
-			cache_index = (way_index << (icache.log2_set + icache.log2_line_size)) |
-				(set_index << icache.log2_line_size);
+	struct cache_info *icache = &core_info[coreid].icache;
 
-			if (ERROR_OK != aice_write_dtr(current_target_id, cache_index))
+	for (set_index = 0; set_index < icache->set; set_index++) {
+		for (way_index = 0; way_index < icache->way; way_index++) {
+			cache_index = (way_index << (icache->log2_set + icache->log2_line_size)) |
+				(set_index << icache->log2_line_size);
+
+			if (ERROR_OK != aice_write_dtr(coreid, cache_index))
 				return ERROR_FAIL;
 
-			if (ERROR_OK != aice_execute_dim(instructions, 4))
+			if (ERROR_OK != aice_execute_dim(coreid, instructions, 4))
 				return ERROR_FAIL;
 		}
 	}
@@ -3567,49 +3627,49 @@ static int aice_usb_icache_inval_all(void)
 	return ERROR_OK;
 }
 
-static int aice_usb_icache_va_inval(uint32_t address)
+static int aice_usb_icache_va_inval(uint32_t coreid, uint32_t address)
 {
 	LOG_DEBUG("aice_usb_icache_va_inval");
 
 	uint32_t instructions[4];
 
-	aice_write_dtr(current_target_id, address);
+	aice_write_dtr(coreid, address);
 
 	instructions[0] = MFSR_DTR(R0);
 	instructions[1] = L1I_VA_INVAL(R0);
 	instructions[2] = ISB;
 	instructions[3] = BEQ_MINUS_12;
 
-	return aice_execute_dim(instructions, 4);
+	return aice_execute_dim(coreid, instructions, 4);
 }
 
-static int aice_usb_cache_ctl(uint32_t subtype, uint32_t address)
+static int aice_usb_cache_ctl(uint32_t coreid, uint32_t subtype, uint32_t address)
 {
 	LOG_DEBUG("aice_usb_cache_ctl");
 
 	int result;
 
-	if (cache_init == false)
-		aice_usb_init_cache();
+	if (core_info[coreid].cache_init == false)
+		aice_usb_init_cache(coreid);
 
 	switch (subtype) {
 		case AICE_CACHE_CTL_L1D_INVALALL:
-			result = aice_usb_dcache_inval_all();
+			result = aice_usb_dcache_inval_all(coreid);
 			break;
 		case AICE_CACHE_CTL_L1D_VA_INVAL:
-			result = aice_usb_dcache_va_inval(address);
+			result = aice_usb_dcache_va_inval(coreid, address);
 			break;
 		case AICE_CACHE_CTL_L1D_WBALL:
-			result = aice_usb_dcache_wb_all();
+			result = aice_usb_dcache_wb_all(coreid);
 			break;
 		case AICE_CACHE_CTL_L1D_VA_WB:
-			result = aice_usb_dcache_va_wb(address);
+			result = aice_usb_dcache_va_wb(coreid, address);
 			break;
 		case AICE_CACHE_CTL_L1I_INVALALL:
-			result = aice_usb_icache_inval_all();
+			result = aice_usb_icache_inval_all(coreid);
 			break;
 		case AICE_CACHE_CTL_L1I_VA_INVAL:
-			result = aice_usb_icache_va_inval(address);
+			result = aice_usb_icache_va_inval(coreid, address);
 			break;
 		default:
 			result = ERROR_FAIL;
@@ -3625,7 +3685,7 @@ static int aice_usb_set_retry_times(uint32_t a_retry_times)
 	return ERROR_OK;
 }
 
-static int aice_usb_program_edm(char *command_sequence)
+static int aice_usb_program_edm(uint32_t coreid, char *command_sequence)
 {
 	char *command_str;
 	char *reg_name_0;
@@ -3657,14 +3717,14 @@ static int aice_usb_program_edm(char *command_sequence)
 			if (reg_name_0 != NULL) {
 				data_value = strtoul(reg_name_0 + 9, NULL, 0);
 
-				if (aice_write_misc(current_target_id,
+				if (aice_write_misc(coreid,
 							NDS_EDM_MISC_GEN_PORT0, data_value) != ERROR_OK)
 					return ERROR_FAIL;
 
 			} else if (reg_name_1 != NULL) {
 				data_value = strtoul(reg_name_1 + 9, NULL, 0);
 
-				if (aice_write_misc(current_target_id,
+				if (aice_write_misc(coreid,
 							NDS_EDM_MISC_GEN_PORT1, data_value) != ERROR_OK)
 					return ERROR_FAIL;
 			} else {
@@ -3700,7 +3760,8 @@ static int aice_usb_set_command_mode(enum aice_command_mode command_mode)
 	return retval;
 }
 
-static int aice_usb_execute(uint32_t *instructions, uint32_t instruction_num)
+static int aice_usb_execute(uint32_t coreid, uint32_t *instructions,
+		uint32_t instruction_num)
 {
 	uint32_t i, j;
 	uint8_t current_instruction_num;
@@ -3708,7 +3769,7 @@ static int aice_usb_execute(uint32_t *instructions, uint32_t instruction_num)
 
 	/* To execute 4 instructions as a special case */
 	if (instruction_num == 4)
-		return aice_execute_dim(instructions, 4);
+		return aice_execute_dim(coreid, instructions, 4);
 
 	for (i = 0 ; i < instruction_num ; i += 3) {
 		if (instruction_num - i < 3) {
@@ -3723,22 +3784,22 @@ static int aice_usb_execute(uint32_t *instructions, uint32_t instruction_num)
 				current_instruction_num * sizeof(uint32_t));
 
 		/** fill DIM */
-		if (aice_write_dim(current_target_id,
+		if (aice_write_dim(coreid,
 					dim_instructions,
 					4) != ERROR_OK)
 			return ERROR_FAIL;
 
 		/** clear DBGER.DPED */
-		if (aice_write_misc(current_target_id,
+		if (aice_write_misc(coreid,
 					NDS_EDM_MISC_DBGER, NDS_DBGER_DPED) != ERROR_OK)
 			return ERROR_FAIL;
 
 		/** execute DIM */
-		if (aice_do_execute(current_target_id) != ERROR_OK)
+		if (aice_do_execute(coreid) != ERROR_OK)
 			return ERROR_FAIL;
 
 		/** check DBGER.DPED */
-		if (aice_check_dbger(NDS_DBGER_DPED) != ERROR_OK) {
+		if (aice_check_dbger(coreid, NDS_DBGER_DPED) != ERROR_OK) {
 
 			LOG_ERROR("<-- TARGET ERROR! Debug operations do not finish properly:"
 					"0x%08x 0x%08x 0x%08x 0x%08x. -->",
@@ -3781,21 +3842,22 @@ static int aice_usb_set_count_to_check_dbger(uint32_t count_to_check)
 	return ERROR_OK;
 }
 
-static int aice_usb_set_data_endian(enum aice_target_endian target_data_endian)
+static int aice_usb_set_data_endian(uint32_t coreid,
+		enum aice_target_endian target_data_endian)
 {
 	data_endian = target_data_endian;
 
 	return ERROR_OK;
 }
 
-static int fill_profiling_batch_commands(uint32_t reg_no)
+static int fill_profiling_batch_commands(uint32_t coreid, uint32_t reg_no)
 {
 	uint32_t dim_instructions[4];
 
 	aice_usb_set_command_mode(AICE_COMMAND_MODE_BATCH);
 
 	/* halt */
-	if (aice_write_misc(current_target_id, NDS_EDM_MISC_EDM_CMDR, 0) != ERROR_OK)
+	if (aice_write_misc(coreid, NDS_EDM_MISC_EDM_CMDR, 0) != ERROR_OK)
 		return ERROR_FAIL;
 
 	/* backup $r0 */
@@ -3803,9 +3865,9 @@ static int fill_profiling_batch_commands(uint32_t reg_no)
 	dim_instructions[1] = DSB;
 	dim_instructions[2] = NOP;
 	dim_instructions[3] = BEQ_MINUS_12;
-	if (aice_write_dim(current_target_id, dim_instructions, 4) != ERROR_OK)
+	if (aice_write_dim(coreid, dim_instructions, 4) != ERROR_OK)
 		return ERROR_FAIL;
-	aice_read_dtr_to_buffer(current_target_id, AICE_BATCH_DATA_BUFFER_0);
+	aice_read_dtr_to_buffer(coreid, AICE_BATCH_DATA_BUFFER_0);
 
 	/* get samples */
 	if (NDS32_REG_TYPE_GPR == nds32_reg_type(reg_no)) {
@@ -3826,17 +3888,17 @@ static int fill_profiling_batch_commands(uint32_t reg_no)
 		dim_instructions[2] = DSB;
 		dim_instructions[3] = BEQ_MINUS_12;
 	}
-	if (aice_write_dim(current_target_id, dim_instructions, 4) != ERROR_OK)
+	if (aice_write_dim(coreid, dim_instructions, 4) != ERROR_OK)
 		return ERROR_FAIL;
-	aice_read_dtr_to_buffer(current_target_id, AICE_BATCH_DATA_BUFFER_1);
+	aice_read_dtr_to_buffer(coreid, AICE_BATCH_DATA_BUFFER_1);
 
 	/* restore $r0 */
-	aice_write_dtr_from_buffer(current_target_id, AICE_BATCH_DATA_BUFFER_0);
+	aice_write_dtr_from_buffer(coreid, AICE_BATCH_DATA_BUFFER_0);
 	dim_instructions[0] = MFSR_DTR(0);
 	dim_instructions[1] = DSB;
 	dim_instructions[2] = NOP;
 	dim_instructions[3] = IRET;  /* free run */
-	if (aice_write_dim(current_target_id, dim_instructions, 4) != ERROR_OK)
+	if (aice_write_dim(coreid, dim_instructions, 4) != ERROR_OK)
 		return ERROR_FAIL;
 
 	aice_command_mode = AICE_COMMAND_MODE_NORMAL;
@@ -3853,7 +3915,7 @@ static int fill_profiling_batch_commands(uint32_t reg_no)
 	return ERROR_OK;
 }
 
-static int aice_usb_profiling(uint32_t interval, uint32_t iteration,
+static int aice_usb_profiling(uint32_t coreid, uint32_t interval, uint32_t iteration,
 		uint32_t reg_no, uint32_t *samples, uint32_t *num_samples)
 {
 	uint32_t iteration_count;
@@ -3872,7 +3934,7 @@ static int aice_usb_profiling(uint32_t interval, uint32_t iteration,
 	if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_DATA_BUF0_CTRL, 0xC0000) != ERROR_OK)
 		return ERROR_FAIL;
 
-	fill_profiling_batch_commands(reg_no);
+	fill_profiling_batch_commands(coreid, reg_no);
 
 	iteration_count = 0;
 	while (iteration_count < iteration) {
@@ -3897,12 +3959,12 @@ static int aice_usb_profiling(uint32_t interval, uint32_t iteration,
 			goto end_profiling;
 		}
 
-		aice_usb_run();
+		aice_usb_run(coreid);
 
 		/* enable BATCH command */
 		if (aice_write_ctrl(AICE_WRITE_CTRL_BATCH_CTRL,
 					0x80000000) != ERROR_OK) {
-			aice_usb_halt();
+			aice_usb_halt(coreid);
 			retval = ERROR_FAIL;
 			goto end_profiling;
 		}
@@ -3921,7 +3983,7 @@ static int aice_usb_profiling(uint32_t interval, uint32_t iteration,
 			if (batch_status & 0x1) {
 				break;
 			} else if (batch_status & 0xE) {
-				aice_usb_halt();
+				aice_usb_halt(coreid);
 				retval = ERROR_FAIL;
 				goto end_profiling;
 			}
@@ -3932,7 +3994,7 @@ static int aice_usb_profiling(uint32_t interval, uint32_t iteration,
 			i++;
 		}
 
-		aice_usb_halt();
+		aice_usb_halt(coreid);
 
 		/* get samples from batch data buffer */
 		if (aice_batch_buffer_read(AICE_BATCH_DATA_BUFFER_1,
@@ -3993,8 +4055,6 @@ struct aice_port_api_s aice_usb_api = {
 	/** */
 	.set_jtag_clock = aice_usb_set_jtag_clock,
 	/** */
-	.select_target = aice_usb_select_target,
-	/** */
 	.memory_access = aice_usb_memory_access,
 	/** */
 	.memory_mode = aice_usb_memory_mode,
diff --git a/src/jtag/aice/aice_usb.h b/src/jtag/aice/aice_usb.h
index ad24263..0d133e6 100644
--- a/src/jtag/aice/aice_usb.h
+++ b/src/jtag/aice/aice_usb.h
@@ -156,6 +156,35 @@ struct aice_usb_handler_s {
 	struct jtag_libusb_device_handle *usb_handle;
 };
 
+struct cache_info {
+	uint32_t set;
+	uint32_t way;
+	uint32_t line_size;
+
+	uint32_t log2_set;
+	uint32_t log2_line_size;
+};
+
+struct aice_nds32_info {
+	uint32_t edm_version;
+	uint32_t r0_backup;
+	uint32_t r1_backup;
+	uint32_t host_dtr_backup;
+	uint32_t target_dtr_backup;
+	uint32_t edmsw_backup;
+	uint32_t edm_ctl_backup;
+	bool debug_under_dex_on;
+	bool dex_use_psw_on;
+	bool host_dtr_valid;
+	bool target_dtr_valid;
+	enum nds_memory_access access_channel;
+	enum nds_memory_select memory_select;
+	enum aice_target_state_s core_state;
+	bool cache_init;
+	struct cache_info icache;
+	struct cache_info dcache;
+};
+
 extern struct aice_port_api_s aice_usb_api;
 
 int aice_read_ctrl(uint32_t address, uint32_t *data);
diff --git a/src/target/nds32.c b/src/target/nds32.c
index e09ce6f..4d25649 100644
--- a/src/target/nds32.c
+++ b/src/target/nds32.c
@@ -395,7 +395,7 @@ static const struct reg_arch_type nds32_reg_access_type_64 = {
 static struct reg_cache *nds32_build_reg_cache(struct target *target,
 		struct nds32 *nds32)
 {
-	struct reg_cache *cache = malloc(sizeof(struct reg_cache));
+	struct reg_cache *cache = calloc(sizeof(struct reg_cache), 1);
 	struct reg *reg_list = calloc(TOTAL_REG_NUM, sizeof(struct reg));
 	struct nds32_reg *reg_arch_info = calloc(TOTAL_REG_NUM, sizeof(struct nds32_reg));
 	int i;
@@ -423,7 +423,7 @@ static struct reg_cache *nds32_build_reg_cache(struct target *target,
 		reg_list[i].size = nds32_reg_size(i);
 		reg_list[i].arch_info = &reg_arch_info[i];
 
-		reg_list[i].reg_data_type = malloc(sizeof(struct reg_data_type));
+		reg_list[i].reg_data_type = calloc(sizeof(struct reg_data_type), 1);
 
 		if (FD0 <= reg_arch_info[i].num && reg_arch_info[i].num <= FD31) {
 			reg_list[i].value = &(reg_arch_info[i].value_64);
@@ -1649,6 +1649,15 @@ int nds32_init_arch_info(struct target *target, struct nds32 *nds32)
 	nds32->active_syscall_id = NDS32_SYSCALL_UNDEFINED;
 	nds32->virtual_hosting_errno = 0;
 	nds32->virtual_hosting_ctrl_c = false;
+	nds32->attached = false;
+
+	nds32->syscall_break.asid = 0;
+	nds32->syscall_break.length = 4;
+	nds32->syscall_break.set = 0;
+	nds32->syscall_break.orig_instr = NULL;
+	nds32->syscall_break.next = NULL;
+	nds32->syscall_break.unique_id = 0x515CAll + target->target_number;
+	nds32->syscall_break.linked_BRP = 0;
 
 	nds32_reg_init();
 
@@ -2187,27 +2196,21 @@ int nds32_assert_reset(struct target *target)
 	return ERROR_OK;
 }
 
-static uint32_t nds32_backup_edm_ctl;
-static bool gdb_attached;
-
 static int nds32_gdb_attach(struct nds32 *nds32)
 {
-	LOG_DEBUG("nds32_gdb_attach");
+	LOG_DEBUG("nds32_gdb_attach, target coreid: %d", nds32->target->coreid);
 
-	if (gdb_attached == false) {
+	if (nds32->attached == false) {
 
 		if (nds32->keep_target_edm_ctl) {
 			/* backup target EDM_CTL */
 			struct aice_port_s *aice = target_to_aice(nds32->target);
-			aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &nds32_backup_edm_ctl);
+			aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &nds32->backup_edm_ctl);
 		}
 
 		target_halt(nds32->target);
 
-		/* turn on polling */
-		jtag_poll_set_enabled(true);
-
-		gdb_attached = true;
+		nds32->attached = true;
 	}
 
 	return ERROR_OK;
@@ -2218,7 +2221,7 @@ static int nds32_gdb_detach(struct nds32 *nds32)
 	LOG_DEBUG("nds32_gdb_detach");
 	bool backup_virtual_hosting_setting;
 
-	if (gdb_attached) {
+	if (nds32->attached) {
 
 		backup_virtual_hosting_setting = nds32->virtual_hosting;
 		/* turn off virtual hosting before resume as gdb-detach */
@@ -2229,13 +2232,10 @@ static int nds32_gdb_detach(struct nds32 *nds32)
 		if (nds32->keep_target_edm_ctl) {
 			/* restore target EDM_CTL */
 			struct aice_port_s *aice = target_to_aice(nds32->target);
-			aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, nds32_backup_edm_ctl);
+			aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, nds32->backup_edm_ctl);
 		}
 
-		/* turn off polling */
-		jtag_poll_set_enabled(false);
-
-		gdb_attached = false;
+		nds32->attached = false;
 	}
 
 	return ERROR_OK;
@@ -2245,7 +2245,12 @@ static int nds32_callback_event_handler(struct target *target,
 		enum target_event event, void *priv)
 {
 	int retval = ERROR_OK;
-	struct nds32 *nds32 = priv;
+	int target_number = *(int *)priv;
+
+	if (target_number != target->target_number)
+		return ERROR_OK;
+
+	struct nds32 *nds32 = target_to_nds32(target);
 
 	switch (event) {
 		case TARGET_EVENT_GDB_ATTACH:
@@ -2266,11 +2271,9 @@ int nds32_init(struct nds32 *nds32)
 	/* Initialize anything we can set up without talking to the target */
 	nds32->memory.access_channel = NDS_MEMORY_ACC_CPU;
 
-	/* turn off polling by default */
-	jtag_poll_set_enabled(false);
-
 	/* register event callback */
-	target_register_event_callback(nds32_callback_event_handler, nds32);
+	target_register_event_callback(nds32_callback_event_handler,
+			&(nds32->target->target_number));
 
 	return ERROR_OK;
 }
@@ -2467,7 +2470,7 @@ int nds32_profiling(struct target *target, uint32_t *samples,
 		iteration = max_num_samples;
 
 	int pc_regnum = nds32->register_map(nds32, PC);
-	aice->port->api->profiling(10, iteration, pc_regnum, samples, num_samples);
+	aice_profiling(aice, 10, iteration, pc_regnum, samples, num_samples);
 
 	register_cache_invalidate(nds32->core_cache);
 
diff --git a/src/target/nds32.h b/src/target/nds32.h
index 304fc35..fe5ee00 100644
--- a/src/target/nds32.h
+++ b/src/target/nds32.h
@@ -296,6 +296,8 @@ struct nds32 {
 	/** Record syscall ID for other operations to do special processing for target */
 	int active_syscall_id;
 
+	struct breakpoint syscall_break;
+
 	/** Flag reporting whether global stop is active. */
 	bool global_stop;
 
@@ -309,6 +311,9 @@ struct nds32 {
 	 * handler, it should be true. */
 	bool keep_target_edm_ctl;
 
+	/* Value of $EDM_CTL before target enters debug mode */
+	uint32_t backup_edm_ctl;
+
 	/** always use word-aligned address to access memory */
 	bool word_access_mem;
 
@@ -346,6 +351,9 @@ struct nds32 {
 	 *  hardware breakpoints or not in ROM */
 	bool auto_convert_hw_bp;
 
+	/* Flag to indicate the target is attached by debugger or not */
+	bool attached;
+
 	/** Backpointer to the target. */
 	struct target *target;
 
diff --git a/src/target/nds32_aice.c b/src/target/nds32_aice.c
index b3a830b..cfb6d86 100644
--- a/src/target/nds32_aice.c
+++ b/src/target/nds32_aice.c
@@ -31,7 +31,7 @@ int aice_read_reg_64(struct aice_port_s *aice, uint32_t num, uint64_t *val)
 		return ERROR_FAIL;
 	}
 
-	return aice->port->api->read_reg_64(num, val);
+	return aice->port->api->read_reg_64(aice->coreid, num, val);
 }
 
 int aice_write_reg_64(struct aice_port_s *aice, uint32_t num, uint64_t val)
@@ -41,17 +41,7 @@ int aice_write_reg_64(struct aice_port_s *aice, uint32_t num, uint64_t val)
 		return ERROR_FAIL;
 	}
 
-	return aice->port->api->write_reg_64(num, val);
-}
-
-int aice_select_target(struct aice_port_s *aice, uint32_t target_id)
-{
-	if (aice->port->api->select_target == NULL) {
-		LOG_WARNING("Not implemented: %s", __func__);
-		return ERROR_FAIL;
-	}
-
-	return aice->port->api->select_target(target_id);
+	return aice->port->api->write_reg_64(aice->coreid, num, val);
 }
 
 int aice_read_tlb(struct aice_port_s *aice, uint32_t virtual_address,
@@ -62,7 +52,7 @@ int aice_read_tlb(struct aice_port_s *aice, uint32_t virtual_address,
 		return ERROR_FAIL;
 	}
 
-	return aice->port->api->read_tlb(virtual_address, physical_address);
+	return aice->port->api->read_tlb(aice->coreid, virtual_address, physical_address);
 }
 
 int aice_cache_ctl(struct aice_port_s *aice, uint32_t subtype, uint32_t address)
@@ -72,7 +62,7 @@ int aice_cache_ctl(struct aice_port_s *aice, uint32_t subtype, uint32_t address)
 		return ERROR_FAIL;
 	}
 
-	return aice->port->api->cache_ctl(subtype, address);
+	return aice->port->api->cache_ctl(aice->coreid, subtype, address);
 }
 
 int aice_set_retry_times(struct aice_port_s *aice, uint32_t a_retry_times)
@@ -92,7 +82,7 @@ int aice_program_edm(struct aice_port_s *aice, char *command_sequence)
 		return ERROR_FAIL;
 	}
 
-	return aice->port->api->program_edm(command_sequence);
+	return aice->port->api->program_edm(aice->coreid, command_sequence);
 }
 
 int aice_set_command_mode(struct aice_port_s *aice,
@@ -114,7 +104,7 @@ int aice_execute(struct aice_port_s *aice, uint32_t *instructions,
 		return ERROR_FAIL;
 	}
 
-	return aice->port->api->execute(instructions, instruction_num);
+	return aice->port->api->execute(aice->coreid, instructions, instruction_num);
 }
 
 int aice_set_custom_srst_script(struct aice_port_s *aice, const char *script)
@@ -156,3 +146,15 @@ int aice_set_count_to_check_dbger(struct aice_port_s *aice, uint32_t count_to_ch
 
 	return aice->port->api->set_count_to_check_dbger(count_to_check);
 }
+
+int aice_profiling(struct aice_port_s *aice, uint32_t interval, uint32_t iteration,
+		uint32_t reg_no, uint32_t *samples, uint32_t *num_samples)
+{
+	if (aice->port->api->profiling == NULL) {
+		LOG_WARNING("Not implemented: %s", __func__);
+		return ERROR_FAIL;
+	}
+
+	return aice->port->api->profiling(aice->coreid, interval, iteration,
+			reg_no, samples, num_samples);
+}
diff --git a/src/target/nds32_aice.h b/src/target/nds32_aice.h
index 6c74e69..d535643 100644
--- a/src/target/nds32_aice.h
+++ b/src/target/nds32_aice.h
@@ -24,7 +24,6 @@
 
 int aice_read_reg_64(struct aice_port_s *aice, uint32_t num, uint64_t *val);
 int aice_write_reg_64(struct aice_port_s *aice, uint32_t num, uint64_t val);
-int aice_select_target(struct aice_port_s *aice, uint32_t target_id);
 int aice_read_tlb(struct aice_port_s *aice, uint32_t virtual_address,
 		uint32_t *physical_address);
 int aice_cache_ctl(struct aice_port_s *aice, uint32_t subtype, uint32_t address);
@@ -38,6 +37,8 @@ int aice_set_custom_srst_script(struct aice_port_s *aice, const char *script);
 int aice_set_custom_trst_script(struct aice_port_s *aice, const char *script);
 int aice_set_custom_restart_script(struct aice_port_s *aice, const char *script);
 int aice_set_count_to_check_dbger(struct aice_port_s *aice, uint32_t count_to_check);
+int aice_profiling(struct aice_port_s *aice, uint32_t interval, uint32_t iteration,
+		uint32_t reg_no, uint32_t *samples, uint32_t *num_samples);
 
 static inline int aice_open(struct aice_port_s *aice, struct aice_port_param_s *param)
 {
@@ -57,70 +58,70 @@ static inline int aice_reset(struct aice_port_s *aice)
 static inline int aice_assert_srst(struct aice_port_s *aice,
 		enum aice_srst_type_s srst)
 {
-	return aice->port->api->assert_srst(srst);
+	return aice->port->api->assert_srst(aice->coreid, srst);
 }
 
 static inline int aice_run(struct aice_port_s *aice)
 {
-	return aice->port->api->run();
+	return aice->port->api->run(aice->coreid);
 }
 
 static inline int aice_halt(struct aice_port_s *aice)
 {
-	return aice->port->api->halt();
+	return aice->port->api->halt(aice->coreid);
 }
 
 static inline int aice_step(struct aice_port_s *aice)
 {
-	return aice->port->api->step();
+	return aice->port->api->step(aice->coreid);
 }
 
 static inline int aice_read_register(struct aice_port_s *aice, uint32_t num,
 		uint32_t *val)
 {
-	return aice->port->api->read_reg(num, val);
+	return aice->port->api->read_reg(aice->coreid, num, val);
 }
 
 static inline int aice_write_register(struct aice_port_s *aice, uint32_t num,
 		uint32_t val)
 {
-	return aice->port->api->write_reg(num, val);
+	return aice->port->api->write_reg(aice->coreid, num, val);
 }
 
 static inline int aice_read_debug_reg(struct aice_port_s *aice, uint32_t addr,
 		uint32_t *val)
 {
-	return aice->port->api->read_debug_reg(addr, val);
+	return aice->port->api->read_debug_reg(aice->coreid, addr, val);
 }
 
 static inline int aice_write_debug_reg(struct aice_port_s *aice, uint32_t addr,
 		const uint32_t val)
 {
-	return aice->port->api->write_debug_reg(addr, val);
+	return aice->port->api->write_debug_reg(aice->coreid, addr, val);
 }
 
 static inline int aice_read_mem_unit(struct aice_port_s *aice, uint32_t addr,
 		uint32_t size, uint32_t count, uint8_t *buffer)
 {
-	return aice->port->api->read_mem_unit(addr, size, count, buffer);
+	return aice->port->api->read_mem_unit(aice->coreid, addr, size, count, buffer);
 }
 
 static inline int aice_write_mem_unit(struct aice_port_s *aice, uint32_t addr,
 		uint32_t size, uint32_t count, const uint8_t *buffer)
 {
-	return aice->port->api->write_mem_unit(addr, size, count, buffer);
+	return aice->port->api->write_mem_unit(aice->coreid, addr, size, count, buffer);
 }
 
 static inline int aice_read_mem_bulk(struct aice_port_s *aice, uint32_t addr,
 		uint32_t length, uint8_t *buffer)
 {
-	return aice->port->api->read_mem_bulk(addr, length, buffer);
+	return aice->port->api->read_mem_bulk(aice->coreid, addr, length, buffer);
 }
 
 static inline int aice_write_mem_bulk(struct aice_port_s *aice, uint32_t addr,
 		uint32_t length, const uint8_t *buffer)
 {
-	return aice->port->api->write_mem_bulk(addr, length, buffer);
+	return aice->port->api->write_mem_bulk(aice->coreid, addr, length, buffer);
 }
 
 static inline int aice_idcode(struct aice_port_s *aice, uint32_t *idcode,
@@ -132,7 +133,7 @@ static inline int aice_idcode(struct aice_port_s *aice, uint32_t *idcode,
 static inline int aice_state(struct aice_port_s *aice,
 		enum aice_target_state_s *state)
 {
-	return aice->port->api->state(state);
+	return aice->port->api->state(aice->coreid, state);
 }
 
 static inline int aice_set_jtag_clock(struct aice_port_s *aice, uint32_t a_clock)
@@ -143,19 +144,19 @@ static inline int aice_set_jtag_clock(struct aice_port_s *aice, uint32_t a_clock
 static inline int aice_memory_access(struct aice_port_s *aice,
 		enum nds_memory_access a_access)
 {
-	return aice->port->api->memory_access(a_access);
+	return aice->port->api->memory_access(aice->coreid, a_access);
 }
 
 static inline int aice_memory_mode(struct aice_port_s *aice,
 		enum nds_memory_select mem_select)
 {
-	return aice->port->api->memory_mode(mem_select);
+	return aice->port->api->memory_mode(aice->coreid, mem_select);
 }
 
 static inline int aice_set_data_endian(struct aice_port_s *aice,
 		enum aice_target_endian target_data_endian)
 {
-	return aice->port->api->set_data_endian(target_data_endian);
+	return aice->port->api->set_data_endian(aice->coreid, target_data_endian);
 }
 
 #endif
diff --git a/src/target/nds32_v3_common.c b/src/target/nds32_v3_common.c
index e01025f..3930c25 100644
--- a/src/target/nds32_v3_common.c
+++ b/src/target/nds32_v3_common.c
@@ -29,18 +29,6 @@
 #include "nds32_aice.h"
 #include "nds32_v3_common.h"
 
-static struct breakpoint syscall_breakpoint = {
-	0x80,
-	0,
-	4,
-	BKPT_SOFT,
-	0,
-	NULL,
-	NULL,
-	0x515CA11,
-	0,
-};
-
 static struct nds32_v3_common_callback *v3_common_callback;
 
 static int nds32_v3_register_mapping(struct nds32 *nds32, int reg_no)
@@ -90,17 +78,18 @@ static int nds32_v3_debug_entry(struct nds32 *nds32, bool enable_watchpoint)
 	if (enable_watchpoint)
 		CHECK_RETVAL(v3_common_callback->deactivate_hardware_watchpoint(nds32->target));
 
+	struct breakpoint *syscall_break = &(nds32->syscall_break);
 	if (nds32->virtual_hosting) {
-		if (syscall_breakpoint.set) {
+		if (syscall_break->set) {
 			/** disable virtual hosting */
 
 			/* remove breakpoint at syscall entry */
-			target_remove_breakpoint(nds32->target, &syscall_breakpoint);
-			syscall_breakpoint.set = 0;
+			target_remove_breakpoint(nds32->target, syscall_break);
+			syscall_break->set = 0;
 
 			uint32_t value_pc;
 			nds32_get_mapped_reg(nds32, PC, &value_pc);
-			if (value_pc == syscall_breakpoint.address)
+			if (value_pc == syscall_break->address)
 				/** process syscall for virtual hosting */
 				nds32->hit_syscall = true;
 		}
@@ -218,10 +207,12 @@ static int nds32_v3_leave_debug_state(struct nds32 *nds32, bool enable_watchpoin
 		}
 
 		/* insert breakpoint at syscall entry */
-		syscall_breakpoint.address = syscall_address;
-		syscall_breakpoint.type = BKPT_SOFT;
-		syscall_breakpoint.set = 1;
-		target_add_breakpoint(target, &syscall_breakpoint);
+		struct breakpoint *syscall_break = &(nds32->syscall_break);
+
+		syscall_break->address = syscall_address;
+		syscall_break->type = BKPT_SOFT;
+		syscall_break->set = 1;
+		target_add_breakpoint(target, syscall_break);
 	}
 
 	return ERROR_OK;