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| author | Paul Fertser <fercerpav@gmail.com> | 2016-12-02 20:15:46 +0300 |
|---|---|---|
| committer | Paul Fertser <fercerpav@gmail.com> | 2018-01-13 08:36:29 +0000 |
| commit | 2420aa00a458c6847faca2d6b7f9d99718d693f2 (patch) | |
| tree | 591278fcadadca5467576df49522988b6b45d122 /src | |
| parent | c26bbf7a1b2a11e9cc369536332bff2faa223da8 (diff) | |
| download | riscv-openocd-2420aa00a458c6847faca2d6b7f9d99718d693f2.zip riscv-openocd-2420aa00a458c6847faca2d6b7f9d99718d693f2.tar.gz riscv-openocd-2420aa00a458c6847faca2d6b7f9d99718d693f2.tar.bz2 | |
target: arm: disassembler: decode v6T2 ARM ISB instruction
Change-Id: Iaaa54aee6a74f0b250b83c53e7a3fb7c17718920
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3895
Tested-by: jenkins
Diffstat (limited to 'src')
| -rw-r--r-- | src/target/arm_disassembler.c | 12 | ||||
| -rw-r--r-- | src/target/arm_disassembler.h | 1 |
2 files changed, 13 insertions, 0 deletions
diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c index 1536679..f432f57 100644 --- a/src/target/arm_disassembler.c +++ b/src/target/arm_disassembler.c @@ -170,6 +170,18 @@ static int evaluate_pld(uint32_t opcode, return ERROR_OK; } + /* ISB */ + if ((opcode & 0x07f000f0) == 0x05700060) { + instruction->type = ARM_ISB; + + snprintf(instruction->text, + 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tISB %s", + address, opcode, + ((opcode & 0x0000000f) == 0xf) ? "SY" : "UNK"); + + return ERROR_OK; + } return evaluate_unknown(opcode, address, instruction); } diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h index b73f24a..e9f4d44 100644 --- a/src/target/arm_disassembler.h +++ b/src/target/arm_disassembler.h @@ -107,6 +107,7 @@ enum arm_instruction_type { ARM_MRRC, ARM_PLD, ARM_DSB, + ARM_ISB, ARM_QADD, ARM_QDADD, ARM_QSUB, |