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| author | Tim Newsome <tim@sifive.com> | 2021-05-20 11:50:34 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-05-20 11:50:34 -0700 |
| commit | 19f7b5c43c24977f24059e88477410658b7da466 (patch) | |
| tree | bb0817f9b83184063a21e91597dd037f8916709c /src | |
| parent | e986ec1827ff9191d324c1085e7c61eac2045734 (diff) | |
| download | riscv-openocd-19f7b5c43c24977f24059e88477410658b7da466.zip riscv-openocd-19f7b5c43c24977f24059e88477410658b7da466.tar.gz riscv-openocd-19f7b5c43c24977f24059e88477410658b7da466.tar.bz2 | |
Add keepalive for vector register access. (#611)
(And whatever else does a lot of register writes.)
Change-Id: I86a1a784fb7b9430aa470dbb39a495b89f56d8c9
Signed-off-by: Tim Newsome <tim@sifive.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/target/riscv/riscv-013.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index cfc040c..cb963d8 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1307,6 +1307,8 @@ static int register_write_direct(struct target *target, unsigned number, LOG_DEBUG("{%d} %s <- 0x%" PRIx64, riscv_current_hartid(target), gdb_regno_name(number), value); + keep_alive(); + int result = register_write_abstract(target, number, value, register_size(target, number)); if (result == ERROR_OK || !has_sufficient_progbuf(target, 2) || |