target/arm: opcodes: rename CamelCase symbols and uppercase variables

No major cross dependencies, mostly changes internal to each
file/function.

Change-Id: I1325560ef0350517d86d4927cb17ceaae81b75d2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6340
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Xiang W <wxjstz@126.com>

5 files changed, 708 insertions, 708 deletions

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 9b8c09e..6618593 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -123,36 +123,36 @@ static int evaluate_pld(uint32_t opcode,
 {
 	/* PLD */
 	if ((opcode & 0x0d30f000) == 0x0510f000) {
-		uint8_t Rn;
-		uint8_t U;
+		uint8_t rn;
+		uint8_t u;
 		unsigned offset;
 
 		instruction->type = ARM_PLD;
-		Rn = (opcode & 0xf0000) >> 16;
-		U = (opcode & 0x00800000) >> 23;
-		if (Rn == 0xf) {
+		rn = (opcode & 0xf0000) >> 16;
+		u = (opcode & 0x00800000) >> 23;
+		if (rn == 0xf) {
 			/* literal */
 			offset = opcode & 0x0fff;
 			snprintf(instruction->text, 128,
 				 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD %s%d",
-				 address, opcode, U ? "" : "-", offset);
+				 address, opcode, u ? "" : "-", offset);
 		} else {
-			uint8_t I, R;
+			uint8_t i, r;
 
-			I = (opcode & 0x02000000) >> 25;
-			R = (opcode & 0x00400000) >> 22;
+			i = (opcode & 0x02000000) >> 25;
+			r = (opcode & 0x00400000) >> 22;
 
-			if (I) {
+			if (i) {
 				/* register PLD{W} [<Rn>,+/-<Rm>{, <shift>}] */
 				offset = (opcode & 0x0F80) >> 7;
-				uint8_t Rm;
-				Rm = opcode & 0xf;
+				uint8_t rm;
+				rm = opcode & 0xf;
 
 				if (offset == 0) {
 					/* No shift */
 					snprintf(instruction->text, 128,
 						 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD%s [r%d, %sr%d]",
-						 address, opcode, R ? "" : "W", Rn, U ? "" : "-", Rm);
+						 address, opcode, r ? "" : "W", rn, u ? "" : "-", rm);
 
 				} else {
 					uint8_t shift;
@@ -162,22 +162,22 @@ static int evaluate_pld(uint32_t opcode,
 						/* LSL */
 						snprintf(instruction->text, 128,
 							 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD%s [r%d, %sr%d, LSL #0x%x)",
-							 address, opcode, R ? "" : "W", Rn, U ? "" : "-", Rm, offset);
+							 address, opcode, r ? "" : "W", rn, u ? "" : "-", rm, offset);
 					} else if (shift == 0x1) {
 						/* LSR */
 						snprintf(instruction->text, 128,
 							 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD%s [r%d, %sr%d, LSR #0x%x)",
-							 address, opcode, R ? "" : "W", Rn, U ? "" : "-", Rm, offset);
+							 address, opcode, r ? "" : "W", rn, u ? "" : "-", rm, offset);
 					} else if (shift == 0x2) {
 						/* ASR */
 						snprintf(instruction->text, 128,
 							 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD%s [r%d, %sr%d, ASR #0x%x)",
-							 address, opcode, R ? "" : "W", Rn, U ? "" : "-", Rm, offset);
+							 address, opcode, r ? "" : "W", rn, u ? "" : "-", rm, offset);
 					} else if (shift == 0x3) {
 						/* ROR */
 						snprintf(instruction->text, 128,
 							 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD%s [r%d, %sr%d, ROR #0x%x)",
-							 address, opcode, R ? "" : "W", Rn, U ? "" : "-", Rm, offset);
+							 address, opcode, r ? "" : "W", rn, u ? "" : "-", rm, offset);
 					}
 				}
 			} else {
@@ -186,11 +186,11 @@ static int evaluate_pld(uint32_t opcode,
 				if (offset == 0) {
 					snprintf(instruction->text, 128,
 						 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD%s [r%d]",
-						 address, opcode, R ? "" : "W", Rn);
+						 address, opcode, r ? "" : "W", rn);
 				} else {
 					snprintf(instruction->text, 128,
 						 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD%s [r%d, #%s%d]",
-						 address, opcode, R ? "" : "W", Rn, U ? "" : "-", offset);
+						 address, opcode, r ? "" : "W", rn, u ? "" : "-", offset);
 				}
 			}
 		}
@@ -349,13 +349,13 @@ static int evaluate_blx_imm(uint32_t opcode,
 static int evaluate_b_bl(uint32_t opcode,
 			 uint32_t address, struct arm_instruction *instruction)
 {
-	uint8_t L;
+	uint8_t l;
 	uint32_t immediate;
 	int offset;
 	uint32_t target_address;
 
 	immediate = opcode & 0x00ffffff;
-	L = (opcode & 0x01000000) >> 24;
+	l = (opcode & 0x01000000) >> 24;
 
 	/* sign extend 24-bit immediate */
 	if (immediate & 0x00800000)
@@ -368,7 +368,7 @@ static int evaluate_b_bl(uint32_t opcode,
 
 	target_address = address + 8 + offset;
 
-	if (L)
+	if (l)
 		instruction->type = ARM_BL;
 	else
 		instruction->type = ARM_B;
@@ -378,7 +378,7 @@ static int evaluate_b_bl(uint32_t opcode,
 			"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tB%s%s 0x%8.8" PRIx32,
 			address,
 			opcode,
-			(L) ? "L" : "",
+			(l) ? "L" : "",
 			COND(opcode),
 			target_address);
 
@@ -397,13 +397,13 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode,
 
 	/* MCRR or MRRC */
 	if (((opcode & 0x0ff00000) == 0x0c400000) || ((opcode & 0x0ff00000) == 0x0c500000)) {
-		uint8_t cp_opcode, Rd, Rn, CRm;
+		uint8_t cp_opcode, rd, rn, crm;
 		char *mnemonic;
 
 		cp_opcode = (opcode & 0xf0) >> 4;
-		Rd = (opcode & 0xf000) >> 12;
-		Rn = (opcode & 0xf0000) >> 16;
-		CRm = (opcode & 0xf);
+		rd = (opcode & 0xf000) >> 12;
+		rn = (opcode & 0xf0000) >> 16;
+		crm = (opcode & 0xf);
 
 		/* MCRR */
 		if ((opcode & 0x0ff00000) == 0x0c400000) {
@@ -424,15 +424,15 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode,
 				address, opcode, mnemonic,
 				((opcode & 0xf0000000) == 0xf0000000)
 				? "2" : COND(opcode),
-				COND(opcode), cp_num, cp_opcode, Rd, Rn, CRm);
+				COND(opcode), cp_num, cp_opcode, rd, rn, crm);
 	} else {/* LDC or STC */
-		uint8_t CRd, Rn, offset;
-		uint8_t U;
+		uint8_t crd, rn, offset;
+		uint8_t u;
 		char *mnemonic;
 		char addressing_mode[32];
 
-		CRd = (opcode & 0xf000) >> 12;
-		Rn = (opcode & 0xf0000) >> 16;
+		crd = (opcode & 0xf000) >> 12;
+		rn = (opcode & 0xf0000) >> 16;
 		offset = (opcode & 0xff) << 2;
 
 		/* load/store */
@@ -444,21 +444,21 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode,
 			mnemonic = "STC";
 		}
 
-		U = (opcode & 0x00800000) >> 23;
+		u = (opcode & 0x00800000) >> 23;
 
 		/* addressing modes */
 		if ((opcode & 0x01200000) == 0x01000000)/* offset */
 			snprintf(addressing_mode, 32, "[r%i, #%s%d]",
-					Rn, U ? "" : "-", offset);
+					rn, u ? "" : "-", offset);
 		else if ((opcode & 0x01200000) == 0x01200000)	/* pre-indexed */
 			snprintf(addressing_mode, 32, "[r%i, #%s%d]!",
-					Rn, U ? "" : "-", offset);
+					rn, u ? "" : "-", offset);
 		else if ((opcode & 0x01200000) == 0x00200000)	/* post-indexed */
 			snprintf(addressing_mode, 32, "[r%i], #%s%d",
-					Rn, U ? "" : "-", offset);
+					rn, u ? "" : "-", offset);
 		else if ((opcode & 0x01200000) == 0x00000000)	/* unindexed */
 			snprintf(addressing_mode, 32, "[r%i], {%d}",
-					Rn, offset >> 2);
+					rn, offset >> 2);
 
 		snprintf(instruction->text, 128, "0x%8.8" PRIx32
 				"\t0x%8.8" PRIx32
@@ -467,7 +467,7 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode,
 				((opcode & 0xf0000000) == 0xf0000000)
 				? "2" : COND(opcode),
 				(opcode & (1 << 22)) ? "L" : "",
-				cp_num, CRd, addressing_mode);
+				cp_num, crd, addressing_mode);
 	}
 
 	return ERROR_OK;
@@ -481,13 +481,13 @@ static int evaluate_cdp_mcr_mrc(uint32_t opcode,
 {
 	const char *cond;
 	char *mnemonic;
-	uint8_t cp_num, opcode_1, CRd_Rd, CRn, CRm, opcode_2;
+	uint8_t cp_num, opcode_1, crd_rd, crn, crm, opcode_2;
 
 	cond = ((opcode & 0xf0000000) == 0xf0000000) ? "2" : COND(opcode);
 	cp_num = (opcode & 0xf00) >> 8;
-	CRd_Rd = (opcode & 0xf000) >> 12;
-	CRn = (opcode & 0xf0000) >> 16;
-	CRm = (opcode & 0xf);
+	crd_rd = (opcode & 0xf000) >> 12;
+	crn = (opcode & 0xf0000) >> 16;
+	crm = (opcode & 0xf);
 	opcode_2 = (opcode & 0xe0) >> 5;
 
 	/* CDP or MRC/MCR */
@@ -511,9 +511,9 @@ static int evaluate_cdp_mcr_mrc(uint32_t opcode,
 				cond,
 				cp_num,
 				opcode_1,
-				CRd_Rd,
-				CRn,
-				CRm,
+				crd_rd,
+				crn,
+				crm,
 				opcode_2);
 	} else {/* bit 4 not set -> CDP */
 		instruction->type = ARM_CDP;
@@ -530,9 +530,9 @@ static int evaluate_cdp_mcr_mrc(uint32_t opcode,
 				cond,
 				cp_num,
 				opcode_1,
-				CRd_Rd,
-				CRn,
-				CRm,
+				crd_rd,
+				crn,
+				crm,
 				opcode_2);
 	}
 
@@ -543,60 +543,60 @@ static int evaluate_cdp_mcr_mrc(uint32_t opcode,
 static int evaluate_load_store(uint32_t opcode,
 			       uint32_t address, struct arm_instruction *instruction)
 {
-	uint8_t I, P, U, B, W, L;
-	uint8_t Rn, Rd;
+	uint8_t i, p, u, b, w, l;
+	uint8_t rn, rd;
 	char *operation;/* "LDR" or "STR" */
 	char *suffix;	/* "", "B", "T", "BT" */
 	char offset[32];
 
 	/* examine flags */
-	I = (opcode & 0x02000000) >> 25;
-	P = (opcode & 0x01000000) >> 24;
-	U = (opcode & 0x00800000) >> 23;
-	B = (opcode & 0x00400000) >> 22;
-	W = (opcode & 0x00200000) >> 21;
-	L = (opcode & 0x00100000) >> 20;
+	i = (opcode & 0x02000000) >> 25;
+	p = (opcode & 0x01000000) >> 24;
+	u = (opcode & 0x00800000) >> 23;
+	b = (opcode & 0x00400000) >> 22;
+	w = (opcode & 0x00200000) >> 21;
+	l = (opcode & 0x00100000) >> 20;
 
 	/* target register */
-	Rd = (opcode & 0xf000) >> 12;
+	rd = (opcode & 0xf000) >> 12;
 
 	/* base register */
-	Rn = (opcode & 0xf0000) >> 16;
+	rn = (opcode & 0xf0000) >> 16;
 
-	instruction->info.load_store.Rd = Rd;
-	instruction->info.load_store.Rn = Rn;
-	instruction->info.load_store.U = U;
+	instruction->info.load_store.rd = rd;
+	instruction->info.load_store.rn = rn;
+	instruction->info.load_store.u = u;
 
 	/* determine operation */
-	if (L)
+	if (l)
 		operation = "LDR";
 	else
 		operation = "STR";
 
 	/* determine instruction type and suffix */
-	if (B) {
-		if ((P == 0) && (W == 1)) {
-			if (L)
+	if (b) {
+		if ((p == 0) && (w == 1)) {
+			if (l)
 				instruction->type = ARM_LDRBT;
 			else
 				instruction->type = ARM_STRBT;
 			suffix = "BT";
 		} else {
-			if (L)
+			if (l)
 				instruction->type = ARM_LDRB;
 			else
 				instruction->type = ARM_STRB;
 			suffix = "B";
 		}
 	} else {
-		if ((P == 0) && (W == 1)) {
-			if (L)
+		if ((p == 0) && (w == 1)) {
+			if (l)
 				instruction->type = ARM_LDRT;
 			else
 				instruction->type = ARM_STRT;
 			suffix = "T";
 		} else {
-			if (L)
+			if (l)
 				instruction->type = ARM_LDR;
 			else
 				instruction->type = ARM_STR;
@@ -604,10 +604,10 @@ static int evaluate_load_store(uint32_t opcode,
 		}
 	}
 
-	if (!I) {	/* #+-<offset_12> */
+	if (!i) {	/* #+-<offset_12> */
 		uint32_t offset_12 = (opcode & 0xfff);
 		if (offset_12)
-			snprintf(offset, 32, ", #%s0x%" PRIx32 "", (U) ? "" : "-", offset_12);
+			snprintf(offset, 32, ", #%s0x%" PRIx32 "", (u) ? "" : "-", offset_12);
 		else
 			snprintf(offset, 32, "%s", "");
 
@@ -615,11 +615,11 @@ static int evaluate_load_store(uint32_t opcode,
 		instruction->info.load_store.offset.offset = offset_12;
 	} else {/* either +-<Rm> or +-<Rm>, <shift>, #<shift_imm> */
 		uint8_t shift_imm, shift;
-		uint8_t Rm;
+		uint8_t rm;
 
 		shift_imm = (opcode & 0xf80) >> 7;
 		shift = (opcode & 0x60) >> 5;
-		Rm = (opcode & 0xf);
+		rm = (opcode & 0xf);
 
 		/* LSR encodes a shift by 32 bit as 0x0 */
 		if ((shift == 0x1) && (shift_imm == 0x0))
@@ -634,35 +634,35 @@ static int evaluate_load_store(uint32_t opcode,
 			shift = 0x4;
 
 		instruction->info.load_store.offset_mode = 1;
-		instruction->info.load_store.offset.reg.Rm = Rm;
+		instruction->info.load_store.offset.reg.rm = rm;
 		instruction->info.load_store.offset.reg.shift = shift;
 		instruction->info.load_store.offset.reg.shift_imm = shift_imm;
 
 		if ((shift_imm == 0x0) && (shift == 0x0))	/* +-<Rm> */
-			snprintf(offset, 32, ", %sr%i", (U) ? "" : "-", Rm);
+			snprintf(offset, 32, ", %sr%i", (u) ? "" : "-", rm);
 		else {	/* +-<Rm>, <Shift>, #<shift_imm> */
 			switch (shift) {
 				case 0x0:		/* LSL */
-					snprintf(offset, 32, ", %sr%i, LSL #0x%x", (U) ? "" : "-", Rm, shift_imm);
+					snprintf(offset, 32, ", %sr%i, LSL #0x%x", (u) ? "" : "-", rm, shift_imm);
 					break;
 				case 0x1:		/* LSR */
-					snprintf(offset, 32, ", %sr%i, LSR #0x%x", (U) ? "" : "-", Rm, shift_imm);
+					snprintf(offset, 32, ", %sr%i, LSR #0x%x", (u) ? "" : "-", rm, shift_imm);
 					break;
 				case 0x2:		/* ASR */
-					snprintf(offset, 32, ", %sr%i, ASR #0x%x", (U) ? "" : "-", Rm, shift_imm);
+					snprintf(offset, 32, ", %sr%i, ASR #0x%x", (u) ? "" : "-", rm, shift_imm);
 					break;
 				case 0x3:		/* ROR */
-					snprintf(offset, 32, ", %sr%i, ROR #0x%x", (U) ? "" : "-", Rm, shift_imm);
+					snprintf(offset, 32, ", %sr%i, ROR #0x%x", (u) ? "" : "-", rm, shift_imm);
 					break;
 				case 0x4:		/* RRX */
-					snprintf(offset, 32, ", %sr%i, RRX", (U) ? "" : "-", Rm);
+					snprintf(offset, 32, ", %sr%i, RRX", (u) ? "" : "-", rm);
 					break;
 			}
 		}
 	}
 
-	if (P == 1) {
-		if (W == 0) {	/* offset */
+	if (p == 1) {
+		if (w == 0) {	/* offset */
 			snprintf(instruction->text,
 					128,
 					"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i%s]",
@@ -671,8 +671,8 @@ static int evaluate_load_store(uint32_t opcode,
 					operation,
 					COND(opcode),
 					suffix,
-					Rd,
-					Rn,
+					rd,
+					rn,
 					offset);
 
 			instruction->info.load_store.index_mode = 0;
@@ -685,8 +685,8 @@ static int evaluate_load_store(uint32_t opcode,
 					operation,
 					COND(opcode),
 					suffix,
-					Rd,
-					Rn,
+					rd,
+					rn,
 					offset);
 
 			instruction->info.load_store.index_mode = 1;
@@ -700,8 +700,8 @@ static int evaluate_load_store(uint32_t opcode,
 				operation,
 				COND(opcode),
 				suffix,
-				Rd,
-				Rn,
+				rd,
+				rn,
 				offset);
 
 		instruction->info.load_store.index_mode = 2;
@@ -1029,35 +1029,35 @@ undef:
 static int evaluate_misc_load_store(uint32_t opcode,
 				    uint32_t address, struct arm_instruction *instruction)
 {
-	uint8_t P, U, I, W, L, S, H;
-	uint8_t Rn, Rd;
+	uint8_t p, u, i, w, l, s, h;
+	uint8_t rn, rd;
 	char *operation;/* "LDR" or "STR" */
 	char *suffix;	/* "H", "SB", "SH", "D" */
 	char offset[32];
 
 	/* examine flags */
-	P = (opcode & 0x01000000) >> 24;
-	U = (opcode & 0x00800000) >> 23;
-	I = (opcode & 0x00400000) >> 22;
-	W = (opcode & 0x00200000) >> 21;
-	L = (opcode & 0x00100000) >> 20;
-	S = (opcode & 0x00000040) >> 6;
-	H = (opcode & 0x00000020) >> 5;
+	p = (opcode & 0x01000000) >> 24;
+	u = (opcode & 0x00800000) >> 23;
+	i = (opcode & 0x00400000) >> 22;
+	w = (opcode & 0x00200000) >> 21;
+	l = (opcode & 0x00100000) >> 20;
+	s = (opcode & 0x00000040) >> 6;
+	h = (opcode & 0x00000020) >> 5;
 
 	/* target register */
-	Rd = (opcode & 0xf000) >> 12;
+	rd = (opcode & 0xf000) >> 12;
 
 	/* base register */
-	Rn = (opcode & 0xf0000) >> 16;
+	rn = (opcode & 0xf0000) >> 16;
 
-	instruction->info.load_store.Rd = Rd;
-	instruction->info.load_store.Rn = Rn;
-	instruction->info.load_store.U = U;
+	instruction->info.load_store.rd = rd;
+	instruction->info.load_store.rn = rn;
+	instruction->info.load_store.u = u;
 
 	/* determine instruction type and suffix */
-	if (S) {/* signed */
-		if (L) {/* load */
-			if (H) {
+	if (s) {/* signed */
+		if (l) {/* load */
+			if (h) {
 				operation = "LDR";
 				instruction->type = ARM_LDRSH;
 				suffix = "SH";
@@ -1069,7 +1069,7 @@ static int evaluate_misc_load_store(uint32_t opcode,
 		} else {/* there are no signed stores, so this is used to encode double-register
 			 *load/stores */
 			suffix = "D";
-			if (H) {
+			if (h) {
 				operation = "STR";
 				instruction->type = ARM_STRD;
 			} else {
@@ -1079,7 +1079,7 @@ static int evaluate_misc_load_store(uint32_t opcode,
 		}
 	} else {/* unsigned */
 		suffix = "H";
-		if (L) {/* load */
+		if (l) {/* load */
 			operation = "LDR";
 			instruction->type = ARM_LDRH;
 		} else {/* store */
@@ -1088,25 +1088,25 @@ static int evaluate_misc_load_store(uint32_t opcode,
 		}
 	}
 
-	if (I) {/* Immediate offset/index (#+-<offset_8>)*/
+	if (i) {/* Immediate offset/index (#+-<offset_8>)*/
 		uint32_t offset_8 = ((opcode & 0xf00) >> 4) | (opcode & 0xf);
-		snprintf(offset, 32, "#%s0x%" PRIx32 "", (U) ? "" : "-", offset_8);
+		snprintf(offset, 32, "#%s0x%" PRIx32 "", (u) ? "" : "-", offset_8);
 
 		instruction->info.load_store.offset_mode = 0;
 		instruction->info.load_store.offset.offset = offset_8;
 	} else {/* Register offset/index (+-<Rm>) */
-		uint8_t Rm;
-		Rm = (opcode & 0xf);
-		snprintf(offset, 32, "%sr%i", (U) ? "" : "-", Rm);
+		uint8_t rm;
+		rm = (opcode & 0xf);
+		snprintf(offset, 32, "%sr%i", (u) ? "" : "-", rm);
 
 		instruction->info.load_store.offset_mode = 1;
-		instruction->info.load_store.offset.reg.Rm = Rm;
+		instruction->info.load_store.offset.reg.rm = rm;
 		instruction->info.load_store.offset.reg.shift = 0x0;
 		instruction->info.load_store.offset.reg.shift_imm = 0x0;
 	}
 
-	if (P == 1) {
-		if (W == 0) {	/* offset */
+	if (p == 1) {
+		if (w == 0) {	/* offset */
 			snprintf(instruction->text,
 					128,
 					"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i, %s]",
@@ -1115,8 +1115,8 @@ static int evaluate_misc_load_store(uint32_t opcode,
 					operation,
 					COND(opcode),
 					suffix,
-					Rd,
-					Rn,
+					rd,
+					rn,
 					offset);
 
 			instruction->info.load_store.index_mode = 0;
@@ -1129,8 +1129,8 @@ static int evaluate_misc_load_store(uint32_t opcode,
 					operation,
 					COND(opcode),
 					suffix,
-					Rd,
-					Rn,
+					rd,
+					rn,
 					offset);
 
 			instruction->info.load_store.index_mode = 1;
@@ -1144,8 +1144,8 @@ static int evaluate_misc_load_store(uint32_t opcode,
 				operation,
 				COND(opcode),
 				suffix,
-				Rd,
-				Rn,
+				rd,
+				rn,
 				offset);
 
 		instruction->info.load_store.index_mode = 2;
@@ -1158,7 +1158,7 @@ static int evaluate_misc_load_store(uint32_t opcode,
 static int evaluate_ldm_stm(uint32_t opcode,
 			    uint32_t address, struct arm_instruction *instruction)
 {
-	uint8_t P, U, S, W, L, Rn;
+	uint8_t p, u, s, w, l, rn;
 	uint32_t register_list;
 	char *addressing_mode;
 	char *mnemonic;
@@ -1167,20 +1167,20 @@ static int evaluate_ldm_stm(uint32_t opcode,
 	int i;
 	int first_reg = 1;
 
-	P = (opcode & 0x01000000) >> 24;
-	U = (opcode & 0x00800000) >> 23;
-	S = (opcode & 0x00400000) >> 22;
-	W = (opcode & 0x00200000) >> 21;
-	L = (opcode & 0x00100000) >> 20;
+	p = (opcode & 0x01000000) >> 24;
+	u = (opcode & 0x00800000) >> 23;
+	s = (opcode & 0x00400000) >> 22;
+	w = (opcode & 0x00200000) >> 21;
+	l = (opcode & 0x00100000) >> 20;
 	register_list = (opcode & 0xffff);
-	Rn = (opcode & 0xf0000) >> 16;
+	rn = (opcode & 0xf0000) >> 16;
 
-	instruction->info.load_store_multiple.Rn = Rn;
+	instruction->info.load_store_multiple.rn = rn;
 	instruction->info.load_store_multiple.register_list = register_list;
-	instruction->info.load_store_multiple.S = S;
-	instruction->info.load_store_multiple.W = W;
+	instruction->info.load_store_multiple.s = s;
+	instruction->info.load_store_multiple.w = w;
 
-	if (L) {
+	if (l) {
 		instruction->type = ARM_LDM;
 		mnemonic = "LDM";
 	} else {
@@ -1188,8 +1188,8 @@ static int evaluate_ldm_stm(uint32_t opcode,
 		mnemonic = "STM";
 	}
 
-	if (P) {
-		if (U) {
+	if (p) {
+		if (u) {
 			instruction->info.load_store_multiple.addressing_mode = 1;
 			addressing_mode = "IB";
 		} else {
@@ -1197,7 +1197,7 @@ static int evaluate_ldm_stm(uint32_t opcode,
 			addressing_mode = "DB";
 		}
 	} else {
-		if (U) {
+		if (u) {
 			instruction->info.load_store_multiple.addressing_mode = 0;
 			/* "IA" is the default in UAL syntax */
 			addressing_mode = "";
@@ -1229,7 +1229,7 @@ static int evaluate_ldm_stm(uint32_t opcode,
 			"\t%s%s%s r%i%s, {%s}%s",
 			address, opcode,
 			mnemonic, addressing_mode, COND(opcode),
-			Rn, (W) ? "!" : "", reg_list, (S) ? "^" : "");
+			rn, (w) ? "!" : "", reg_list, (s) ? "^" : "");
 
 	return ERROR_OK;
 }
@@ -1242,12 +1242,12 @@ static int evaluate_mul_and_extra_ld_st(uint32_t opcode,
 	if ((opcode & 0x000000f0) == 0x00000090) {
 		/* Multiply (accumulate) */
 		if ((opcode & 0x0f800000) == 0x00000000) {
-			uint8_t Rm, Rs, Rn, Rd, S;
-			Rm = opcode & 0xf;
-			Rs = (opcode & 0xf00) >> 8;
-			Rn = (opcode & 0xf000) >> 12;
-			Rd = (opcode & 0xf0000) >> 16;
-			S = (opcode & 0x00100000) >> 20;
+			uint8_t rm, rs, rn, rd, s;
+			rm = opcode & 0xf;
+			rs = (opcode & 0xf00) >> 8;
+			rn = (opcode & 0xf000) >> 12;
+			rd = (opcode & 0xf0000) >> 16;
+			s = (opcode & 0x00100000) >> 20;
 
 			/* examine A bit (accumulate) */
 			if (opcode & 0x00200000) {
@@ -1258,11 +1258,11 @@ static int evaluate_mul_and_extra_ld_st(uint32_t opcode,
 						address,
 						opcode,
 						COND(opcode),
-						(S) ? "S" : "",
-						Rd,
-						Rm,
-						Rs,
-						Rn);
+						(s) ? "S" : "",
+						rd,
+						rm,
+						rs,
+						rn);
 			} else {
 				instruction->type = ARM_MUL;
 				snprintf(instruction->text,
@@ -1271,10 +1271,10 @@ static int evaluate_mul_and_extra_ld_st(uint32_t opcode,
 						address,
 						opcode,
 						COND(opcode),
-						(S) ? "S" : "",
-						Rd,
-						Rm,
-						Rs);
+						(s) ? "S" : "",
+						rd,
+						rm,
+						rs);
 			}
 
 			return ERROR_OK;
@@ -1283,12 +1283,12 @@ static int evaluate_mul_and_extra_ld_st(uint32_t opcode,
 		/* Multiply (accumulate) long */
 		if ((opcode & 0x0f800000) == 0x00800000) {
 			char *mnemonic = NULL;
-			uint8_t Rm, Rs, RdHi, RdLow, S;
-			Rm = opcode & 0xf;
-			Rs = (opcode & 0xf00) >> 8;
-			RdHi = (opcode & 0xf000) >> 12;
-			RdLow = (opcode & 0xf0000) >> 16;
-			S = (opcode & 0x00100000) >> 20;
+			uint8_t rm, rs, rd_hi, rd_low, s;
+			rm = opcode & 0xf;
+			rs = (opcode & 0xf00) >> 8;
+			rd_hi = (opcode & 0xf000) >> 12;
+			rd_low = (opcode & 0xf0000) >> 16;
+			s = (opcode & 0x00100000) >> 20;
 
 			switch ((opcode & 0x00600000) >> 21) {
 				case 0x0:
@@ -1316,21 +1316,21 @@ static int evaluate_mul_and_extra_ld_st(uint32_t opcode,
 					opcode,
 					mnemonic,
 					COND(opcode),
-					(S) ? "S" : "",
-					RdLow,
-					RdHi,
-					Rm,
-					Rs);
+					(s) ? "S" : "",
+					rd_low,
+					rd_hi,
+					rm,
+					rs);
 
 			return ERROR_OK;
 		}
 
 		/* Swap/swap byte */
 		if ((opcode & 0x0f800000) == 0x01000000) {
-			uint8_t Rm, Rd, Rn;
-			Rm = opcode & 0xf;
-			Rd = (opcode & 0xf000) >> 12;
-			Rn = (opcode & 0xf0000) >> 16;
+			uint8_t rm, rd, rn;
+			rm = opcode & 0xf;
+			rd = (opcode & 0xf000) >> 12;
+			rn = (opcode & 0xf0000) >> 16;
 
 			/* examine B flag */
 			instruction->type = (opcode & 0x00400000) ? ARM_SWPB : ARM_SWP;
@@ -1342,9 +1342,9 @@ static int evaluate_mul_and_extra_ld_st(uint32_t opcode,
 					opcode,
 					(opcode & 0x00400000) ? "SWPB" : "SWP",
 					COND(opcode),
-					Rd,
-					Rm,
-					Rn);
+					rd,
+					rm,
+					rn);
 			return ERROR_OK;
 		}
 
@@ -1356,8 +1356,8 @@ static int evaluate_mul_and_extra_ld_st(uint32_t opcode,
 static int evaluate_mrs_msr(uint32_t opcode,
 			    uint32_t address, struct arm_instruction *instruction)
 {
-	int R = (opcode & 0x00400000) >> 22;
-	char *PSR = (R) ? "SPSR" : "CPSR";
+	int r = (opcode & 0x00400000) >> 22;
+	char *PSR = (r) ? "SPSR" : "CPSR";
 
 	/* Move register to status register (MSR) */
 	if (opcode & 0x00200000) {
@@ -1382,7 +1382,7 @@ static int evaluate_mrs_msr(uint32_t opcode,
 					ror(immediate, (rotate * 2))
 					);
 		} else {/* register variant */
-			uint8_t Rm = opcode & 0xf;
+			uint8_t rm = opcode & 0xf;
 			snprintf(instruction->text,
 					128,
 					"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMSR%s %s_%s%s%s%s, r%i",
@@ -1394,15 +1394,15 @@ static int evaluate_mrs_msr(uint32_t opcode,
 					(opcode & 0x20000) ? "x" : "",
 					(opcode & 0x40000) ? "s" : "",
 					(opcode & 0x80000) ? "f" : "",
-					Rm
+					rm
 					);
 		}
 
 	} else {/* Move status register to register (MRS) */
-		uint8_t Rd;
+		uint8_t rd;
 
 		instruction->type = ARM_MRS;
-		Rd = (opcode & 0x0000f000) >> 12;
+		rd = (opcode & 0x0000f000) >> 12;
 
 		snprintf(instruction->text,
 				128,
@@ -1410,7 +1410,7 @@ static int evaluate_mrs_msr(uint32_t opcode,
 				address,
 				opcode,
 				COND(opcode),
-				Rd,
+				rd,
 				PSR);
 	}
 
@@ -1427,37 +1427,37 @@ static int evaluate_misc_instr(uint32_t opcode,
 
 	/* BX */
 	if ((opcode & 0x006000f0) == 0x00200010) {
-		uint8_t Rm;
+		uint8_t rm;
 		instruction->type = ARM_BX;
-		Rm = opcode & 0xf;
+		rm = opcode & 0xf;
 
 		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBX%s r%i",
-				address, opcode, COND(opcode), Rm);
+				address, opcode, COND(opcode), rm);
 
-		instruction->info.b_bl_bx_blx.reg_operand = Rm;
+		instruction->info.b_bl_bx_blx.reg_operand = rm;
 		instruction->info.b_bl_bx_blx.target_address = -1;
 	}
 
 	/* BXJ - "Jazelle" support (ARMv5-J) */
 	if ((opcode & 0x006000f0) == 0x00200020) {
-		uint8_t Rm;
+		uint8_t rm;
 		instruction->type = ARM_BX;
-		Rm = opcode & 0xf;
+		rm = opcode & 0xf;
 
 		snprintf(instruction->text, 128,
 				"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBXJ%s r%i",
-				address, opcode, COND(opcode), Rm);
+				address, opcode, COND(opcode), rm);
 
-		instruction->info.b_bl_bx_blx.reg_operand = Rm;
+		instruction->info.b_bl_bx_blx.reg_operand = rm;
 		instruction->info.b_bl_bx_blx.target_address = -1;
 	}
 
 	/* CLZ */
 	if ((opcode & 0x006000f0) == 0x00600010) {
-		uint8_t Rm, Rd;
+		uint8_t rm, rd;
 		instruction->type = ARM_CLZ;
-		Rm = opcode & 0xf;
-		Rd = (opcode & 0xf000) >> 12;
+		rm = opcode & 0xf;
+		rd = (opcode & 0xf000) >> 12;
 
 		snprintf(instruction->text,
 				128,
@@ -1465,30 +1465,30 @@ static int evaluate_misc_instr(uint32_t opcode,
 				address,
 				opcode,
 				COND(opcode),
-				Rd,
-				Rm);
+				rd,
+				rm);
 	}
 
 	/* BLX(2) */
 	if ((opcode & 0x006000f0) == 0x00200030) {
-		uint8_t Rm;
+		uint8_t rm;
 		instruction->type = ARM_BLX;
-		Rm = opcode & 0xf;
+		rm = opcode & 0xf;
 
 		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBLX%s r%i",
-				address, opcode, COND(opcode), Rm);
+				address, opcode, COND(opcode), rm);
 
-		instruction->info.b_bl_bx_blx.reg_operand = Rm;
+		instruction->info.b_bl_bx_blx.reg_operand = rm;
 		instruction->info.b_bl_bx_blx.target_address = -1;
 	}
 
 	/* Enhanced DSP add/subtracts */
 	if ((opcode & 0x0000000f0) == 0x00000050) {
-		uint8_t Rm, Rd, Rn;
+		uint8_t rm, rd, rn;
 		char *mnemonic = NULL;
-		Rm = opcode & 0xf;
-		Rd = (opcode & 0xf000) >> 12;
-		Rn = (opcode & 0xf0000) >> 16;
+		rm = opcode & 0xf;
+		rd = (opcode & 0xf000) >> 12;
+		rn = (opcode & 0xf0000) >> 16;
 
 		switch ((opcode & 0x00600000) >> 21) {
 			case 0x0:
@@ -1516,9 +1516,9 @@ static int evaluate_misc_instr(uint32_t opcode,
 				opcode,
 				mnemonic,
 				COND(opcode),
-				Rd,
-				Rm,
-				Rn);
+				rd,
+				rm,
+				rn);
 	}
 
 	/* exception return */
@@ -1571,12 +1571,12 @@ static int evaluate_misc_instr(uint32_t opcode,
 
 		/* SMLA < x><y> */
 		if ((opcode & 0x00600000) == 0x00000000) {
-			uint8_t Rd, Rm, Rs, Rn;
-			instruction->type = ARM_SMLAxy;
-			Rd = (opcode & 0xf0000) >> 16;
-			Rm = (opcode & 0xf);
-			Rs = (opcode & 0xf00) >> 8;
-			Rn = (opcode & 0xf000) >> 12;
+			uint8_t rd, rm, rs, rn;
+			instruction->type = ARM_SMLAXY;
+			rd = (opcode & 0xf0000) >> 16;
+			rm = (opcode & 0xf);
+			rs = (opcode & 0xf00) >> 8;
+			rn = (opcode & 0xf000) >> 12;
 
 			snprintf(instruction->text,
 					128,
@@ -1586,20 +1586,20 @@ static int evaluate_misc_instr(uint32_t opcode,
 					(x) ? "T" : "B",
 					(y) ? "T" : "B",
 					COND(opcode),
-					Rd,
-					Rm,
-					Rs,
-					Rn);
+					rd,
+					rm,
+					rs,
+					rn);
 		}
 
 		/* SMLAL < x><y> */
 		if ((opcode & 0x00600000) == 0x00400000) {
-			uint8_t RdLow, RdHi, Rm, Rs;
-			instruction->type = ARM_SMLAxy;
-			RdHi = (opcode & 0xf0000) >> 16;
-			RdLow = (opcode & 0xf000) >> 12;
-			Rm = (opcode & 0xf);
-			Rs = (opcode & 0xf00) >> 8;
+			uint8_t rd_low, rd_hi, rm, rs;
+			instruction->type = ARM_SMLAXY;
+			rd_hi = (opcode & 0xf0000) >> 16;
+			rd_low = (opcode & 0xf000) >> 12;
+			rm = (opcode & 0xf);
+			rs = (opcode & 0xf00) >> 8;
 
 			snprintf(instruction->text,
 					128,
@@ -1609,20 +1609,20 @@ static int evaluate_misc_instr(uint32_t opcode,
 					(x) ? "T" : "B",
 					(y) ? "T" : "B",
 					COND(opcode),
-					RdLow,
-					RdHi,
-					Rm,
-					Rs);
+					rd_low,
+					rd_hi,
+					rm,
+					rs);
 		}
 
 		/* SMLAW < y> */
 		if (((opcode & 0x00600000) == 0x00200000) && (x == 0)) {
-			uint8_t Rd, Rm, Rs, Rn;
-			instruction->type = ARM_SMLAWy;
-			Rd = (opcode & 0xf0000) >> 16;
-			Rm = (opcode & 0xf);
-			Rs = (opcode & 0xf00) >> 8;
-			Rn = (opcode & 0xf000) >> 12;
+			uint8_t rd, rm, rs, rn;
+			instruction->type = ARM_SMLAWY;
+			rd = (opcode & 0xf0000) >> 16;
+			rm = (opcode & 0xf);
+			rs = (opcode & 0xf00) >> 8;
+			rn = (opcode & 0xf000) >> 12;
 
 			snprintf(instruction->text,
 					128,
@@ -1631,19 +1631,19 @@ static int evaluate_misc_instr(uint32_t opcode,
 					opcode,
 					(y) ? "T" : "B",
 					COND(opcode),
-					Rd,
-					Rm,
-					Rs,
-					Rn);
+					rd,
+					rm,
+					rs,
+					rn);
 		}
 
 		/* SMUL < x><y> */
 		if ((opcode & 0x00600000) == 0x00600000) {
-			uint8_t Rd, Rm, Rs;
-			instruction->type = ARM_SMULxy;
-			Rd = (opcode & 0xf0000) >> 16;
-			Rm = (opcode & 0xf);
-			Rs = (opcode & 0xf00) >> 8;
+			uint8_t rd, rm, rs;
+			instruction->type = ARM_SMULXY;
+			rd = (opcode & 0xf0000) >> 16;
+			rm = (opcode & 0xf);
+			rs = (opcode & 0xf00) >> 8;
 
 			snprintf(instruction->text,
 					128,
@@ -1653,18 +1653,18 @@ static int evaluate_misc_instr(uint32_t opcode,
 					(x) ? "T" : "B",
 					(y) ? "T" : "B",
 					COND(opcode),
-					Rd,
-					Rm,
-					Rs);
+					rd,
+					rm,
+					rs);
 		}
 
 		/* SMULW < y> */
 		if (((opcode & 0x00600000) == 0x00200000) && (x == 1)) {
-			uint8_t Rd, Rm, Rs;
-			instruction->type = ARM_SMULWy;
-			Rd = (opcode & 0xf0000) >> 16;
-			Rm = (opcode & 0xf);
-			Rs = (opcode & 0xf00) >> 8;
+			uint8_t rd, rm, rs;
+			instruction->type = ARM_SMULWY;
+			rd = (opcode & 0xf0000) >> 16;
+			rm = (opcode & 0xf);
+			rs = (opcode & 0xf00) >> 8;
 
 			snprintf(instruction->text,
 					128,
@@ -1673,9 +1673,9 @@ static int evaluate_misc_instr(uint32_t opcode,
 					opcode,
 					(y) ? "T" : "B",
 					COND(opcode),
-					Rd,
-					Rm,
-					Rs);
+					rd,
+					rm,
+					rs);
 		}
 	}
 
@@ -1686,24 +1686,24 @@ static int evaluate_mov_imm(uint32_t opcode,
 			      uint32_t address, struct arm_instruction *instruction)
 {
 	uint16_t immediate;
-	uint8_t Rd;
-	bool T;
+	uint8_t rd;
+	bool t;
 
-	Rd = (opcode & 0xf000) >> 12;
-	T = opcode & 0x00400000;
+	rd = (opcode & 0xf000) >> 12;
+	t = opcode & 0x00400000;
 	immediate = (opcode & 0xf0000) >> 4 | (opcode & 0xfff);
 
 	instruction->type = ARM_MOV;
-	instruction->info.data_proc.Rd = Rd;
+	instruction->info.data_proc.rd = rd;
 
 	snprintf(instruction->text,
 		 128,
 		 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMOV%s%s r%i, #0x%" PRIx16,
 		 address,
 		 opcode,
-		 T ? "T" : "W",
+		 t ? "T" : "W",
 		 COND(opcode),
-		 Rd,
+		 rd,
 		 immediate);
 
 	return ERROR_OK;
@@ -1712,20 +1712,20 @@ static int evaluate_mov_imm(uint32_t opcode,
 static int evaluate_data_proc(uint32_t opcode,
 			      uint32_t address, struct arm_instruction *instruction)
 {
-	uint8_t I, op, S, Rn, Rd;
+	uint8_t i, op, s, rn, rd;
 	char *mnemonic = NULL;
 	char shifter_operand[32];
 
-	I = (opcode & 0x02000000) >> 25;
+	i = (opcode & 0x02000000) >> 25;
 	op = (opcode & 0x01e00000) >> 21;
-	S = (opcode & 0x00100000) >> 20;
+	s = (opcode & 0x00100000) >> 20;
 
-	Rd = (opcode & 0xf000) >> 12;
-	Rn = (opcode & 0xf0000) >> 16;
+	rd = (opcode & 0xf000) >> 12;
+	rn = (opcode & 0xf0000) >> 16;
 
-	instruction->info.data_proc.Rd = Rd;
-	instruction->info.data_proc.Rn = Rn;
-	instruction->info.data_proc.S = S;
+	instruction->info.data_proc.rd = rd;
+	instruction->info.data_proc.rn = rn;
+	instruction->info.data_proc.s = s;
 
 	switch (op) {
 		case 0x0:
@@ -1794,7 +1794,7 @@ static int evaluate_data_proc(uint32_t opcode,
 			break;
 	}
 
-	if (I) {/* immediate shifter operand (#<immediate>)*/
+	if (i) {/* immediate shifter operand (#<immediate>)*/
 		uint8_t immed_8 = opcode & 0xff;
 		uint8_t rotate_imm = (opcode & 0xf00) >> 8;
 		uint32_t immediate;
@@ -1806,9 +1806,9 @@ static int evaluate_data_proc(uint32_t opcode,
 		instruction->info.data_proc.variant = 0;
 		instruction->info.data_proc.shifter_operand.immediate.immediate = immediate;
 	} else {/* register-based shifter operand */
-		uint8_t shift, Rm;
+		uint8_t shift, rm;
 		shift = (opcode & 0x60) >> 5;
-		Rm = (opcode & 0xf);
+		rm = (opcode & 0xf);
 
 		if ((opcode & 0x10) != 0x10) {	/* Immediate shifts ("<Rm>" or "<Rm>, <shift>
 						 *#<shift_immediate>") */
@@ -1816,7 +1816,7 @@ static int evaluate_data_proc(uint32_t opcode,
 			shift_imm = (opcode & 0xf80) >> 7;
 
 			instruction->info.data_proc.variant = 1;
-			instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm;
+			instruction->info.data_proc.shifter_operand.immediate_shift.rm = rm;
 			instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm =
 				shift_imm;
 			instruction->info.data_proc.shifter_operand.immediate_shift.shift = shift;
@@ -1834,51 +1834,51 @@ static int evaluate_data_proc(uint32_t opcode,
 				shift = 0x4;
 
 			if ((shift_imm == 0x0) && (shift == 0x0))
-				snprintf(shifter_operand, 32, "r%i", Rm);
+				snprintf(shifter_operand, 32, "r%i", rm);
 			else {
 				if (shift == 0x0)	/* LSL */
 					snprintf(shifter_operand,
 							32,
 							"r%i, LSL #0x%x",
-							Rm,
+							rm,
 							shift_imm);
 				else if (shift == 0x1)	/* LSR */
 					snprintf(shifter_operand,
 							32,
 							"r%i, LSR #0x%x",
-							Rm,
+							rm,
 							shift_imm);
 				else if (shift == 0x2)	/* ASR */
 					snprintf(shifter_operand,
 							32,
 							"r%i, ASR #0x%x",
-							Rm,
+							rm,
 							shift_imm);
 				else if (shift == 0x3)	/* ROR */
 					snprintf(shifter_operand,
 							32,
 							"r%i, ROR #0x%x",
-							Rm,
+							rm,
 							shift_imm);
 				else if (shift == 0x4)	/* RRX */
-					snprintf(shifter_operand, 32, "r%i, RRX", Rm);
+					snprintf(shifter_operand, 32, "r%i, RRX", rm);
 			}
 		} else {/* Register shifts ("<Rm>, <shift> <Rs>") */
-			uint8_t Rs = (opcode & 0xf00) >> 8;
+			uint8_t rs = (opcode & 0xf00) >> 8;
 
 			instruction->info.data_proc.variant = 2;
-			instruction->info.data_proc.shifter_operand.register_shift.Rm = Rm;
-			instruction->info.data_proc.shifter_operand.register_shift.Rs = Rs;
+			instruction->info.data_proc.shifter_operand.register_shift.rm = rm;
+			instruction->info.data_proc.shifter_operand.register_shift.rs = rs;
 			instruction->info.data_proc.shifter_operand.register_shift.shift = shift;
 
 			if (shift == 0x0)	/* LSL */
-				snprintf(shifter_operand, 32, "r%i, LSL r%i", Rm, Rs);
+				snprintf(shifter_operand, 32, "r%i, LSL r%i", rm, rs);
 			else if (shift == 0x1)	/* LSR */
-				snprintf(shifter_operand, 32, "r%i, LSR r%i", Rm, Rs);
+				snprintf(shifter_operand, 32, "r%i, LSR r%i", rm, rs);
 			else if (shift == 0x2)	/* ASR */
-				snprintf(shifter_operand, 32, "r%i, ASR r%i", Rm, Rs);
+				snprintf(shifter_operand, 32, "r%i, ASR r%i", rm, rs);
 			else if (shift == 0x3)	/* ROR */
-				snprintf(shifter_operand, 32, "r%i, ROR r%i", Rm, Rs);
+				snprintf(shifter_operand, 32, "r%i, ROR r%i", rm, rs);
 		}
 	}
 
@@ -1891,9 +1891,9 @@ static int evaluate_data_proc(uint32_t opcode,
 				opcode,
 				mnemonic,
 				COND(opcode),
-				(S) ? "S" : "",
-				Rd,
-				Rn,
+				(s) ? "S" : "",
+				rd,
+				rn,
 				shifter_operand);
 	} else if ((op == 0xd) || (op == 0xf)) {	/* <opcode1>{<cond>}{S} <Rd>,
 							 *<shifter_operand> */
@@ -1911,13 +1911,13 @@ static int evaluate_data_proc(uint32_t opcode,
 					opcode,
 					mnemonic,
 					COND(opcode),
-					(S) ? "S" : "",
-					Rd,
+					(s) ? "S" : "",
+					rd,
 					shifter_operand);
 	} else {/* <opcode2>{<cond>} <Rn>, <shifter_operand> */
 		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s r%i, %s",
 				address, opcode, mnemonic, COND(opcode),
-				Rn, shifter_operand);
+				rn, shifter_operand);
 	}
 
 	return ERROR_OK;
@@ -2123,9 +2123,9 @@ static int evaluate_b_bl_blx_thumb(uint16_t opcode,
 static int evaluate_add_sub_thumb(uint16_t opcode,
 				  uint32_t address, struct arm_instruction *instruction)
 {
-	uint8_t Rd = (opcode >> 0) & 0x7;
-	uint8_t Rn = (opcode >> 3) & 0x7;
-	uint8_t Rm_imm = (opcode >> 6) & 0x7;
+	uint8_t rd = (opcode >> 0) & 0x7;
+	uint8_t rn = (opcode >> 3) & 0x7;
+	uint8_t rm_imm = (opcode >> 6) & 0x7;
 	uint32_t opc = opcode & (1 << 9);
 	uint32_t reg_imm  = opcode & (1 << 10);
 	char *mnemonic;
@@ -2139,22 +2139,22 @@ static int evaluate_add_sub_thumb(uint16_t opcode,
 		mnemonic = "ADDS";
 	}
 
-	instruction->info.data_proc.Rd = Rd;
-	instruction->info.data_proc.Rn = Rn;
-	instruction->info.data_proc.S = 1;
+	instruction->info.data_proc.rd = rd;
+	instruction->info.data_proc.rn = rn;
+	instruction->info.data_proc.s = 1;
 
 	if (reg_imm) {
 		instruction->info.data_proc.variant = 0;/*immediate*/
-		instruction->info.data_proc.shifter_operand.immediate.immediate = Rm_imm;
+		instruction->info.data_proc.shifter_operand.immediate.immediate = rm_imm;
 		snprintf(instruction->text, 128,
 				"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, r%i, #%d",
-				address, opcode, mnemonic, Rd, Rn, Rm_imm);
+				address, opcode, mnemonic, rd, rn, rm_imm);
 	} else {
 		instruction->info.data_proc.variant = 1;/*immediate shift*/
-		instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm_imm;
+		instruction->info.data_proc.shifter_operand.immediate_shift.rm = rm_imm;
 		snprintf(instruction->text, 128,
 				"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, r%i, r%i",
-				address, opcode, mnemonic, Rd, Rn, Rm_imm);
+				address, opcode, mnemonic, rd, rn, rm_imm);
 	}
 
 	return ERROR_OK;
@@ -2163,8 +2163,8 @@ static int evaluate_add_sub_thumb(uint16_t opcode,
 static int evaluate_shift_imm_thumb(uint16_t opcode,
 				    uint32_t address, struct arm_instruction *instruction)
 {
-	uint8_t Rd = (opcode >> 0) & 0x7;
-	uint8_t Rm = (opcode >> 3) & 0x7;
+	uint8_t rd = (opcode >> 0) & 0x7;
+	uint8_t rm = (opcode >> 3) & 0x7;
 	uint8_t imm = (opcode >> 6) & 0x1f;
 	uint8_t opc = (opcode >> 11) & 0x3;
 	char *mnemonic = NULL;
@@ -2190,17 +2190,17 @@ static int evaluate_shift_imm_thumb(uint16_t opcode,
 	if ((imm == 0) && (opc != 0))
 		imm = 32;
 
-	instruction->info.data_proc.Rd = Rd;
-	instruction->info.data_proc.Rn = -1;
-	instruction->info.data_proc.S = 1;
+	instruction->info.data_proc.rd = rd;
+	instruction->info.data_proc.rn = -1;
+	instruction->info.data_proc.s = 1;
 
 	instruction->info.data_proc.variant = 1;/*immediate_shift*/
-	instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm;
+	instruction->info.data_proc.shifter_operand.immediate_shift.rm = rm;
 	instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm = imm;
 
 	snprintf(instruction->text, 128,
 			"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, r%i, #%#2.2x",
-			address, opcode, mnemonic, Rd, Rm, imm);
+			address, opcode, mnemonic, rd, rm, imm);
 
 	return ERROR_OK;
 }
@@ -2209,13 +2209,13 @@ static int evaluate_data_proc_imm_thumb(uint16_t opcode,
 					uint32_t address, struct arm_instruction *instruction)
 {
 	uint8_t imm = opcode & 0xff;
-	uint8_t Rd = (opcode >> 8) & 0x7;
+	uint8_t rd = (opcode >> 8) & 0x7;
 	uint32_t opc = (opcode >> 11) & 0x3;
 	char *mnemonic = NULL;
 
-	instruction->info.data_proc.Rd = Rd;
-	instruction->info.data_proc.Rn = Rd;
-	instruction->info.data_proc.S = 1;
+	instruction->info.data_proc.rd = rd;
+	instruction->info.data_proc.rn = rd;
+	instruction->info.data_proc.s = 1;
 	instruction->info.data_proc.variant = 0;/*immediate*/
 	instruction->info.data_proc.shifter_operand.immediate.immediate = imm;
 
@@ -2223,12 +2223,12 @@ static int evaluate_data_proc_imm_thumb(uint16_t opcode,
 		case 0:
 			instruction->type = ARM_MOV;
 			mnemonic = "MOVS";
-			instruction->info.data_proc.Rn = -1;
+			instruction->info.data_proc.rn = -1;
 			break;
 		case 1:
 			instruction->type = ARM_CMP;
 			mnemonic = "CMP";
-			instruction->info.data_proc.Rd = -1;
+			instruction->info.data_proc.rd = -1;
 			break;
 		case 2:
 			instruction->type = ARM_ADD;
@@ -2242,7 +2242,7 @@ static int evaluate_data_proc_imm_thumb(uint16_t opcode,
 
 	snprintf(instruction->text, 128,
 			"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, #%#2.2x",
-			address, opcode, mnemonic, Rd, imm);
+			address, opcode, mnemonic, rd, imm);
 
 	return ERROR_OK;
 }
@@ -2250,27 +2250,27 @@ static int evaluate_data_proc_imm_thumb(uint16_t opcode,
 static int evaluate_data_proc_thumb(uint16_t opcode,
 				    uint32_t address, struct arm_instruction *instruction)
 {
-	uint8_t high_reg, op, Rm, Rd, H1, H2;
+	uint8_t high_reg, op, rm, rd, h1, h2;
 	char *mnemonic = NULL;
 	bool nop = false;
 
 	high_reg = (opcode & 0x0400) >> 10;
 	op = (opcode & 0x03C0) >> 6;
 
-	Rd = (opcode & 0x0007);
-	Rm = (opcode & 0x0038) >> 3;
-	H1 = (opcode & 0x0080) >> 7;
-	H2 = (opcode & 0x0040) >> 6;
+	rd = (opcode & 0x0007);
+	rm = (opcode & 0x0038) >> 3;
+	h1 = (opcode & 0x0080) >> 7;
+	h2 = (opcode & 0x0040) >> 6;
 
-	instruction->info.data_proc.Rd = Rd;
-	instruction->info.data_proc.Rn = Rd;
-	instruction->info.data_proc.S = (!high_reg || (instruction->type == ARM_CMP));
+	instruction->info.data_proc.rd = rd;
+	instruction->info.data_proc.rn = rd;
+	instruction->info.data_proc.s = (!high_reg || (instruction->type == ARM_CMP));
 	instruction->info.data_proc.variant = 1	/*immediate shift*/;
-	instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm;
+	instruction->info.data_proc.shifter_operand.immediate_shift.rm = rm;
 
 	if (high_reg) {
-		Rd |= H1 << 3;
-		Rm |= H2 << 3;
+		rd |= h1 << 3;
+		rm |= h2 << 3;
 		op >>= 2;
 
 		switch (op) {
@@ -2285,24 +2285,24 @@ static int evaluate_data_proc_thumb(uint16_t opcode,
 			case 0x2:
 				instruction->type = ARM_MOV;
 				mnemonic = "MOV";
-				if (Rd == Rm)
+				if (rd == rm)
 					nop = true;
 				break;
 			case 0x3:
 				if ((opcode & 0x7) == 0x0) {
-					instruction->info.b_bl_bx_blx.reg_operand = Rm;
-					if (H1) {
+					instruction->info.b_bl_bx_blx.reg_operand = rm;
+					if (h1) {
 						instruction->type = ARM_BLX;
 						snprintf(instruction->text, 128,
 								"0x%8.8" PRIx32
 								"  0x%4.4x    \tBLX\tr%i",
-								address, opcode, Rm);
+								address, opcode, rm);
 					} else {
 						instruction->type = ARM_BX;
 						snprintf(instruction->text, 128,
 								"0x%8.8" PRIx32
 								"  0x%4.4x    \tBX\tr%i",
-								address, opcode, Rm);
+								address, opcode, rm);
 					}
 				} else {
 					instruction->type = ARM_UNDEFINED_INSTRUCTION;
@@ -2329,24 +2329,24 @@ static int evaluate_data_proc_thumb(uint16_t opcode,
 				mnemonic = "LSLS";
 				instruction->info.data_proc.variant = 2	/*register shift*/;
 				instruction->info.data_proc.shifter_operand.register_shift.shift = 0;
-				instruction->info.data_proc.shifter_operand.register_shift.Rm = Rd;
-				instruction->info.data_proc.shifter_operand.register_shift.Rs = Rm;
+				instruction->info.data_proc.shifter_operand.register_shift.rm = rd;
+				instruction->info.data_proc.shifter_operand.register_shift.rs = rm;
 				break;
 			case 0x3:
 				instruction->type = ARM_MOV;
 				mnemonic = "LSRS";
 				instruction->info.data_proc.variant = 2	/*register shift*/;
 				instruction->info.data_proc.shifter_operand.register_shift.shift = 1;
-				instruction->info.data_proc.shifter_operand.register_shift.Rm = Rd;
-				instruction->info.data_proc.shifter_operand.register_shift.Rs = Rm;
+				instruction->info.data_proc.shifter_operand.register_shift.rm = rd;
+				instruction->info.data_proc.shifter_operand.register_shift.rs = rm;
 				break;
 			case 0x4:
 				instruction->type = ARM_MOV;
 				mnemonic = "ASRS";
 				instruction->info.data_proc.variant = 2	/*register shift*/;
 				instruction->info.data_proc.shifter_operand.register_shift.shift = 2;
-				instruction->info.data_proc.shifter_operand.register_shift.Rm = Rd;
-				instruction->info.data_proc.shifter_operand.register_shift.Rs = Rm;
+				instruction->info.data_proc.shifter_operand.register_shift.rm = rd;
+				instruction->info.data_proc.shifter_operand.register_shift.rs = rm;
 				break;
 			case 0x5:
 				instruction->type = ARM_ADC;
@@ -2361,8 +2361,8 @@ static int evaluate_data_proc_thumb(uint16_t opcode,
 				mnemonic = "RORS";
 				instruction->info.data_proc.variant = 2	/*register shift*/;
 				instruction->info.data_proc.shifter_operand.register_shift.shift = 3;
-				instruction->info.data_proc.shifter_operand.register_shift.Rm = Rd;
-				instruction->info.data_proc.shifter_operand.register_shift.Rs = Rm;
+				instruction->info.data_proc.shifter_operand.register_shift.rm = rd;
+				instruction->info.data_proc.shifter_operand.register_shift.rs = rm;
 				break;
 			case 0x8:
 				instruction->type = ARM_TST;
@@ -2373,7 +2373,7 @@ static int evaluate_data_proc_thumb(uint16_t opcode,
 				mnemonic = "RSBS";
 				instruction->info.data_proc.variant = 0	/*immediate*/;
 				instruction->info.data_proc.shifter_operand.immediate.immediate = 0;
-				instruction->info.data_proc.Rn = Rm;
+				instruction->info.data_proc.rn = rm;
 				break;
 			case 0xA:
 				instruction->type = ARM_CMP;
@@ -2406,11 +2406,11 @@ static int evaluate_data_proc_thumb(uint16_t opcode,
 		snprintf(instruction->text, 128,
 				"0x%8.8" PRIx32 "  0x%4.4x    \tNOP\t\t\t"
 				"; (%s r%i, r%i)",
-				address, opcode, mnemonic, Rd, Rm);
+				address, opcode, mnemonic, rd, rm);
 	else
 		snprintf(instruction->text, 128,
 				"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, r%i",
-				address, opcode, mnemonic, Rd, Rm);
+				address, opcode, mnemonic, rd, rm);
 
 	return ERROR_OK;
 }
@@ -2425,14 +2425,14 @@ static int evaluate_load_literal_thumb(uint16_t opcode,
 				       uint32_t address, struct arm_instruction *instruction)
 {
 	uint32_t immediate;
-	uint8_t Rd = (opcode >> 8) & 0x7;
+	uint8_t rd = (opcode >> 8) & 0x7;
 
 	instruction->type = ARM_LDR;
 	immediate = opcode & 0x000000ff;
 	immediate *= 4;
 
-	instruction->info.load_store.Rd = Rd;
-	instruction->info.load_store.Rn = 15 /*PC*/;
+	instruction->info.load_store.rd = rd;
+	instruction->info.load_store.rn = 15 /*PC*/;
 	instruction->info.load_store.index_mode = 0;	/*offset*/
 	instruction->info.load_store.offset_mode = 0;	/*immediate*/
 	instruction->info.load_store.offset.offset = immediate;
@@ -2440,7 +2440,7 @@ static int evaluate_load_literal_thumb(uint16_t opcode,
 	snprintf(instruction->text, 128,
 			"0x%8.8" PRIx32 "  0x%4.4x    \t"
 			"LDR\tr%i, [pc, #%#" PRIx32 "]\t; %#8.8" PRIx32,
-			address, opcode, Rd, immediate,
+			address, opcode, rd, immediate,
 			thumb_alignpc4(address) + immediate);
 
 	return ERROR_OK;
@@ -2449,9 +2449,9 @@ static int evaluate_load_literal_thumb(uint16_t opcode,
 static int evaluate_load_store_reg_thumb(uint16_t opcode,
 					 uint32_t address, struct arm_instruction *instruction)
 {
-	uint8_t Rd = (opcode >> 0) & 0x7;
-	uint8_t Rn = (opcode >> 3) & 0x7;
-	uint8_t Rm = (opcode >> 6) & 0x7;
+	uint8_t rd = (opcode >> 0) & 0x7;
+	uint8_t rn = (opcode >> 3) & 0x7;
+	uint8_t rm = (opcode >> 6) & 0x7;
 	uint8_t opc = (opcode >> 9) & 0x7;
 	char *mnemonic = NULL;
 
@@ -2492,13 +2492,13 @@ static int evaluate_load_store_reg_thumb(uint16_t opcode,
 
 	snprintf(instruction->text, 128,
 			"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, [r%i, r%i]",
-			address, opcode, mnemonic, Rd, Rn, Rm);
+			address, opcode, mnemonic, rd, rn, rm);
 
-	instruction->info.load_store.Rd = Rd;
-	instruction->info.load_store.Rn = Rn;
+	instruction->info.load_store.rd = rd;
+	instruction->info.load_store.rn = rn;
 	instruction->info.load_store.index_mode = 0;	/*offset*/
 	instruction->info.load_store.offset_mode = 1;	/*register*/
-	instruction->info.load_store.offset.reg.Rm = Rm;
+	instruction->info.load_store.offset.reg.rm = rm;
 
 	return ERROR_OK;
 }
@@ -2507,15 +2507,15 @@ static int evaluate_load_store_imm_thumb(uint16_t opcode,
 					 uint32_t address, struct arm_instruction *instruction)
 {
 	uint32_t offset = (opcode >> 6) & 0x1f;
-	uint8_t Rd = (opcode >> 0) & 0x7;
-	uint8_t Rn = (opcode >> 3) & 0x7;
-	uint32_t L = opcode & (1 << 11);
-	uint32_t B = opcode & (1 << 12);
+	uint8_t rd = (opcode >> 0) & 0x7;
+	uint8_t rn = (opcode >> 3) & 0x7;
+	uint32_t l = opcode & (1 << 11);
+	uint32_t b = opcode & (1 << 12);
 	char *mnemonic;
 	char suffix = ' ';
 	uint32_t shift = 2;
 
-	if (L) {
+	if (l) {
 		instruction->type = ARM_LDR;
 		mnemonic = "LDR";
 	} else {
@@ -2526,17 +2526,17 @@ static int evaluate_load_store_imm_thumb(uint16_t opcode,
 	if ((opcode&0xF000) == 0x8000) {
 		suffix = 'H';
 		shift = 1;
-	} else if (B) {
+	} else if (b) {
 		suffix = 'B';
 		shift = 0;
 	}
 
 	snprintf(instruction->text, 128,
 			"0x%8.8" PRIx32 "  0x%4.4x    \t%s%c\tr%i, [r%i, #%#" PRIx32 "]",
-			address, opcode, mnemonic, suffix, Rd, Rn, offset << shift);
+			address, opcode, mnemonic, suffix, rd, rn, offset << shift);
 
-	instruction->info.load_store.Rd = Rd;
-	instruction->info.load_store.Rn = Rn;
+	instruction->info.load_store.rd = rd;
+	instruction->info.load_store.rn = rn;
 	instruction->info.load_store.index_mode = 0;	/*offset*/
 	instruction->info.load_store.offset_mode = 0;	/*immediate*/
 	instruction->info.load_store.offset.offset = offset << shift;
@@ -2548,11 +2548,11 @@ static int evaluate_load_store_stack_thumb(uint16_t opcode,
 					   uint32_t address, struct arm_instruction *instruction)
 {
 	uint32_t offset = opcode  & 0xff;
-	uint8_t Rd = (opcode >> 8) & 0x7;
-	uint32_t L = opcode & (1 << 11);
+	uint8_t rd = (opcode >> 8) & 0x7;
+	uint32_t l = opcode & (1 << 11);
 	char *mnemonic;
 
-	if (L) {
+	if (l) {
 		instruction->type = ARM_LDR;
 		mnemonic = "LDR";
 	} else {
@@ -2562,10 +2562,10 @@ static int evaluate_load_store_stack_thumb(uint16_t opcode,
 
 	snprintf(instruction->text, 128,
 			"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, [SP, #%#" PRIx32 "]",
-			address, opcode, mnemonic, Rd, offset*4);
+			address, opcode, mnemonic, rd, offset*4);
 
-	instruction->info.load_store.Rd = Rd;
-	instruction->info.load_store.Rn = 13 /*SP*/;
+	instruction->info.load_store.rd = rd;
+	instruction->info.load_store.rn = 13 /*SP*/;
 	instruction->info.load_store.index_mode = 0;	/*offset*/
 	instruction->info.load_store.offset_mode = 0;	/*immediate*/
 	instruction->info.load_store.offset.offset = offset*4;
@@ -2577,28 +2577,28 @@ static int evaluate_add_sp_pc_thumb(uint16_t opcode,
 				    uint32_t address, struct arm_instruction *instruction)
 {
 	uint32_t imm = opcode  & 0xff;
-	uint8_t Rd = (opcode >> 8) & 0x7;
-	uint8_t Rn;
-	uint32_t SP = opcode & (1 << 11);
+	uint8_t rd = (opcode >> 8) & 0x7;
+	uint8_t rn;
+	uint32_t sp = opcode & (1 << 11);
 	const char *reg_name;
 
 	instruction->type = ARM_ADD;
 
-	if (SP) {
+	if (sp) {
 		reg_name = "SP";
-		Rn = 13;
+		rn = 13;
 	} else {
 		reg_name = "PC";
-		Rn = 15;
+		rn = 15;
 	}
 
 	snprintf(instruction->text, 128,
 			"0x%8.8" PRIx32 "  0x%4.4x  \tADD\tr%i, %s, #%#" PRIx32,
-			address, opcode, Rd, reg_name, imm * 4);
+			address, opcode, rd, reg_name, imm * 4);
 
 	instruction->info.data_proc.variant = 0	/* immediate */;
-	instruction->info.data_proc.Rd = Rd;
-	instruction->info.data_proc.Rn = Rn;
+	instruction->info.data_proc.rd = rd;
+	instruction->info.data_proc.rn = rn;
 	instruction->info.data_proc.shifter_operand.immediate.immediate = imm*4;
 
 	return ERROR_OK;
@@ -2625,8 +2625,8 @@ static int evaluate_adjust_stack_thumb(uint16_t opcode,
 			address, opcode, mnemonic, imm*4);
 
 	instruction->info.data_proc.variant = 0	/* immediate */;
-	instruction->info.data_proc.Rd = 13 /*SP*/;
-	instruction->info.data_proc.Rn = 13 /*SP*/;
+	instruction->info.data_proc.rd = 13 /*SP*/;
+	instruction->info.data_proc.rn = 13 /*SP*/;
 	instruction->info.data_proc.shifter_operand.immediate.immediate = imm*4;
 
 	return ERROR_OK;
@@ -2650,9 +2650,9 @@ static int evaluate_load_store_multiple_thumb(uint16_t opcode,
 					      uint32_t address, struct arm_instruction *instruction)
 {
 	uint32_t reg_list = opcode  & 0xff;
-	uint32_t L = opcode & (1 << 11);
-	uint32_t R = opcode & (1 << 8);
-	uint8_t Rn = (opcode >> 8) & 7;
+	uint32_t l = opcode & (1 << 11);
+	uint32_t r = opcode & (1 << 8);
+	uint8_t rn = (opcode >> 8) & 7;
 	uint8_t addr_mode = 0 /* IA */;
 	char reg_names[40];
 	char *reg_names_p;
@@ -2667,28 +2667,28 @@ static int evaluate_load_store_multiple_thumb(uint16_t opcode,
 	if ((opcode & 0xf000) == 0xc000) {	/* generic load/store multiple */
 		char *wback = "!";
 
-		if (L) {
+		if (l) {
 			instruction->type = ARM_LDM;
 			mnemonic = "LDM";
-			if (opcode & (1 << Rn))
+			if (opcode & (1 << rn))
 				wback = "";
 		} else {
 			instruction->type = ARM_STM;
 			mnemonic = "STM";
 		}
-		snprintf(ptr_name, sizeof(ptr_name), "r%i%s, ", Rn, wback);
+		snprintf(ptr_name, sizeof(ptr_name), "r%i%s, ", rn, wback);
 	} else {/* push/pop */
-		Rn = 13;/* SP */
-		if (L) {
+		rn = 13;/* SP */
+		if (l) {
 			instruction->type = ARM_LDM;
 			mnemonic = "POP";
-			if (R)
+			if (r)
 				reg_list |= (1 << 15) /*PC*/;
 		} else {
 			instruction->type = ARM_STM;
 			mnemonic = "PUSH";
 			addr_mode = 3;	/*DB*/
-			if (R)
+			if (r)
 				reg_list |= (1 << 14) /*LR*/;
 		}
 	}
@@ -2711,7 +2711,7 @@ static int evaluate_load_store_multiple_thumb(uint16_t opcode,
 			address, opcode, mnemonic, ptr_name, reg_names);
 
 	instruction->info.load_store_multiple.register_list = reg_list;
-	instruction->info.load_store_multiple.Rn = Rn;
+	instruction->info.load_store_multiple.rn = rn;
 	instruction->info.load_store_multiple.addressing_mode = addr_mode;
 
 	return ERROR_OK;
diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h
index beecb3f..6f15f4b 100644
--- a/src/target/arm_disassembler.h
+++ b/src/target/arm_disassembler.h
@@ -112,11 +112,11 @@ enum arm_instruction_type {
 	ARM_QDADD,
 	ARM_QSUB,
 	ARM_QDSUB,
-	ARM_SMLAxy,
-	ARM_SMLALxy,
-	ARM_SMLAWy,
-	ARM_SMULxy,
-	ARM_SMULWy,
+	ARM_SMLAXY,
+	ARM_SMLALXY,
+	ARM_SMLAWY,
+	ARM_SMULXY,
+	ARM_SMULWY,
 	ARM_LDRD,
 	ARM_STRD,
 
@@ -133,35 +133,35 @@ union arm_shifter_operand {
 		uint32_t immediate;
 	} immediate;
 	struct {
-		uint8_t Rm;
+		uint8_t rm;
 		uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
 		uint8_t shift_imm;
 	} immediate_shift;
 	struct {
-		uint8_t Rm;
+		uint8_t rm;
 		uint8_t shift;
-		uint8_t Rs;
+		uint8_t rs;
 	} register_shift;
 };
 
 struct arm_data_proc_instr {
 	int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
-	uint8_t S;
-	uint8_t Rn;
-	uint8_t Rd;
+	uint8_t s;
+	uint8_t rn;
+	uint8_t rd;
 	union arm_shifter_operand shifter_operand;
 };
 
 struct arm_load_store_instr {
-	uint8_t Rd;
-	uint8_t Rn;
-	uint8_t U;
+	uint8_t rd;
+	uint8_t rn;
+	uint8_t u;
 	int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
 	int offset_mode; /* 0: immediate, 1: (scaled) register */
 	union {
 		uint32_t offset;
 		struct {
-			uint8_t Rm;
+			uint8_t rm;
 			uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
 			uint8_t shift_imm;
 		} reg;
@@ -169,11 +169,11 @@ struct arm_load_store_instr {
 };
 
 struct arm_load_store_multiple_instr {
-	uint8_t Rn;
+	uint8_t rn;
 	uint32_t register_list;
 	uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
-	uint8_t S;
-	uint8_t W;
+	uint8_t s;
+	uint8_t w;
 };
 
 struct arm_instruction {
diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h
index 90f8416..00035f5 100644
--- a/src/target/arm_opcodes.h
+++ b/src/target/arm_opcodes.h
@@ -36,184 +36,184 @@
 /* ARM mode instructions */
 
 /* Store multiple increment after
- * Rn: base register
- * List: for each bit in list: store register
- * S: in privileged mode: store user-mode registers
- * W = 1: update the base register. W = 0: leave the base register untouched
+ * rn: base register
+ * list: for each bit in list: store register
+ * s: in privileged mode: store user-mode registers
+ * w = 1: update the base register. w = 0: leave the base register untouched
  */
-#define ARMV4_5_STMIA(Rn, List, S, W) \
-	(0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
+#define ARMV4_5_STMIA(rn, list, s, w) \
+	(0xe8800000 | ((s) << 22) | ((w) << 21) | ((rn) << 16) | (list))
 
 /* Load multiple increment after
- * Rn: base register
- * List: for each bit in list: store register
- * S: in privileged mode: store user-mode registers
- * W = 1: update the base register. W = 0: leave the base register untouched
+ * rn: base register
+ * list: for each bit in list: store register
+ * s: in privileged mode: store user-mode registers
+ * w = 1: update the base register. w = 0: leave the base register untouched
  */
-#define ARMV4_5_LDMIA(Rn, List, S, W) \
-	(0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
+#define ARMV4_5_LDMIA(rn, list, s, w) \
+	(0xe8900000 | ((s) << 22) | ((w) << 21) | ((rn) << 16) | (list))
 
 /* MOV r8, r8 */
 #define ARMV4_5_NOP					(0xe1a08008)
 
 /* Move PSR to general purpose register
- * R = 1: SPSR R = 0: CPSR
- * Rn: target register
+ * r = 1: SPSR r = 0: CPSR
+ * rn: target register
  */
-#define ARMV4_5_MRS(Rn, R)	(0xe10f0000 | ((R) << 22) | ((Rn) << 12))
+#define ARMV4_5_MRS(rn, r)	(0xe10f0000 | ((r) << 22) | ((rn) << 12))
 
 /* Store register
- * Rd: register to store
- * Rn: base register
+ * rd: register to store
+ * rn: base register
  */
-#define ARMV4_5_STR(Rd, Rn)	(0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
+#define ARMV4_5_STR(rd, rn)	(0xe5800000 | ((rd) << 12) | ((rn) << 16))
 
 /* Load register
- * Rd: register to load
- * Rn: base register
+ * rd: register to load
+ * rn: base register
  */
-#define ARMV4_5_LDR(Rd, Rn)	(0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
+#define ARMV4_5_LDR(rd, rn)	(0xe5900000 | ((rd) << 12) | ((rn) << 16))
 
 /* Move general purpose register to PSR
- * R = 1: SPSR R = 0: CPSR
- * Field: Field mask
+ * r = 1: SPSR r = 0: CPSR
+ * field: Field mask
  * 1: control field 2: extension field 4: status field 8: flags field
- * Rm: source register
+ * rm: source register
  */
-#define ARMV4_5_MSR_GP(Rm, Field, R) \
-	(0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
-#define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \
-	(0xe320f000 | (Im)  | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
+#define ARMV4_5_MSR_GP(rm, field, r) \
+	(0xe120f000 | (rm) | ((field) << 16) | ((r) << 22))
+#define ARMV4_5_MSR_IM(im, rotate, field, r) \
+	(0xe320f000 | (im)  | ((rotate) << 8) | ((field) << 16) | ((r) << 22))
 
 /* Load Register Word Immediate Post-Index
- * Rd: register to load
- * Rn: base register
+ * rd: register to load
+ * rn: base register
  */
-#define ARMV4_5_LDRW_IP(Rd, Rn)	(0xe4900004 | ((Rd) << 12) | ((Rn) << 16))
+#define ARMV4_5_LDRW_IP(rd, rn)	(0xe4900004 | ((rd) << 12) | ((rn) << 16))
 
 /* Load Register Halfword Immediate Post-Index
- * Rd: register to load
- * Rn: base register
+ * rd: register to load
+ * rn: base register
  */
-#define ARMV4_5_LDRH_IP(Rd, Rn)	(0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
+#define ARMV4_5_LDRH_IP(rd, rn)	(0xe0d000b2 | ((rd) << 12) | ((rn) << 16))
 
 /* Load Register Byte Immediate Post-Index
- * Rd: register to load
- * Rn: base register
+ * rd: register to load
+ * rn: base register
  */
-#define ARMV4_5_LDRB_IP(Rd, Rn)	(0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
+#define ARMV4_5_LDRB_IP(rd, rn)	(0xe4d00001 | ((rd) << 12) | ((rn) << 16))
 
 /* Store register Word Immediate Post-Index
- * Rd: register to store
- * Rn: base register
+ * rd: register to store
+ * rn: base register
  */
-#define ARMV4_5_STRW_IP(Rd, Rn)	(0xe4800004 | ((Rd) << 12) | ((Rn) << 16))
+#define ARMV4_5_STRW_IP(rd, rn)	(0xe4800004 | ((rd) << 12) | ((rn) << 16))
 
 /* Store register Halfword Immediate Post-Index
- * Rd: register to store
- * Rn: base register
+ * rd: register to store
+ * rn: base register
  */
-#define ARMV4_5_STRH_IP(Rd, Rn)	(0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
+#define ARMV4_5_STRH_IP(rd, rn)	(0xe0c000b2 | ((rd) << 12) | ((rn) << 16))
 
 /* Store register Byte Immediate Post-Index
- * Rd: register to store
- * Rn: base register
+ * rd: register to store
+ * rn: base register
  */
-#define ARMV4_5_STRB_IP(Rd, Rn)	(0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
+#define ARMV4_5_STRB_IP(rd, rn)	(0xe4c00001 | ((rd) << 12) | ((rn) << 16))
 
 /* Branch (and Link)
- * Im: Branch target (left-shifted by 2 bits, added to PC)
- * L: 1: branch and link 0: branch only
+ * im: Branch target (left-shifted by 2 bits, added to PC)
+ * l: 1: branch and link 0: branch only
  */
-#define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
+#define ARMV4_5_B(im, l) (0xea000000 | (im) | ((l) << 24))
 
 /* Branch and exchange (ARM state)
- * Rm: register holding branch target address
+ * rm: register holding branch target address
  */
-#define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
+#define ARMV4_5_BX(rm) (0xe12fff10 | (rm))
 
 /* Copies two words from two ARM core registers
  * into a doubleword extension register, or
  * from a doubleword extension register to two ARM core registers.
  * See Armv7-A arch reference manual section A8.8.345
- * Rt:   Arm core register 1
- * Rt2:  Arm core register 2
- * Vm:   The doubleword extension register
- * M:    m = UInt(M:Vm);
+ * rt:   Arm core register 1
+ * rt2:  Arm core register 2
+ * vm:   The doubleword extension register
+ * m:    m = UInt(m:vm);
  * op:   to_arm_registers = (op == ‘1’);
  */
-#define ARMV4_5_VMOV(op, Rt2, Rt, M, Vm) \
-	(0xec400b10 | ((op) << 20) | ((Rt2) << 16) | \
-	((Rt) << 12) | ((M) << 5) | (Vm))
+#define ARMV4_5_VMOV(op, rt2, rt, m, vm) \
+	(0xec400b10 | ((op) << 20) | ((rt2) << 16) | \
+	((rt) << 12) | ((m) << 5) | (vm))
 
 /* Moves the value of the FPSCR to an ARM core register
- * Rt: Arm core register
+ * rt: Arm core register
  */
-#define ARMV4_5_VMRS(Rt) (0xeef10a10 | ((Rt) << 12))
+#define ARMV4_5_VMRS(rt) (0xeef10a10 | ((rt) << 12))
 
 /* Moves the value of an ARM core register to the FPSCR.
- * Rt: Arm core register
+ * rt: Arm core register
  */
-#define ARMV4_5_VMSR(Rt) (0xeee10a10 | ((Rt) << 12))
+#define ARMV4_5_VMSR(rt) (0xeee10a10 | ((rt) << 12))
 
 /* Store data from coprocessor to consecutive memory
  * See Armv7-A arch doc section A8.6.187
- * P:    1=index mode (offset from Rn)
- * U:    1=add, 0=subtract  Rn address with imm
- * D:    Opcode D encoding
- * W:    write back the offset start address to the Rn register
- * CP:   Coprocessor number (4 bits)
- * CRd:  Coprocessor source register (4 bits)
- * Rn:   Base register for memory address (4 bits)
+ * p:    1=index mode (offset from rn)
+ * u:    1=add, 0=subtract  rn address with imm
+ * d:    Opcode D encoding
+ * w:    write back the offset start address to the rn register
+ * cp:   Coprocessor number (4 bits)
+ * crd:  Coprocessor source register (4 bits)
+ * rn:   Base register for memory address (4 bits)
  * imm:  Immediate value (0 - 1020, must be divisible by 4)
  */
-#define ARMV4_5_STC(P, U, D, W, CP, CRd, Rn, imm) \
-	(0xec000000 | ((P) << 24) | ((U) << 23) | ((D) << 22) | \
-	((W) << 21) | ((Rn) << 16) | ((CRd) << 12) | ((CP) << 8) | ((imm)>>2))
+#define ARMV4_5_STC(p, u, d, w, cp, crd, rn, imm) \
+	(0xec000000 | ((p) << 24) | ((u) << 23) | ((d) << 22) | \
+	((w) << 21) | ((rn) << 16) | ((crd) << 12) | ((cp) << 8) | ((imm)>>2))
 
 /* Loads data from consecutive memory to coprocessor
  * See Armv7-A arch doc section A8.6.51
- * P:    1=index mode (offset from Rn)
- * U:    1=add, 0=subtract  Rn address with imm
- * D:    Opcode D encoding
- * W:    write back the offset start address to the Rn register
- * CP:   Coprocessor number (4 bits)
- * CRd:  Coprocessor dest register (4 bits)
- * Rn:   Base register for memory address (4 bits)
+ * p:    1=index mode (offset from rn)
+ * u:    1=add, 0=subtract  rn address with imm
+ * d:    Opcode D encoding
+ * w:    write back the offset start address to the rn register
+ * cp:   Coprocessor number (4 bits)
+ * crd:  Coprocessor dest register (4 bits)
+ * rn:   Base register for memory address (4 bits)
  * imm:  Immediate value (0 - 1020, must be divisible by 4)
  */
-#define ARMV4_5_LDC(P, U, D, W, CP, CRd, Rn, imm) \
-	(0xec100000 | ((P) << 24) | ((U) << 23) | ((D) << 22) | \
-	((W) << 21) | ((Rn) << 16) | ((CRd) << 12) | ((CP) << 8) | ((imm) >> 2))
+#define ARMV4_5_LDC(p, u, d, w, cp, crd, rn, imm) \
+	(0xec100000 | ((p) << 24) | ((u) << 23) | ((d) << 22) | \
+	((w) << 21) | ((rn) << 16) | ((crd) << 12) | ((cp) << 8) | ((imm) >> 2))
 
 /* Move to ARM register from coprocessor
- * CP: Coprocessor number
+ * cp: Coprocessor number
  * op1: Coprocessor opcode
- * Rd: destination register
- * CRn: first coprocessor operand
- * CRm: second coprocessor operand
+ * rd: destination register
+ * crn: first coprocessor operand
+ * crm: second coprocessor operand
  * op2: Second coprocessor opcode
  */
-#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) \
-	(0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
-	| ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
+#define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2) \
+	(0xee100010 | (crm) | ((op2) << 5) | ((cp) << 8) \
+	| ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
 
 /* Move to coprocessor from ARM register
- * CP: Coprocessor number
+ * cp: Coprocessor number
  * op1: Coprocessor opcode
- * Rd: destination register
- * CRn: first coprocessor operand
- * CRm: second coprocessor operand
+ * rd: destination register
+ * crn: first coprocessor operand
+ * crm: second coprocessor operand
  * op2: Second coprocessor opcode
  */
-#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) \
-	(0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
-	| ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
+#define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2) \
+	(0xee000010 | (crm) | ((op2) << 5) | ((cp) << 8) \
+	| ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
 
 /* Breakpoint instruction (ARMv5)
- * Im: 16-bit immediate
+ * im: 16-bit immediate
  */
-#define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 4) | (Im & 0xf))
+#define ARMV5_BKPT(im) (0xe1200070 | ((im & 0xfff0) << 4) | (im & 0xf))
 
 
 /* Thumb mode instructions
@@ -228,45 +228,45 @@
  */
 
 /* Store register (Thumb mode)
- * Rd: source register
- * Rn: base register
+ * rd: source register
+ * rn: base register
  */
-#define ARMV4_5_T_STR(Rd, Rn) \
-	((0x6000 | (Rd) | ((Rn) << 3)) | \
-	((0x6000 | (Rd) | ((Rn) << 3)) << 16))
+#define ARMV4_5_T_STR(rd, rn) \
+	((0x6000 | (rd) | ((rn) << 3)) | \
+	((0x6000 | (rd) | ((rn) << 3)) << 16))
 
 /* Load register (Thumb state)
- * Rd: destination register
- * Rn: base register
+ * rd: destination register
+ * rn: base register
  */
-#define ARMV4_5_T_LDR(Rd, Rn) \
-	((0x6800 | ((Rn) << 3) | (Rd)) \
-	| ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
+#define ARMV4_5_T_LDR(rd, rn) \
+	((0x6800 | ((rn) << 3) | (rd)) \
+	| ((0x6800 | ((rn) << 3) | (rd)) << 16))
 
 /* Load multiple (Thumb state)
- * Rn: base register
- * List: for each bit in list: store register
+ * rn: base register
+ * list: for each bit in list: store register
  */
-#define ARMV4_5_T_LDMIA(Rn, List) \
-	((0xc800 | ((Rn) << 8) | (List)) \
-	| ((0xc800 | ((Rn) << 8) | (List)) << 16))
+#define ARMV4_5_T_LDMIA(rn, list) \
+	((0xc800 | ((rn) << 8) | (list)) \
+	| ((0xc800 | ((rn) << 8) | (list)) << 16))
 
 /* Load register with PC relative addressing
- * Rd: register to load
+ * rd: register to load
  */
-#define ARMV4_5_T_LDR_PCREL(Rd) \
-	((0x4800 | ((Rd) << 8)) \
-	| ((0x4800 | ((Rd) << 8)) << 16))
+#define ARMV4_5_T_LDR_PCREL(rd) \
+	((0x4800 | ((rd) << 8)) \
+	| ((0x4800 | ((rd) << 8)) << 16))
 
 /* Move hi register (Thumb mode)
- * Rd: destination register
- * Rm: source register
+ * rd: destination register
+ * rm: source register
  */
-#define ARMV4_5_T_MOV(Rd, Rm) \
-	((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
-		(((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) \
-	| ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
-		(((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
+#define ARMV4_5_T_MOV(rd, rm) \
+	((0x4600 | ((rd) & 0x7) | (((rd) & 0x8) << 4) | \
+		(((rm) & 0x7) << 3) | (((rm) & 0x8) << 3)) \
+	| ((0x4600 | ((rd) & 0x7) | (((rd) & 0x8) << 4) | \
+		(((rm) & 0x7) << 3) | (((rm) & 0x8) << 3)) << 16))
 
 /* No operation (Thumb mode)
  * NOTE:  this is "MOV r8, r8" ... Thumb2 adds two
@@ -275,63 +275,63 @@
 #define ARMV4_5_T_NOP	(0x46c0 | (0x46c0 << 16))
 
 /* Move immediate to register (Thumb state)
- * Rd: destination register
- * Im: 8-bit immediate value
+ * rd: destination register
+ * im: 8-bit immediate value
  */
-#define ARMV4_5_T_MOV_IM(Rd, Im) \
-	((0x2000 | ((Rd) << 8) | (Im)) \
-	| ((0x2000 | ((Rd) << 8) | (Im)) << 16))
+#define ARMV4_5_T_MOV_IM(rd, im) \
+	((0x2000 | ((rd) << 8) | (im)) \
+	| ((0x2000 | ((rd) << 8) | (im)) << 16))
 
 /* Branch and Exchange
- * Rm: register containing branch target
+ * rm: register containing branch target
  */
-#define ARMV4_5_T_BX(Rm) \
-	((0x4700 | ((Rm) << 3)) \
-	| ((0x4700 | ((Rm) << 3)) << 16))
+#define ARMV4_5_T_BX(rm) \
+	((0x4700 | ((rm) << 3)) \
+	| ((0x4700 | ((rm) << 3)) << 16))
 
 /* Branch (Thumb state)
- * Imm: Branch target
+ * imm: Branch target
  */
-#define ARMV4_5_T_B(Imm) \
-	((0xe000 | (Imm)) \
-	| ((0xe000 | (Imm)) << 16))
+#define ARMV4_5_T_B(imm) \
+	((0xe000 | (imm)) \
+	| ((0xe000 | (imm)) << 16))
 
 /* Breakpoint instruction (ARMv5) (Thumb state)
  * Im: 8-bit immediate
  */
-#define ARMV5_T_BKPT(Im) \
-	((0xbe00 | (Im)) \
-	| ((0xbe00 | (Im)) << 16))
+#define ARMV5_T_BKPT(im) \
+	((0xbe00 | (im)) \
+	| ((0xbe00 | (im)) << 16))
 
 /* Move to Register from Special Register
  *	32 bit Thumb2 instruction
- * Rd: destination register
- * SYSm: source special register
+ * rd: destination register
+ * sysm: source special register
  */
-#define ARM_T2_MRS(Rd, SYSm) \
-	((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
+#define ARM_T2_MRS(rd, sysm) \
+	((0xF3EF) | ((0x8000 | (rd << 8) | sysm) << 16))
 
 /* Move from Register from Special Register
  *	32 bit Thumb2 instruction
- * Rd: source register
- * SYSm: destination special register
+ * rd: source register
+ * sysm: destination special register
  */
-#define ARM_T2_MSR(SYSm, Rn) \
-	((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16))
+#define ARM_T2_MSR(sysm, rn) \
+	((0xF380 | (rn << 8)) | ((0x8800 | sysm) << 16))
 
 /* Change Processor State.
  *	16 bit Thumb2 instruction
- * Rd: source register
+ * rd: source register
  * IF: A_FLAG and/or I_FLAG and/or F_FLAG
  */
 #define A_FLAG 4
 #define I_FLAG 2
 #define F_FLAG 1
-#define ARM_T2_CPSID(IF) \
-	((0xB660 | (1 << 8) | ((IF)&0x3)) \
-	| ((0xB660 | (1 << 8) | ((IF)&0x3)) << 16))
-#define ARM_T2_CPSIE(IF) \
-	((0xB660 | (0 << 8) | ((IF)&0x3)) \
-	| ((0xB660 | (0 << 8) | ((IF)&0x3)) << 16))
+#define ARM_T2_CPSID(_if) \
+	((0xB660 | (1 << 8) | ((_if)&0x3)) \
+	| ((0xB660 | (1 << 8) | ((_if)&0x3)) << 16))
+#define ARM_T2_CPSIE(_if) \
+	((0xB660 | (0 << 8) | ((_if)&0x3)) \
+	| ((0xB660 | (0 << 8) | ((_if)&0x3)) << 16))
 
 #endif /* OPENOCD_TARGET_ARM_OPCODES_H */
diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index 245e108..480d9bc 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -31,7 +31,7 @@
 #include "register.h"
 #include <helper/log.h>
 
-static uint32_t arm_shift(uint8_t shift, uint32_t Rm,
+static uint32_t arm_shift(uint8_t shift, uint32_t rm,
 	uint32_t shift_amount, uint8_t *carry)
 {
 	uint32_t return_value = 0;
@@ -39,22 +39,22 @@ static uint32_t arm_shift(uint8_t shift, uint32_t Rm,
 
 	if (shift == 0x0) {	/* LSL */
 		if ((shift_amount > 0) && (shift_amount <= 32)) {
-			return_value = Rm << shift_amount;
-			*carry = Rm >> (32 - shift_amount);
+			return_value = rm << shift_amount;
+			*carry = rm >> (32 - shift_amount);
 		} else if (shift_amount > 32) {
 			return_value = 0x0;
 			*carry = 0x0;
 		} else /* (shift_amount == 0) */
-			return_value = Rm;
+			return_value = rm;
 	} else if (shift == 0x1) {	/* LSR */
 		if ((shift_amount > 0) && (shift_amount <= 32)) {
-			return_value = Rm >> shift_amount;
-			*carry = (Rm >> (shift_amount - 1)) & 1;
+			return_value = rm >> shift_amount;
+			*carry = (rm >> (shift_amount - 1)) & 1;
 		} else if (shift_amount > 32) {
 			return_value = 0x0;
 			*carry = 0x0;
 		} else /* (shift_amount == 0) */
-			return_value = Rm;
+			return_value = rm;
 	} else if (shift == 0x2) {	/* ASR */
 		if ((shift_amount > 0) && (shift_amount <= 32)) {
 			/* C right shifts of unsigned values are guaranteed to
@@ -62,11 +62,11 @@ static uint32_t arm_shift(uint8_t shift, uint32_t Rm,
 			 * shift (shift in signed-bit) by adding the sign bit
 			 * manually
 			 */
-			return_value = Rm >> shift_amount;
-			if (Rm & 0x80000000)
+			return_value = rm >> shift_amount;
+			if (rm & 0x80000000)
 				return_value |= 0xffffffff << (32 - shift_amount);
 		} else if (shift_amount > 32) {
-			if (Rm & 0x80000000) {
+			if (rm & 0x80000000) {
 				return_value = 0xffffffff;
 				*carry = 0x1;
 			} else {
@@ -74,20 +74,20 @@ static uint32_t arm_shift(uint8_t shift, uint32_t Rm,
 				*carry = 0x0;
 			}
 		} else /* (shift_amount == 0) */
-			return_value = Rm;
+			return_value = rm;
 	} else if (shift == 0x3) {	/* ROR */
 		if (shift_amount == 0)
-			return_value = Rm;
+			return_value = rm;
 		else {
 			shift_amount = shift_amount % 32;
-			return_value = (Rm >> shift_amount) | (Rm << (32 - shift_amount));
+			return_value = (rm >> shift_amount) | (rm << (32 - shift_amount));
 			*carry = (return_value >> 31) & 0x1;
 		}
 	} else if (shift == 0x4) {	/* RRX */
-		return_value = Rm >> 1;
+		return_value = rm >> 1;
 		if (*carry)
-			Rm |= 0x80000000;
-		*carry = Rm & 0x1;
+			rm |= 0x80000000;
+		*carry = rm & 0x1;
 	}
 
 	return return_value;
@@ -111,25 +111,25 @@ static uint32_t arm_shifter_operand(struct arm_sim_interface *sim,
 	if (variant == 0) /* 32-bit immediate */
 		return_value = shifter_operand.immediate.immediate;
 	else if (variant == 1) {/* immediate shift */
-		uint32_t Rm = sim->get_reg_mode(sim, shifter_operand.immediate_shift.Rm);
+		uint32_t rm = sim->get_reg_mode(sim, shifter_operand.immediate_shift.rm);
 
 		/* adjust RM in case the PC is being read */
-		if (shifter_operand.immediate_shift.Rm == 15)
-			Rm += 2 * instruction_size;
+		if (shifter_operand.immediate_shift.rm == 15)
+			rm += 2 * instruction_size;
 
 		return_value = arm_shift(shifter_operand.immediate_shift.shift,
-				Rm, shifter_operand.immediate_shift.shift_imm,
+				rm, shifter_operand.immediate_shift.shift_imm,
 				shifter_carry_out);
 	} else if (variant == 2) {	/* register shift */
-		uint32_t Rm = sim->get_reg_mode(sim, shifter_operand.register_shift.Rm);
-		uint32_t Rs = sim->get_reg_mode(sim, shifter_operand.register_shift.Rs);
+		uint32_t rm = sim->get_reg_mode(sim, shifter_operand.register_shift.rm);
+		uint32_t rs = sim->get_reg_mode(sim, shifter_operand.register_shift.rs);
 
 		/* adjust RM in case the PC is being read */
-		if (shifter_operand.register_shift.Rm == 15)
-			Rm += 2 * instruction_size;
+		if (shifter_operand.register_shift.rm == 15)
+			rm += 2 * instruction_size;
 
 		return_value = arm_shift(shifter_operand.immediate_shift.shift,
-				Rm, Rs, shifter_carry_out);
+				rm, rs, shifter_carry_out);
 	} else {
 		LOG_ERROR("BUG: shifter_operand.variant not 0, 1 or 2");
 		return_value = 0xffffffff;
@@ -324,8 +324,8 @@ static int arm_simulate_step_core(struct target *target,
 				sim->set_reg(sim, 15, target_address);
 			else if (instruction.type == ARM_BL) {
 				uint32_t old_pc = sim->get_reg(sim, 15);
-				int T = (sim->get_state(sim) == ARM_STATE_THUMB);
-				sim->set_reg_mode(sim, 14, old_pc + 4 + T);
+				int t = (sim->get_state(sim) == ARM_STATE_THUMB);
+				sim->set_reg_mode(sim, 14, old_pc + 4 + t);
 				sim->set_reg(sim, 15, target_address);
 			} else if (instruction.type == ARM_BX) {
 				if (target_address & 0x1)
@@ -335,8 +335,8 @@ static int arm_simulate_step_core(struct target *target,
 				sim->set_reg(sim, 15, target_address & 0xfffffffe);
 			} else if (instruction.type == ARM_BLX) {
 				uint32_t old_pc = sim->get_reg(sim, 15);
-				int T = (sim->get_state(sim) == ARM_STATE_THUMB);
-				sim->set_reg_mode(sim, 14, old_pc + 4 + T);
+				int t = (sim->get_state(sim) == ARM_STATE_THUMB);
+				sim->set_reg_mode(sim, 14, old_pc + 4 + t);
 
 				if (target_address & 0x1)
 					sim->set_state(sim, ARM_STATE_THUMB);
@@ -351,16 +351,16 @@ static int arm_simulate_step_core(struct target *target,
 	/* data processing instructions, except compare instructions (CMP, CMN, TST, TEQ) */
 	else if (((instruction.type >= ARM_AND) && (instruction.type <= ARM_RSC))
 		|| ((instruction.type >= ARM_ORR) && (instruction.type <= ARM_MVN))) {
-		uint32_t Rd, Rn, shifter_operand;
-		uint8_t C = sim->get_cpsr(sim, 29, 1);
+		uint32_t rd, rn, shifter_operand;
+		uint8_t c = sim->get_cpsr(sim, 29, 1);
 		uint8_t carry_out;
 
-		Rd = 0x0;
+		rd = 0x0;
 		/* ARM_MOV and ARM_MVN does not use Rn */
 		if ((instruction.type != ARM_MOV) && (instruction.type != ARM_MVN))
-			Rn = sim->get_reg_mode(sim, instruction.info.data_proc.Rn);
+			rn = sim->get_reg_mode(sim, instruction.info.data_proc.rn);
 		else
-			Rn = 0;
+			rn = 0;
 
 		shifter_operand = arm_shifter_operand(sim,
 				instruction.info.data_proc.variant,
@@ -368,53 +368,53 @@ static int arm_simulate_step_core(struct target *target,
 				&carry_out);
 
 		/* adjust Rn in case the PC is being read */
-		if (instruction.info.data_proc.Rn == 15)
-			Rn += 2 * instruction_size;
+		if (instruction.info.data_proc.rn == 15)
+			rn += 2 * instruction_size;
 
 		if (instruction.type == ARM_AND)
-			Rd = Rn & shifter_operand;
+			rd = rn & shifter_operand;
 		else if (instruction.type == ARM_EOR)
-			Rd = Rn ^ shifter_operand;
+			rd = rn ^ shifter_operand;
 		else if (instruction.type == ARM_SUB)
-			Rd = Rn - shifter_operand;
+			rd = rn - shifter_operand;
 		else if (instruction.type == ARM_RSB)
-			Rd = shifter_operand - Rn;
+			rd = shifter_operand - rn;
 		else if (instruction.type == ARM_ADD)
-			Rd = Rn + shifter_operand;
+			rd = rn + shifter_operand;
 		else if (instruction.type == ARM_ADC)
-			Rd = Rn + shifter_operand + (C & 1);
+			rd = rn + shifter_operand + (c & 1);
 		else if (instruction.type == ARM_SBC)
-			Rd = Rn - shifter_operand - (C & 1) ? 0 : 1;
+			rd = rn - shifter_operand - (c & 1) ? 0 : 1;
 		else if (instruction.type == ARM_RSC)
-			Rd = shifter_operand - Rn - (C & 1) ? 0 : 1;
+			rd = shifter_operand - rn - (c & 1) ? 0 : 1;
 		else if (instruction.type == ARM_ORR)
-			Rd = Rn | shifter_operand;
+			rd = rn | shifter_operand;
 		else if (instruction.type == ARM_BIC)
-			Rd = Rn & ~(shifter_operand);
+			rd = rn & ~(shifter_operand);
 		else if (instruction.type == ARM_MOV)
-			Rd = shifter_operand;
+			rd = shifter_operand;
 		else if (instruction.type == ARM_MVN)
-			Rd = ~shifter_operand;
+			rd = ~shifter_operand;
 		else
 			LOG_WARNING("unhandled instruction type");
 
 		if (dry_run_pc) {
-			if (instruction.info.data_proc.Rd == 15)
-				*dry_run_pc = Rd & ~1;
+			if (instruction.info.data_proc.rd == 15)
+				*dry_run_pc = rd & ~1;
 			else
 				*dry_run_pc = current_pc + instruction_size;
 
 			return ERROR_OK;
 		} else {
-			if (instruction.info.data_proc.Rd == 15) {
-				sim->set_reg_mode(sim, 15, Rd & ~1);
-				if (Rd & 1)
+			if (instruction.info.data_proc.rd == 15) {
+				sim->set_reg_mode(sim, 15, rd & ~1);
+				if (rd & 1)
 					sim->set_state(sim, ARM_STATE_THUMB);
 				else
 					sim->set_state(sim, ARM_STATE_ARM);
 				return ERROR_OK;
 			}
-			sim->set_reg_mode(sim, instruction.info.data_proc.Rd, Rd);
+			sim->set_reg_mode(sim, instruction.info.data_proc.rd, rd);
 			LOG_WARNING("no updating of flags yet");
 		}
 	}
@@ -429,31 +429,31 @@ static int arm_simulate_step_core(struct target *target,
 	/* load register instructions */
 	else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH)) {
 		uint32_t load_address = 0, modified_address = 0, load_value = 0;
-		uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store.Rn);
+		uint32_t rn = sim->get_reg_mode(sim, instruction.info.load_store.rn);
 
 		/* adjust Rn in case the PC is being read */
-		if (instruction.info.load_store.Rn == 15)
-			Rn += 2 * instruction_size;
+		if (instruction.info.load_store.rn == 15)
+			rn += 2 * instruction_size;
 
 		if (instruction.info.load_store.offset_mode == 0) {
-			if (instruction.info.load_store.U)
-				modified_address = Rn + instruction.info.load_store.offset.offset;
+			if (instruction.info.load_store.u)
+				modified_address = rn + instruction.info.load_store.offset.offset;
 			else
-				modified_address = Rn - instruction.info.load_store.offset.offset;
+				modified_address = rn - instruction.info.load_store.offset.offset;
 		} else if (instruction.info.load_store.offset_mode == 1) {
 			uint32_t offset;
-			uint32_t Rm = sim->get_reg_mode(sim,
-					instruction.info.load_store.offset.reg.Rm);
+			uint32_t rm = sim->get_reg_mode(sim,
+					instruction.info.load_store.offset.reg.rm);
 			uint8_t shift = instruction.info.load_store.offset.reg.shift;
 			uint8_t shift_imm = instruction.info.load_store.offset.reg.shift_imm;
 			uint8_t carry = sim->get_cpsr(sim, 29, 1);
 
-			offset = arm_shift(shift, Rm, shift_imm, &carry);
+			offset = arm_shift(shift, rm, shift_imm, &carry);
 
-			if (instruction.info.load_store.U)
-				modified_address = Rn + offset;
+			if (instruction.info.load_store.u)
+				modified_address = rn + offset;
 			else
-				modified_address = Rn - offset;
+				modified_address = rn - offset;
 		} else
 			LOG_ERROR("BUG: offset_mode neither 0 (offset) nor 1 (scaled register)");
 
@@ -463,7 +463,7 @@ static int arm_simulate_step_core(struct target *target,
 			 * the base address register
 			 */
 			load_address = modified_address;
-			modified_address = Rn;
+			modified_address = rn;
 		} else if (instruction.info.load_store.index_mode == 1) {
 			/* pre-indexed mode
 			 * we load from the modified address, and write it
@@ -475,17 +475,17 @@ static int arm_simulate_step_core(struct target *target,
 			 * we load from the unmodified address, and write the
 			 * modified address back
 			 */
-			load_address = Rn;
+			load_address = rn;
 		}
 
-		if ((!dry_run_pc) || (instruction.info.load_store.Rd == 15)) {
+		if ((!dry_run_pc) || (instruction.info.load_store.rd == 15)) {
 			retval = target_read_u32(target, load_address, &load_value);
 			if (retval != ERROR_OK)
 				return retval;
 		}
 
 		if (dry_run_pc) {
-			if (instruction.info.load_store.Rd == 15)
+			if (instruction.info.load_store.rd == 15)
 				*dry_run_pc = load_value & ~1;
 			else
 				*dry_run_pc = current_pc + instruction_size;
@@ -494,10 +494,10 @@ static int arm_simulate_step_core(struct target *target,
 			if ((instruction.info.load_store.index_mode == 1) ||
 				(instruction.info.load_store.index_mode == 2))
 				sim->set_reg_mode(sim,
-					instruction.info.load_store.Rn,
+					instruction.info.load_store.rn,
 					modified_address);
 
-			if (instruction.info.load_store.Rd == 15) {
+			if (instruction.info.load_store.rd == 15) {
 				sim->set_reg_mode(sim, 15, load_value & ~1);
 				if (load_value & 1)
 					sim->set_state(sim, ARM_STATE_THUMB);
@@ -505,13 +505,13 @@ static int arm_simulate_step_core(struct target *target,
 					sim->set_state(sim, ARM_STATE_ARM);
 				return ERROR_OK;
 			}
-			sim->set_reg_mode(sim, instruction.info.load_store.Rd, load_value);
+			sim->set_reg_mode(sim, instruction.info.load_store.rd, load_value);
 		}
 	}
 	/* load multiple instruction */
 	else if (instruction.type == ARM_LDM) {
 		int i;
-		uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store_multiple.Rn);
+		uint32_t rn = sim->get_reg_mode(sim, instruction.info.load_store_multiple.rn);
 		uint32_t load_values[16];
 		int bits_set = 0;
 
@@ -522,24 +522,24 @@ static int arm_simulate_step_core(struct target *target,
 
 		switch (instruction.info.load_store_multiple.addressing_mode) {
 			case 0:	/* Increment after */
-				/* Rn = Rn; */
+				/* rn = rn; */
 				break;
 			case 1:	/* Increment before */
-				Rn = Rn + 4;
+				rn = rn + 4;
 				break;
 			case 2:	/* Decrement after */
-				Rn = Rn - (bits_set * 4) + 4;
+				rn = rn - (bits_set * 4) + 4;
 				break;
 			case 3:	/* Decrement before */
-				Rn = Rn - (bits_set * 4);
+				rn = rn - (bits_set * 4);
 				break;
 		}
 
 		for (i = 0; i < 16; i++) {
 			if (instruction.info.load_store_multiple.register_list & (1 << i)) {
 				if ((!dry_run_pc) || (i == 15))
-					target_read_u32(target, Rn, &load_values[i]);
-				Rn += 4;
+					target_read_u32(target, rn, &load_values[i]);
+				rn += 4;
 			}
 		}
 
@@ -551,7 +551,7 @@ static int arm_simulate_step_core(struct target *target,
 		} else {
 			int update_cpsr = 0;
 
-			if (instruction.info.load_store_multiple.S) {
+			if (instruction.info.load_store_multiple.s) {
 				if (instruction.info.load_store_multiple.register_list & 0x8000)
 					update_cpsr = 1;
 			}
@@ -576,8 +576,8 @@ static int arm_simulate_step_core(struct target *target,
 			}
 
 			/* base register writeback */
-			if (instruction.info.load_store_multiple.W)
-				sim->set_reg_mode(sim, instruction.info.load_store_multiple.Rn, Rn);
+			if (instruction.info.load_store_multiple.w)
+				sim->set_reg_mode(sim, instruction.info.load_store_multiple.rn, rn);
 
 
 			if (instruction.info.load_store_multiple.register_list & 0x8000)
@@ -591,8 +591,8 @@ static int arm_simulate_step_core(struct target *target,
 		if (dry_run_pc) {
 			/* STM wont affect PC (advance by instruction size */
 		} else {
-			uint32_t Rn = sim->get_reg_mode(sim,
-					instruction.info.load_store_multiple.Rn);
+			uint32_t rn = sim->get_reg_mode(sim,
+					instruction.info.load_store_multiple.rn);
 			int bits_set = 0;
 
 			for (i = 0; i < 16; i++) {
@@ -602,30 +602,30 @@ static int arm_simulate_step_core(struct target *target,
 
 			switch (instruction.info.load_store_multiple.addressing_mode) {
 				case 0:	/* Increment after */
-					/* Rn = Rn; */
+					/* rn = rn; */
 					break;
 				case 1:	/* Increment before */
-					Rn = Rn + 4;
+					rn = rn + 4;
 					break;
 				case 2:	/* Decrement after */
-					Rn = Rn - (bits_set * 4) + 4;
+					rn = rn - (bits_set * 4) + 4;
 					break;
 				case 3:	/* Decrement before */
-					Rn = Rn - (bits_set * 4);
+					rn = rn - (bits_set * 4);
 					break;
 			}
 
 			for (i = 0; i < 16; i++) {
 				if (instruction.info.load_store_multiple.register_list & (1 << i)) {
-					target_write_u32(target, Rn, sim->get_reg_mode(sim, i));
-					Rn += 4;
+					target_write_u32(target, rn, sim->get_reg_mode(sim, i));
+					rn += 4;
 				}
 			}
 
 			/* base register writeback */
-			if (instruction.info.load_store_multiple.W)
+			if (instruction.info.load_store_multiple.w)
 				sim->set_reg_mode(sim,
-					instruction.info.load_store_multiple.Rn, Rn);
+					instruction.info.load_store_multiple.rn, rn);
 
 		}
 	} else if (!dry_run_pc) {
diff --git a/src/target/armv8_opcodes.h b/src/target/armv8_opcodes.h
index 239c4c5..8c213ef 100644
--- a/src/target/armv8_opcodes.h
+++ b/src/target/armv8_opcodes.h
@@ -26,13 +26,13 @@
 #define SYSTEM_CUREL_NONCH		0xF
 #define SYSTEM_AARCH64			0x1
 
-#define SYSTEM_AAR64_MODE_EL0t	0x0
-#define SYSTEM_AAR64_MODE_EL1t	0x4
-#define SYSTEM_AAR64_MODE_EL1h	0x5
-#define SYSTEM_AAR64_MODE_EL2t	0x8
-#define SYSTEM_AAR64_MODE_EL2h	0x9
-#define SYSTEM_AAR64_MODE_EL3t	0xC
-#define SYSTEM_AAR64_MODE_EL3h	0xd
+#define SYSTEM_AAR64_MODE_EL0T	0x0
+#define SYSTEM_AAR64_MODE_EL1T	0x4
+#define SYSTEM_AAR64_MODE_EL1H	0x5
+#define SYSTEM_AAR64_MODE_EL2T	0x8
+#define SYSTEM_AAR64_MODE_EL2H	0x9
+#define SYSTEM_AAR64_MODE_EL3T	0xC
+#define SYSTEM_AAR64_MODE_EL3H	0xd
 
 #define SYSTEM_DAIF			0b1101101000010001
 #define SYSTEM_DAIF_MASK		0x3C0
@@ -109,26 +109,26 @@
 #define SYSTEM_ESR_EL2			0b1110001010010000
 #define SYSTEM_ESR_EL3			0b1111001010010000
 
-#define ARMV8_MRS_DSPSR(Rt)	(0xd53b4500 | (Rt))
-#define ARMV8_MSR_DSPSR(Rt)	(0xd51b4500 | (Rt))
-#define ARMV8_MRS_DLR(Rt)	(0xd53b4520 | (Rt))
-#define ARMV8_MSR_DLR(Rt)	(0xd51b4520 | (Rt))
+#define ARMV8_MRS_DSPSR(rt)	(0xd53b4500 | (rt))
+#define ARMV8_MSR_DSPSR(rt)	(0xd51b4500 | (rt))
+#define ARMV8_MRS_DLR(rt)	(0xd53b4520 | (rt))
+#define ARMV8_MSR_DLR(rt)	(0xd51b4520 | (rt))
 
 /* T32 instruction to access coprocessor registers */
-#define ARMV8_MCR_T1(cp, CRn, opc1, CRm, opc2, Rt) ARMV4_5_MCR(cp, opc1, Rt, CRn, CRm, opc2)
-#define ARMV8_MRC_T1(cp, CRn, opc1, CRm, opc2, Rt) ARMV4_5_MRC(cp, opc1, Rt, CRn, CRm, opc2)
+#define ARMV8_MCR_T1(cp, crn, opc1, crm, opc2, rt) ARMV4_5_MCR(cp, opc1, rt, crn, crm, opc2)
+#define ARMV8_MRC_T1(cp, crn, opc1, crm, opc2, rt) ARMV4_5_MRC(cp, opc1, rt, crn, crm, opc2)
 
 /* T32 instructions to access DSPSR and DLR */
-#define ARMV8_MRC_DSPSR(Rt) ARMV8_MRC_T1(15, 4, 3, 5, 0, Rt)
-#define ARMV8_MCR_DSPSR(Rt) ARMV8_MCR_T1(15, 4, 3, 5, 0, Rt)
-#define ARMV8_MRC_DLR(Rt)	ARMV8_MRC_T1(15, 4, 3, 5, 1, Rt)
-#define ARMV8_MCR_DLR(Rt)	ARMV8_MCR_T1(15, 4, 3, 5, 1, Rt)
-
-#define ARMV8_DCPS1(IM)		(0xd4a00001 | (((IM) & 0xFFFF) << 5))
-#define ARMV8_DCPS2(IM)		(0xd4a00002 | (((IM) & 0xFFFF) << 5))
-#define ARMV8_DCPS3(IM)		(0xd4a00003 | (((IM) & 0xFFFF) << 5))
-#define ARMV8_DCPS(EL, IM)	(0xd4a00000 | (((IM) & 0xFFFF) << 5) | EL)
-#define ARMV8_DCPS_T1(EL)	(0xf78f8000 | EL)
+#define ARMV8_MRC_DSPSR(rt) ARMV8_MRC_T1(15, 4, 3, 5, 0, rt)
+#define ARMV8_MCR_DSPSR(rt) ARMV8_MCR_T1(15, 4, 3, 5, 0, rt)
+#define ARMV8_MRC_DLR(rt)	ARMV8_MRC_T1(15, 4, 3, 5, 1, rt)
+#define ARMV8_MCR_DLR(rt)	ARMV8_MCR_T1(15, 4, 3, 5, 1, rt)
+
+#define ARMV8_DCPS1(im)		(0xd4a00001 | (((im) & 0xFFFF) << 5))
+#define ARMV8_DCPS2(im)		(0xd4a00002 | (((im) & 0xFFFF) << 5))
+#define ARMV8_DCPS3(im)		(0xd4a00003 | (((im) & 0xFFFF) << 5))
+#define ARMV8_DCPS(el, im)	(0xd4a00000 | (((im) & 0xFFFF) << 5) | el)
+#define ARMV8_DCPS_T1(el)	(0xf78f8000 | el)
 #define ARMV8_DRPS		0xd6bf03e0
 #define ARMV8_ERET_T1		0xf3de8f00
 
@@ -137,54 +137,54 @@
 #define ARMV8_ISB				0xd5033fdf
 #define ARMV8_ISB_SY_T1				0xf3bf8f6f
 
-#define ARMV8_MRS(System, Rt)	(0xd5300000 | ((System) << 5) | (Rt))
+#define ARMV8_MRS(system, rt)	(0xd5300000 | ((system) << 5) | (rt))
 /* ARM V8 Move to system register. */
-#define ARMV8_MSR_GP(System, Rt) \
-	(0xd5100000 | ((System) << 5) | (Rt))
+#define ARMV8_MSR_GP(system, rt) \
+	(0xd5100000 | ((system) << 5) | (rt))
 /* ARM V8 Move immediate to process state field. */
-#define ARMV8_MSR_IM(Op1, CRm, Op2) \
-	(0xd500401f | ((Op1) << 16)  | ((CRm) << 8) | ((Op2) << 5))
+#define ARMV8_MSR_IM(op1, crm, op2) \
+	(0xd500401f | ((op1) << 16)  | ((crm) << 8) | ((op2) << 5))
 
-#define ARMV8_MRS_T1(R, M1, Rd, M) (0xF3E08020 | (R << 20) | (M1 << 16) | (Rd << 8) | (M << 4))
-#define ARMV8_MRS_xPSR_T1(R, Rd) (0xF3EF8000 | (R << 20) | (Rd << 8))
-#define ARMV8_MSR_GP_T1(R, M1, Rd, M) (0xF3808020 | (R << 20) | (M1 << 8) | (Rd << 16) | (M << 4))
-#define ARMV8_MSR_GP_xPSR_T1(R, Rn, mask) (0xF3808000 | (R << 20) | (Rn << 16) | (mask << 8))
+#define ARMV8_MRS_T1(r, m1, rd, m) (0xF3E08020 | (r << 20) | (m1 << 16) | (rd << 8) | (m << 4))
+#define ARMV8_MRS_xPSR_T1(r, rd) (0xF3EF8000 | (r << 20) | (rd << 8))
+#define ARMV8_MSR_GP_T1(r, m1, rd, m) (0xF3808020 | (r << 20) | (m1 << 8) | (rd << 16) | (m << 4))
+#define ARMV8_MSR_GP_xPSR_T1(r, rn, mask) (0xF3808000 | (r << 20) | (rn << 16) | (mask << 8))
 
-#define ARMV8_BKPT(Im) (0xD4200000 | ((Im & 0xffff) << 5))
-#define ARMV8_HLT(Im) (0x0D4400000 | ((Im & 0xffff) << 5))
-#define ARMV8_HLT_A1(Im) (0xE1000070 | ((Im & 0xFFF0) << 4) | (Im & 0xF))
-#define ARMV8_HLT_T1(Im) (0xba80 | (Im & 0x3f))
+#define ARMV8_BKPT(im) (0xD4200000 | ((im & 0xffff) << 5))
+#define ARMV8_HLT(im) (0x0D4400000 | ((im & 0xffff) << 5))
+#define ARMV8_HLT_A1(im) (0xE1000070 | ((im & 0xFFF0) << 4) | (im & 0xF))
+#define ARMV8_HLT_T1(im) (0xba80 | (im & 0x3f))
 
-#define ARMV8_MOVFSP_64(Rt) ((1 << 31) | 0x11000000 | (0x1f << 5) | (Rt))
-#define ARMV8_MOVTSP_64(Rt) ((1 << 31) | 0x11000000 | (Rt << 5) | (0x1F))
-#define ARMV8_MOVFSP_32(Rt) (0x11000000 | (0x1f << 5) | (Rt))
-#define ARMV8_MOVTSP_32(Rt) (0x11000000 | (Rt << 5) | (0x1F))
+#define ARMV8_MOVFSP_64(rt) ((1 << 31) | 0x11000000 | (0x1f << 5) | (rt))
+#define ARMV8_MOVTSP_64(rt) ((1 << 31) | 0x11000000 | (rt << 5) | (0x1F))
+#define ARMV8_MOVFSP_32(rt) (0x11000000 | (0x1f << 5) | (rt))
+#define ARMV8_MOVTSP_32(rt) (0x11000000 | (rt << 5) | (0x1F))
 
-#define ARMV8_LDRB_IP(Rd, Rn) (0x38401400 | (Rn << 5) | Rd)
-#define ARMV8_LDRH_IP(Rd, Rn) (0x78402400 | (Rn << 5) | Rd)
-#define ARMV8_LDRW_IP(Rd, Rn) (0xb8404400 | (Rn << 5) | Rd)
+#define ARMV8_LDRB_IP(rd, rn) (0x38401400 | (rn << 5) | rd)
+#define ARMV8_LDRH_IP(rd, rn) (0x78402400 | (rn << 5) | rd)
+#define ARMV8_LDRW_IP(rd, rn) (0xb8404400 | (rn << 5) | rd)
 
-#define ARMV8_LDRB_IP_T3(Rd, Rn) (0xf8100b01 | (Rn << 16) | (Rd << 12))
-#define ARMV8_LDRH_IP_T3(Rd, Rn) (0xf8300b02 | (Rn << 16) | (Rd << 12))
-#define ARMV8_LDRW_IP_T3(Rd, Rn) (0xf8500b04 | (Rn << 16) | (Rd << 12))
+#define ARMV8_LDRB_IP_T3(rd, rn) (0xf8100b01 | (rn << 16) | (rd << 12))
+#define ARMV8_LDRH_IP_T3(rd, rn) (0xf8300b02 | (rn << 16) | (rd << 12))
+#define ARMV8_LDRW_IP_T3(rd, rn) (0xf8500b04 | (rn << 16) | (rd << 12))
 
-#define ARMV8_STRB_IP(Rd, Rn) (0x38001400 | (Rn << 5) | Rd)
-#define ARMV8_STRH_IP(Rd, Rn) (0x78002400 | (Rn << 5) | Rd)
-#define ARMV8_STRW_IP(Rd, Rn) (0xb8004400 | (Rn << 5) | Rd)
+#define ARMV8_STRB_IP(rd, rn) (0x38001400 | (rn << 5) | rd)
+#define ARMV8_STRH_IP(rd, rn) (0x78002400 | (rn << 5) | rd)
+#define ARMV8_STRW_IP(rd, rn) (0xb8004400 | (rn << 5) | rd)
 
-#define ARMV8_STRB_IP_T3(Rd, Rn) (0xf8000b01 | (Rn << 16) | (Rd << 12))
-#define ARMV8_STRH_IP_T3(Rd, Rn) (0xf8200b02 | (Rn << 16) | (Rd << 12))
-#define ARMV8_STRW_IP_T3(Rd, Rn) (0xf8400b04 | (Rn << 16) | (Rd << 12))
+#define ARMV8_STRB_IP_T3(rd, rn) (0xf8000b01 | (rn << 16) | (rd << 12))
+#define ARMV8_STRH_IP_T3(rd, rn) (0xf8200b02 | (rn << 16) | (rd << 12))
+#define ARMV8_STRW_IP_T3(rd, rn) (0xf8400b04 | (rn << 16) | (rd << 12))
 
-#define ARMV8_MOV_GPR_VFP(Rd, Rn, Index) (0x4e083c00 | (Index << 20) | (Rn << 5) | Rd)
-#define ARMV8_MOV_VFP_GPR(Rd, Rn, Index) (0x4e081c00 | (Index << 20) | (Rn << 5) | Rd)
+#define ARMV8_MOV_GPR_VFP(rd, rn, index) (0x4e083c00 | (index << 20) | (rn << 5) | rd)
+#define ARMV8_MOV_VFP_GPR(rd, rn, index) (0x4e081c00 | (index << 20) | (rn << 5) | rd)
 
-#define ARMV8_MRS_FPCR(Rt)	(0xd53b4400 | (Rt))
-#define ARMV8_MRS_FPSR(Rt)	(0xd53b4420 | (Rt))
-#define ARMV8_MSR_FPCR(Rt)	(0xd51b4400 | (Rt))
-#define ARMV8_MSR_FPSR(Rt)	(0xd51b4420 | (Rt))
+#define ARMV8_MRS_FPCR(rt)	(0xd53b4400 | (rt))
+#define ARMV8_MRS_FPSR(rt)	(0xd53b4420 | (rt))
+#define ARMV8_MSR_FPCR(rt)	(0xd51b4400 | (rt))
+#define ARMV8_MSR_FPSR(rt)	(0xd51b4420 | (rt))
 
-#define ARMV8_SYS(System, Rt) (0xD5080000 | ((System) << 5) | Rt)
+#define ARMV8_SYS(system, rt) (0xD5080000 | ((system) << 5) | rt)
 
 enum armv8_opcode {
 	READ_REG_CTR,