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| author | Tim Newsome <tim@sifive.com> | 2021-01-14 13:52:50 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2021-01-14 13:53:43 -0800 |
| commit | fcdecd88aecb98507e5e97926cdbbb84c36ce3b0 (patch) | |
| tree | 86c1c6c2116ab9c9e06f146b65665fa341e934bd /src/target | |
| parent | d7db23c6fcda69e22b23e64b65b10c637f8ddb9e (diff) | |
| download | riscv-openocd-fcdecd88aecb98507e5e97926cdbbb84c36ce3b0.zip riscv-openocd-fcdecd88aecb98507e5e97926cdbbb84c36ce3b0.tar.gz riscv-openocd-fcdecd88aecb98507e5e97926cdbbb84c36ce3b0.tar.bz2 | |
Don't write to zero.
It doesn't have any effect on real hardware, and by caching the value we
pretended it did.
Fixes #564
Change-Id: I9f4e2cc8abddee61435bbd8d992cbff971a0c28d
Signed-off-by: Tim Newsome <tim@sifive.com>
Diffstat (limited to 'src/target')
| -rw-r--r-- | src/target/riscv/riscv.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 9978931..9a56561 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -4165,6 +4165,11 @@ static int register_set(struct reg *reg, uint8_t *buf) riscv_current_hartid(target), str, reg->name, reg->valid); free(str); + /* Exit early for writing x0, which on the hardware would be ignored, and we + * don't want to update our cache. */ + if (reg->number == GDB_REGNO_ZERO) + return ERROR_OK; + memcpy(reg->value, buf, DIV_ROUND_UP(reg->size, 8)); reg->valid = gdb_regno_cacheable(reg->number, true); |