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| author | Antonio Borneo <borneo.antonio@gmail.com> | 2022-06-13 16:41:11 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2022-06-24 21:49:25 +0000 |
| commit | e4f5ce5d3e342826794739a273b1f72a48d63540 (patch) | |
| tree | c6ec89f1b925dd1e7aac4fc9eb1f64dc798f55ff /src/target | |
| parent | f23ac683430ffb08b511dd02afc93bc1f454a017 (diff) | |
| download | riscv-openocd-e4f5ce5d3e342826794739a273b1f72a48d63540.zip riscv-openocd-e4f5ce5d3e342826794739a273b1f72a48d63540.tar.gz riscv-openocd-e4f5ce5d3e342826794739a273b1f72a48d63540.tar.bz2 | |
aarch64: fix handling of 'reset halt'
Commit 6c0151623cb0 ("aarch64: add support for "reset halt"")
introduces the register setting to halt at reset vector, but:
- does not consider the case 'srst_pulls_trst' that makes useless
setting the registers as they will be erased by the pulled trst;
- does not clean sticky errors in case of 'srst_gates_jtag'.
Avoid any register initialization on 'srst_pulls_trst' and move
the cleaning of sticky errors in the common block.
Change-Id: I6f839f06f7b091e234ede31ec18096e51f017bcd
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 6c0151623cb0 ("aarch64: add support for "reset halt"")
Reviewed-on: https://review.openocd.org/c/openocd/+/7034
Tested-by: jenkins
Reviewed-by: Christian Hoff <christian.hoff@advantest.com>
Diffstat (limited to 'src/target')
| -rw-r--r-- | src/target/aarch64.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 8a8f21d..e4d420f 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -1942,7 +1942,7 @@ static int aarch64_assert_reset(struct target *target) else if (reset_config & RESET_HAS_SRST) { bool srst_asserted = false; - if (target->reset_halt) { + if (target->reset_halt && !(reset_config & RESET_SRST_PULLS_TRST)) { if (target_was_examined(target)) { if (reset_config & RESET_SRST_NO_GATING) { @@ -1952,12 +1952,12 @@ static int aarch64_assert_reset(struct target *target) */ adapter_assert_reset(); srst_asserted = true; - - /* make sure to clear all sticky errors */ - mem_ap_write_atomic_u32(armv8->debug_ap, - armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE); } + /* make sure to clear all sticky errors */ + mem_ap_write_atomic_u32(armv8->debug_ap, + armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE); + /* set up Reset Catch debug event to halt the CPU after reset */ retval = aarch64_enable_reset_catch(target, true); if (retval != ERROR_OK) |