Add `riscv info` command. (#558)

Add `riscv info` command. Final output is "TCL format" and looks like this:
```
hart.xlen              64
hart.trigger_count      4
dm.abits                6
dm.progbufsize          2
dm.sbversion            0
dm.sbasize              0
dm.sbaccess128          0
dm.sbaccess64           0
dm.sbaccess32           0
dm.sbaccess16           0
dm.sbaccess8            0
```

* Add `riscv info` command.

This command displays some basic information that OpenOCD has detected
about the target. The output is displayed in YAML so it can easily be
parsed. Example of current output:
```
Hart:
  XLEN: 32
  trigger count: 4
Debug Module:
  abits: 6
  progbufsize: 2
  sbversion: 0
  sbasize: 0
  sbaccess128: 0
  sbaccess64: 0
  sbaccess32: 0
  sbaccess16: 0
  sbaccess8: 0
```

Change-Id: If920c083ff6ec9f482c50f913cd8ceaa62461217
Signed-off-by: Tim Newsome <tim@sifive.com>

* Disable workflow inherited from upstream.

Change-Id: Ifc5ed1b4f5ec2278b8bcf3279c9fd462e469fefa
Signed-off-by: Tim Newsome <tim@sifive.com>

* Switch from YAML to TCL "set array" input format.

Change-Id: I3833210e5bf6d7cffc9934c04ec5201ae7732ad8
Signed-off-by: Tim Newsome <tim@sifive.com>

* Remove indent in `riscv info` output.

That was getting a little too cute, and probably more confusing than
helpful.

Change-Id: Ie51416f53ab4b69294962f0565767d370db82867
Signed-off-by: Tim Newsome <tim@sifive.com>

3 files changed, 57 insertions, 0 deletions

diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index c727101..0565e49 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -1876,6 +1876,22 @@ static unsigned riscv013_data_bits(struct target *target)
 	return 32;
 }
 
+COMMAND_HELPER(riscv013_print_info, struct target *target)
+{
+	RISCV013_INFO(info);
+	riscv_print_info_line(CMD, "dm", "abits", info->abits);
+	riscv_print_info_line(CMD, "dm", "progbufsize", info->progbufsize);
+	riscv_print_info_line(CMD, "dm", "sbversion", get_field(info->sbcs, DM_SBCS_SBVERSION));
+	riscv_print_info_line(CMD, "dm", "sbasize", get_field(info->sbcs, DM_SBCS_SBASIZE));
+	riscv_print_info_line(CMD, "dm", "sbaccess128", get_field(info->sbcs, DM_SBCS_SBACCESS128));
+	riscv_print_info_line(CMD, "dm", "sbaccess64", get_field(info->sbcs, DM_SBCS_SBACCESS64));
+	riscv_print_info_line(CMD, "dm", "sbaccess32", get_field(info->sbcs, DM_SBCS_SBACCESS32));
+	riscv_print_info_line(CMD, "dm", "sbaccess16", get_field(info->sbcs, DM_SBCS_SBACCESS16));
+	riscv_print_info_line(CMD, "dm", "sbaccess8", get_field(info->sbcs, DM_SBCS_SBACCESS8));
+
+	return 0;
+}
+
 static int prep_for_vector_access(struct target *target, uint64_t *vtype,
 		uint64_t *vl, unsigned *debug_vl)
 {
@@ -2273,6 +2289,7 @@ static int init_target(struct command_context *cmd_ctx,
 	generic_info->test_compliance = &riscv013_test_compliance;
 	generic_info->hart_count = &riscv013_hart_count;
 	generic_info->data_bits = &riscv013_data_bits;
+	generic_info->print_info = &riscv013_print_info;
 	generic_info->version_specific = calloc(1, sizeof(riscv013_info_t));
 	if (!generic_info->version_specific)
 		return ERROR_FAIL;
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index fd81b57..2c34795 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -3134,6 +3134,33 @@ error:
 	return result;
 }
 
+COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key,
+			   unsigned value)
+{
+	char full_key[80];
+	snprintf(full_key, sizeof(full_key), "%s.%s", section, key);
+	command_print(CMD, "%-21s %3d", full_key, value);
+	return 0;
+}
+
+COMMAND_HANDLER(handle_info)
+{
+	struct target *target = get_current_target(CMD_CTX);
+	RISCV_INFO(r);
+
+	/* This output format can be fed directly into TCL's "array set". */
+
+	riscv_print_info_line(CMD, "hart", "xlen", riscv_xlen(target));
+	riscv_enumerate_triggers(target);
+	riscv_print_info_line(CMD, "hart", "trigger_count",
+						  r->trigger_count[target->coreid]);
+
+	if (r->print_info)
+		return CALL_COMMAND_HANDLER(r->print_info, target);
+
+	return 0;
+}
+
 static const struct command_registration riscv_exec_command_handlers[] = {
 	{
 		.name = "dump_sample_buf",
@@ -3143,6 +3170,13 @@ static const struct command_registration riscv_exec_command_handlers[] = {
 		.help = "Print the contents of the sample buffer, and clear the buffer."
 	},
 	{
+		.name = "info",
+		.handler = handle_info,
+		.mode = COMMAND_ANY,
+		.usage = "riscv info",
+		.help = "Displays some information OpenOCD detected about the target."
+	},
+	{
 		.name = "memory_sample",
 		.handler = handle_memory_sample_command,
 		.mode = COMMAND_ANY,
diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h
index 80cef7b..8e098c0 100644
--- a/src/target/riscv/riscv.h
+++ b/src/target/riscv/riscv.h
@@ -10,6 +10,7 @@ struct riscv_program;
 #include "gdb_regs.h"
 #include "jtag/jtag.h"
 #include "target/register.h"
+#include "command.h"
 
 /* The register cache is statically allocated. */
 #define RISCV_MAX_HARTS 1024
@@ -198,6 +199,8 @@ typedef struct {
 	int (*hart_count)(struct target *target);
 	unsigned (*data_bits)(struct target *target);
 
+	COMMAND_HELPER((*print_info), struct target *target);
+
 	/* Storage for vector register types. */
 	struct reg_data_type_vector vector_uint8;
 	struct reg_data_type_vector vector_uint16;
@@ -238,6 +241,9 @@ typedef struct {
 	riscv_sample_buf_t sample_buf;
 } riscv_info_t;
 
+COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key,
+			   unsigned value);
+
 typedef struct {
 	uint8_t tunneled_dr_width;
 	struct scan_field tunneled_dr[4];