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| author | Erhan Kurubas <erhan.kurubas@espressif.com> | 2022-06-12 01:04:08 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2022-06-24 21:47:07 +0000 |
| commit | af9daf4433e006197942121a069a5e9d7ec28671 (patch) | |
| tree | 9cfe15fb9bccc162d0b35e47c61b59676c2c1be2 /src/target | |
| parent | 2053120ba10d68339c61cd2b247bde01bda41ab7 (diff) | |
| download | riscv-openocd-af9daf4433e006197942121a069a5e9d7ec28671.zip riscv-openocd-af9daf4433e006197942121a069a5e9d7ec28671.tar.gz riscv-openocd-af9daf4433e006197942121a069a5e9d7ec28671.tar.bz2 | |
esp32s2: convert counted timeout to timeval_ms
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Id685408281478cec0e7e886dbedb3b8972c7b652
Reviewed-on: https://review.openocd.org/c/openocd/+/7020
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Ian Thompson <ianst@cadence.com>
Diffstat (limited to 'src/target')
| -rw-r--r-- | src/target/espressif/esp32s2.c | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/src/target/espressif/esp32s2.c b/src/target/espressif/esp32s2.c index 3698032..1bf56b9 100644 --- a/src/target/espressif/esp32s2.c +++ b/src/target/espressif/esp32s2.c @@ -21,6 +21,7 @@ #include "config.h" #endif +#include <helper/time_support.h> #include "assert.h" #include <target/target.h> #include <target/target_type.h> @@ -482,15 +483,16 @@ static int esp32s2_soc_reset(struct target *target) } /* Wait for SoC to reset */ alive_sleep(100); - int timeout = 100; - while (target->state != TARGET_RESET && target->state != TARGET_RUNNING && --timeout > 0) { + int64_t timeout = timeval_ms() + 100; + while (target->state != TARGET_RESET && target->state != TARGET_RUNNING) { alive_sleep(10); xtensa_poll(target); + if (timeval_ms() >= timeout) { + LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d", target->state); + return ERROR_TARGET_TIMEOUT; + } } - if (timeout == 0) { - LOG_ERROR("Timed out waiting for CPU to be reset, target->state=%d", target->state); - return ERROR_TARGET_TIMEOUT; - } + xtensa_halt(target); res = target_wait_state(target, TARGET_HALTED, 1000); if (res != ERROR_OK) { |