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author | Antonio Borneo <borneo.antonio@gmail.com> | 2019-05-06 00:03:03 +0200 |
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committer | Antonio Borneo <borneo.antonio@gmail.com> | 2020-05-09 14:39:05 +0100 |
commit | 9b29cb58acbd14ed831d68fce4d6e6a1728f8caf (patch) | |
tree | 76ba767e4074f82fb6ba90510086c2be9d5e00a4 /src/target | |
parent | 5df5e89cf3caf02dc6f49a5d3c8aa8b1349a1dbf (diff) | |
download | riscv-openocd-9b29cb58acbd14ed831d68fce4d6e6a1728f8caf.zip riscv-openocd-9b29cb58acbd14ed831d68fce4d6e6a1728f8caf.tar.gz riscv-openocd-9b29cb58acbd14ed831d68fce4d6e6a1728f8caf.tar.bz2 |
coding style: remove useless break after a goto or return
In a switch/case statement, a break placed after a goto or return
is never executed.
The script checkpatch available in Linux kernel v5.1 issues a
warning for such unused break statements.
In the process of reviewing the new checkpatch for its inclusion
in OpenOCD, let's get rid of these warnings.
The script checkpatch is unable to fixup automatically this case.
Thanks to having "break" command using a single code line, this
patch has been generated using the script below:
find src/ -type f -exec ./tools/scripts/checkpatch.pl -q \
--types UNNECESSARY_BREAK -f {} \; \
| sed -n '/^#/{s/^.*FILE: //;s/:$//;s/:/ /;p}' \
| awk 'function P() {print "sed -i '\''"b"'\'' "a};
{
if ($1!=a) {
if (a) {P()};
a=$1;
b=$2"{d}";
} else {
b=b";"$2"{d}"
}
};
END {P()}'
Change-Id: I56ca098faa5fe8d1e3f712dc0a029a3f10559d99
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5617
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
Diffstat (limited to 'src/target')
-rw-r--r-- | src/target/arm_disassembler.c | 1 | ||||
-rw-r--r-- | src/target/arm_dpm.c | 2 | ||||
-rw-r--r-- | src/target/armv4_5.c | 3 | ||||
-rw-r--r-- | src/target/avr32_ap7k.c | 2 | ||||
-rw-r--r-- | src/target/riscv/riscv-013.c | 2 |
5 files changed, 0 insertions, 10 deletions
diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c index 8eb8194..04c3922 100644 --- a/src/target/arm_disassembler.c +++ b/src/target/arm_disassembler.c @@ -2309,7 +2309,6 @@ static int evaluate_data_proc_thumb(uint16_t opcode, address, opcode); } return ERROR_OK; - break; } } else { switch (op) { diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c index f5dd22d..a01339c 100644 --- a/src/target/arm_dpm.c +++ b/src/target/arm_dpm.c @@ -212,7 +212,6 @@ int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum) break; case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31: return dpm_read_reg_u64(dpm, r, regnum); - break; case ARM_VFP_V3_FPSCR: /* "VMRS r0, FPSCR"; then return via DCC */ retval = dpm->instr_read_data_r0(dpm, @@ -294,7 +293,6 @@ static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum) break; case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31: return dpm_write_reg_u64(dpm, r, regnum); - break; case ARM_VFP_V3_FPSCR: /* move to r0 from DCC, then "VMSR FPSCR, r0" */ retval = dpm->instr_write_data_r0(dpm, diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index a0983cd..b4581d5 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -1223,7 +1223,6 @@ int arm_get_gdb_reg_list(struct target *target, (*reg_list)[25] = arm->cpsr; return ERROR_OK; - break; case REG_CLASS_ALL: switch (arm->core_type) { @@ -1273,12 +1272,10 @@ int arm_get_gdb_reg_list(struct target *target, } return ERROR_OK; - break; default: LOG_ERROR("not a valid register class type in query."); return ERROR_FAIL; - break; } } diff --git a/src/target/avr32_ap7k.c b/src/target/avr32_ap7k.c index cf08e3a..6221059 100644 --- a/src/target/avr32_ap7k.c +++ b/src/target/avr32_ap7k.c @@ -464,7 +464,6 @@ static int avr32_ap7k_read_memory(struct target *target, target_addr_t address, break; case 1: return avr32_jtag_read_memory8(&ap7k->jtag, address, count, buffer); - break; default: break; } @@ -505,7 +504,6 @@ static int avr32_ap7k_write_memory(struct target *target, target_addr_t address, break; case 1: return avr32_jtag_write_memory8(&ap7k->jtag, address, count, buffer); - break; default: break; } diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 8307b02..e302941 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -666,10 +666,8 @@ uint32_t abstract_register_size(unsigned width) return set_field(0, AC_ACCESS_REGISTER_SIZE, 2); case 64: return set_field(0, AC_ACCESS_REGISTER_SIZE, 3); - break; case 128: return set_field(0, AC_ACCESS_REGISTER_SIZE, 4); - break; default: LOG_ERROR("Unsupported register width: %d", width); return 0; |