Merge branch 'master' into from_upstream

Change-Id: I036350ee06aa396344fb8a80c7dba148ec24c9c8

52 files changed, 1088 insertions, 1232 deletions

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index ff68e3a..7acb472 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -29,6 +29,7 @@
 #include "armv8_opcodes.h"
 #include "armv8_cache.h"
 #include "arm_semihosting.h"
+#include "jtag/interface.h"
 #include "smp.h"
 #include <helper/time_support.h>
 
@@ -1662,7 +1663,7 @@ static int aarch64_assert_reset(struct target *target)
 		/* REVISIT handle "pulls" cases, if there's
 		 * hardware that needs them to work.
 		 */
-		jtag_add_reset(0, 1);
+		adapter_assert_reset();
 	} else {
 		LOG_ERROR("%s: how to reset?", target_name(target));
 		return ERROR_FAIL;
@@ -1686,7 +1687,7 @@ static int aarch64_deassert_reset(struct target *target)
 	LOG_DEBUG(" ");
 
 	/* be certain SRST is off */
-	jtag_add_reset(0, 0);
+	adapter_deassert_reset();
 
 	if (!target_was_examined(target))
 		return ERROR_OK;
@@ -2533,7 +2534,7 @@ COMMAND_HANDLER(aarch64_handle_cache_info_command)
 	struct target *target = get_current_target(CMD_CTX);
 	struct armv8_common *armv8 = target_to_armv8(target);
 
-	return armv8_handle_cache_info_command(CMD_CTX,
+	return armv8_handle_cache_info_command(CMD,
 			&armv8->armv8_mmu.armv8_cache);
 }
 
@@ -2572,7 +2573,7 @@ COMMAND_HANDLER(aarch64_mask_interrupts_command)
 	}
 
 	n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, aarch64->isrmasking_mode);
-	command_print(CMD_CTX, "aarch64 interrupt mask %s", n->name);
+	command_print(CMD, "aarch64 interrupt mask %s", n->name);
 
 	return ERROR_OK;
 }
diff --git a/src/target/adi_v5_swd.c b/src/target/adi_v5_swd.c
index d92e296..594b508 100644
--- a/src/target/adi_v5_swd.c
+++ b/src/target/adi_v5_swd.c
@@ -352,6 +352,7 @@ static const struct command_registration swd_handlers[] = {
 		.mode = COMMAND_ANY,
 		.help = "SWD command group",
 		.chain = swd_commands,
+		.usage = "",
 	},
 	COMMAND_REGISTRATION_DONE
 };
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index b592ffc..abe5f1c 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -233,11 +233,11 @@ static void arm720t_pre_restore_context(struct target *target)
 	arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
 }
 
-static int arm720t_verify_pointer(struct command_context *cmd_ctx,
+static int arm720t_verify_pointer(struct command_invocation *cmd,
 		struct arm720t_common *arm720t)
 {
 	if (arm720t->common_magic != ARM720T_COMMON_MAGIC) {
-		command_print(cmd_ctx, "target is not an ARM720");
+		command_print(cmd, "target is not an ARM720");
 		return ERROR_TARGET_INVALID;
 	}
 	return ERROR_OK;
@@ -442,12 +442,12 @@ COMMAND_HANDLER(arm720t_handle_cp15_command)
 	struct target *target = get_current_target(CMD_CTX);
 	struct arm720t_common *arm720t = target_to_arm720(target);
 
-	retval = arm720t_verify_pointer(CMD_CTX, arm720t);
+	retval = arm720t_verify_pointer(CMD, arm720t);
 	if (retval != ERROR_OK)
 		return retval;
 
 	if (target->state != TARGET_HALTED) {
-		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+		command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
 		return ERROR_OK;
 	}
 
@@ -460,7 +460,7 @@ COMMAND_HANDLER(arm720t_handle_cp15_command)
 			uint32_t value;
 			retval = arm720t_read_cp15(target, opcode, &value);
 			if (retval != ERROR_OK) {
-				command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
+				command_print(CMD, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 				return ERROR_OK;
 			}
 
@@ -468,17 +468,17 @@ COMMAND_HANDLER(arm720t_handle_cp15_command)
 			if (retval != ERROR_OK)
 				return retval;
 
-			command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
+			command_print(CMD, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 		} else if (CMD_ARGC == 2) {
 			uint32_t value;
 			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
 
 			retval = arm720t_write_cp15(target, opcode, value);
 			if (retval != ERROR_OK) {
-				command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
+				command_print(CMD, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 				return ERROR_OK;
 			}
-			command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
+			command_print(CMD, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 		}
 	}
 
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index c6a8a26..b2962d1 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2747,14 +2747,14 @@ COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
 	if (!is_arm7_9(arm7_9)) {
-		command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
+		command_print(CMD, "current target isn't an ARM7/ARM9 target");
 		return ERROR_TARGET_INVALID;
 	}
 
 	if (CMD_ARGC > 0)
 		COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->use_dbgrq);
 
-	command_print(CMD_CTX,
+	command_print(CMD,
 		"use of EmbeddedICE dbgrq instead of breakpoint for target halt %s",
 		(arm7_9->use_dbgrq) ? "enabled" : "disabled");
 
@@ -2767,14 +2767,14 @@ COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
 	if (!is_arm7_9(arm7_9)) {
-		command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
+		command_print(CMD, "current target isn't an ARM7/ARM9 target");
 		return ERROR_TARGET_INVALID;
 	}
 
 	if (CMD_ARGC > 0)
 		COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->fast_memory_access);
 
-	command_print(CMD_CTX,
+	command_print(CMD,
 		"fast memory access is %s",
 		(arm7_9->fast_memory_access) ? "enabled" : "disabled");
 
@@ -2787,14 +2787,14 @@ COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
 	if (!is_arm7_9(arm7_9)) {
-		command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
+		command_print(CMD, "current target isn't an ARM7/ARM9 target");
 		return ERROR_TARGET_INVALID;
 	}
 
 	if (CMD_ARGC > 0)
 		COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->dcc_downloads);
 
-	command_print(CMD_CTX,
+	command_print(CMD,
 		"dcc downloads are %s",
 		(arm7_9->dcc_downloads) ? "enabled" : "disabled");
 
@@ -2864,7 +2864,7 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
 
 static const struct command_registration arm7_9_any_command_handlers[] = {
 	{
-		"dbgrq",
+		.name = "dbgrq",
 		.handler = handle_arm7_9_dbgrq_command,
 		.mode = COMMAND_ANY,
 		.usage = "['enable'|'disable']",
@@ -2872,7 +2872,7 @@ static const struct command_registration arm7_9_any_command_handlers[] = {
 			"for target halt requests",
 	},
 	{
-		"fast_memory_access",
+		.name = "fast_memory_access",
 		.handler = handle_arm7_9_fast_memory_access_command,
 		.mode = COMMAND_ANY,
 		.usage = "['enable'|'disable']",
@@ -2880,7 +2880,7 @@ static const struct command_registration arm7_9_any_command_handlers[] = {
 			"but potentially safer accesses",
 	},
 	{
-		"dcc_downloads",
+		.name = "dcc_downloads",
 		.handler = handle_arm7_9_dcc_downloads_command,
 		.mode = COMMAND_ANY,
 		.usage = "['enable'|'disable']",
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index ed9d388..2ecf218 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -507,11 +507,11 @@ void arm920t_pre_restore_context(struct target *target)
 
 static const char arm920_not[] = "target is not an ARM920";
 
-static int arm920t_verify_pointer(struct command_context *cmd_ctx,
+static int arm920t_verify_pointer(struct command_invocation *cmd,
 	struct arm920t_common *arm920t)
 {
 	if (arm920t->common_magic != ARM920T_COMMON_MAGIC) {
-		command_print(cmd_ctx, arm920_not);
+		command_print(cmd, arm920_not);
 		return ERROR_TARGET_INVALID;
 	}
 
@@ -869,7 +869,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 	int segment, index_t;
 	struct reg *r;
 
-	retval = arm920t_verify_pointer(CMD_CTX, arm920t);
+	retval = arm920t_verify_pointer(CMD, arm920t);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -1103,7 +1103,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 	/* restore CP15 MMU and Cache settings */
 	arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_ctrl_saved);
 
-	command_print(CMD_CTX, "cache content successfully output to %s",
+	command_print(CMD, "cache content successfully output to %s",
 		CMD_ARGV[0]);
 
 	fclose(output);
@@ -1151,7 +1151,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 	int victim;
 	struct reg *r;
 
-	retval = arm920t_verify_pointer(CMD_CTX, arm920t);
+	retval = arm920t_verify_pointer(CMD, arm920t);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -1415,7 +1415,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 			(i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
 	}
 
-	command_print(CMD_CTX, "mmu content successfully output to %s",
+	command_print(CMD, "mmu content successfully output to %s",
 		CMD_ARGV[0]);
 
 	fclose(output);
@@ -1451,12 +1451,12 @@ COMMAND_HANDLER(arm920t_handle_cp15_command)
 	struct target *target = get_current_target(CMD_CTX);
 	struct arm920t_common *arm920t = target_to_arm920(target);
 
-	retval = arm920t_verify_pointer(CMD_CTX, arm920t);
+	retval = arm920t_verify_pointer(CMD, arm920t);
 	if (retval != ERROR_OK)
 		return retval;
 
 	if (target->state != TARGET_HALTED) {
-		command_print(CMD_CTX, "target must be stopped for "
+		command_print(CMD, "target must be stopped for "
 			"\"%s\" command", CMD_NAME);
 		return ERROR_OK;
 	}
@@ -1472,7 +1472,7 @@ COMMAND_HANDLER(arm920t_handle_cp15_command)
 			uint32_t value;
 			retval = arm920t_read_cp15_physical(target, address, &value);
 			if (retval != ERROR_OK) {
-				command_print(CMD_CTX,
+				command_print(CMD,
 					"couldn't access reg %i", address);
 				return ERROR_OK;
 			}
@@ -1480,7 +1480,7 @@ COMMAND_HANDLER(arm920t_handle_cp15_command)
 			if (retval != ERROR_OK)
 				return retval;
 
-			command_print(CMD_CTX, "%i: %8.8" PRIx32,
+			command_print(CMD, "%i: %8.8" PRIx32,
 				address, value);
 		} else if (CMD_ARGC == 2)   {
 			uint32_t value;
@@ -1488,12 +1488,12 @@ COMMAND_HANDLER(arm920t_handle_cp15_command)
 			retval = arm920t_write_cp15_physical(target,
 					address, value);
 			if (retval != ERROR_OK) {
-				command_print(CMD_CTX,
+				command_print(CMD,
 					"couldn't access reg %i", address);
 				/* REVISIT why lie? "return retval"? */
 				return ERROR_OK;
 			}
-			command_print(CMD_CTX, "%i: %8.8" PRIx32,
+			command_print(CMD, "%i: %8.8" PRIx32,
 				address, value);
 		}
 	}
@@ -1507,13 +1507,13 @@ COMMAND_HANDLER(arm920t_handle_cp15i_command)
 	struct target *target = get_current_target(CMD_CTX);
 	struct arm920t_common *arm920t = target_to_arm920(target);
 
-	retval = arm920t_verify_pointer(CMD_CTX, arm920t);
+	retval = arm920t_verify_pointer(CMD, arm920t);
 	if (retval != ERROR_OK)
 		return retval;
 
 
 	if (target->state != TARGET_HALTED) {
-		command_print(CMD_CTX, "target must be stopped for "
+		command_print(CMD, "target must be stopped for "
 			"\"%s\" command", CMD_NAME);
 		return ERROR_OK;
 	}
@@ -1530,14 +1530,14 @@ COMMAND_HANDLER(arm920t_handle_cp15i_command)
 			retval = arm920t_read_cp15_interpreted(target,
 					opcode, 0x0, &value);
 			if (retval != ERROR_OK) {
-				command_print(CMD_CTX,
+				command_print(CMD,
 					"couldn't execute %8.8" PRIx32,
 					opcode);
 				/* REVISIT why lie? "return retval"? */
 				return ERROR_OK;
 			}
 
-			command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32,
+			command_print(CMD, "%8.8" PRIx32 ": %8.8" PRIx32,
 				opcode, value);
 		} else if (CMD_ARGC == 2) {
 			uint32_t value;
@@ -1545,13 +1545,13 @@ COMMAND_HANDLER(arm920t_handle_cp15i_command)
 			retval = arm920t_write_cp15_interpreted(target,
 					opcode, value, 0);
 			if (retval != ERROR_OK) {
-				command_print(CMD_CTX,
+				command_print(CMD,
 					"couldn't execute %8.8" PRIx32,
 					opcode);
 				/* REVISIT why lie? "return retval"? */
 				return ERROR_OK;
 			}
-			command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32,
+			command_print(CMD, "%8.8" PRIx32 ": %8.8" PRIx32,
 				opcode, value);
 		} else if (CMD_ARGC == 3) {
 			uint32_t value;
@@ -1561,12 +1561,12 @@ COMMAND_HANDLER(arm920t_handle_cp15i_command)
 			retval = arm920t_write_cp15_interpreted(target,
 					opcode, value, address);
 			if (retval != ERROR_OK) {
-				command_print(CMD_CTX,
+				command_print(CMD,
 					"couldn't execute %8.8" PRIx32, opcode);
 				/* REVISIT why lie? "return retval"? */
 				return ERROR_OK;
 			}
-			command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32
+			command_print(CMD, "%8.8" PRIx32 ": %8.8" PRIx32
 				" %8.8" PRIx32, opcode, value, address);
 		}
 	} else
@@ -1581,11 +1581,11 @@ COMMAND_HANDLER(arm920t_handle_cache_info_command)
 	struct target *target = get_current_target(CMD_CTX);
 	struct arm920t_common *arm920t = target_to_arm920(target);
 
-	retval = arm920t_verify_pointer(CMD_CTX, arm920t);
+	retval = arm920t_verify_pointer(CMD, arm920t);
 	if (retval != ERROR_OK)
 		return retval;
 
-	return armv4_5_handle_cache_info_command(CMD_CTX,
+	return armv4_5_handle_cache_info_command(CMD,
 		&arm920t->armv4_5_mmu.armv4_5_cache);
 }
 
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 3f22a8a..ac30485 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -501,11 +501,11 @@ static void arm926ejs_pre_restore_context(struct target *target)
 
 static const char arm926_not[] = "target is not an ARM926";
 
-static int arm926ejs_verify_pointer(struct command_context *cmd_ctx,
+static int arm926ejs_verify_pointer(struct command_invocation *cmd,
 		struct arm926ejs_common *arm926)
 {
 	if (arm926->common_magic != ARM926EJS_COMMON_MAGIC) {
-		command_print(cmd_ctx, arm926_not);
+		command_print(cmd, arm926_not);
 		return ERROR_TARGET_INVALID;
 	}
 	return ERROR_OK;
@@ -729,11 +729,11 @@ COMMAND_HANDLER(arm926ejs_handle_cache_info_command)
 	struct target *target = get_current_target(CMD_CTX);
 	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
 
-	retval = arm926ejs_verify_pointer(CMD_CTX, arm926ejs);
+	retval = arm926ejs_verify_pointer(CMD, arm926ejs);
 	if (retval != ERROR_OK)
 		return retval;
 
-	return armv4_5_handle_cache_info_command(CMD_CTX, &arm926ejs->armv4_5_mmu.armv4_5_cache);
+	return armv4_5_handle_cache_info_command(CMD, &arm926ejs->armv4_5_mmu.armv4_5_cache);
 }
 
 static int arm926ejs_virt2phys(struct target *target, target_addr_t virtual, target_addr_t *physical)
diff --git a/src/target/arm946e.c b/src/target/arm946e.c
index 5e25d71..112631a 100644
--- a/src/target/arm946e.c
+++ b/src/target/arm946e.c
@@ -99,11 +99,11 @@ static int arm946e_target_create(struct target *target, Jim_Interp *interp)
 	return ERROR_OK;
 }
 
-static int arm946e_verify_pointer(struct command_context *cmd_ctx,
+static int arm946e_verify_pointer(struct command_invocation *cmd,
 	struct arm946e_common *arm946e)
 {
 	if (arm946e->common_magic != ARM946E_COMMON_MAGIC) {
-		command_print(cmd_ctx, "target is not an ARM946");
+		command_print(cmd, "target is not an ARM946");
 		return ERROR_TARGET_INVALID;
 	}
 	return ERROR_OK;
@@ -549,70 +549,54 @@ int arm946e_read_memory(struct target *target, target_addr_t address,
 	return ERROR_OK;
 }
 
-static int jim_arm946e_cp15(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
+COMMAND_HANDLER(arm946e_handle_cp15)
 {
 	/* one or two arguments, access a single register (write if second argument is given) */
-	if (argc < 2 || argc > 3) {
-		Jim_WrongNumArgs(interp, 1, argv, "addr [value]");
-		return JIM_ERR;
-	}
-
-	struct command_context *cmd_ctx = current_command_context(interp);
-	assert(cmd_ctx != NULL);
+	if (CMD_ARGC < 1 || CMD_ARGC > 2)
+		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	struct target *target = get_current_target(cmd_ctx);
-	if (target == NULL) {
-		LOG_ERROR("arm946e: no current target");
-		return JIM_ERR;
-	}
+	struct target *target = get_current_target(CMD_CTX);
 
 	struct arm946e_common *arm946e = target_to_arm946(target);
-	int retval = arm946e_verify_pointer(cmd_ctx, arm946e);
+	int retval = arm946e_verify_pointer(CMD, arm946e);
 	if (retval != ERROR_OK)
-		return JIM_ERR;
+		return retval;
 
 	if (target->state != TARGET_HALTED) {
-		command_print(cmd_ctx, "target %s must be stopped for \"cp15\" command", target_name(target));
-		return JIM_ERR;
+		command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
+		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	long l;
 	uint32_t address;
-	retval = Jim_GetLong(interp, argv[1], &l);
-	address = l;
-	if (JIM_OK != retval)
-		return retval;
+	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
 
-	if (argc == 2) {
+	if (CMD_ARGC == 1) {
 		uint32_t value;
 		retval = arm946e_read_cp15(target, address, &value);
 		if (retval != ERROR_OK) {
-			command_print(cmd_ctx, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
-			return JIM_ERR;
+			command_print(CMD, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
+			return retval;
 		}
 		retval = jtag_execute_queue();
 		if (retval != ERROR_OK)
-			return JIM_ERR;
-		char buf[20];
-		sprintf(buf, "0x%08" PRIx32, value);
+			return retval;
+
 		/* Return value in hex format */
-		Jim_SetResultString(interp, buf, -1);
-	} else if (argc == 3) {
+		command_print(CMD, "0x%08" PRIx32, value);
+	} else if (CMD_ARGC == 2) {
 		uint32_t value;
-		retval = Jim_GetLong(interp, argv[2], &l);
-		value = l;
-		if (JIM_OK != retval)
-			return retval;
+		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
+
 		retval = arm946e_write_cp15(target, address, value);
 		if (retval != ERROR_OK) {
-			command_print(cmd_ctx, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
-			return JIM_ERR;
+			command_print(CMD, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
+			return retval;
 		}
 		if (address == CP15_CTL)
 			arm946e_update_cp15_caches(target, value);
 	}
 
-	return JIM_OK;
+	return ERROR_OK;
 }
 
 COMMAND_HANDLER(arm946e_handle_idcache)
@@ -624,12 +608,12 @@ COMMAND_HANDLER(arm946e_handle_idcache)
 	struct target *target = get_current_target(CMD_CTX);
 	struct arm946e_common *arm946e = target_to_arm946(target);
 
-	retval = arm946e_verify_pointer(CMD_CTX, arm946e);
+	retval = arm946e_verify_pointer(CMD, arm946e);
 	if (retval != ERROR_OK)
 		return retval;
 
 	if (target->state != TARGET_HALTED) {
-		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+		command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
@@ -639,9 +623,9 @@ COMMAND_HANDLER(arm946e_handle_idcache)
 		bool  bena = ((arm946e->cp15_control_reg & (icache ? CP15_CTL_ICACHE : CP15_CTL_DCACHE)) != 0)
 			  && (arm946e->cp15_control_reg & 0x1);
 		if (csize == 0)
-			command_print(CMD_CTX, "%s-cache absent", icache ? "I" : "D");
+			command_print(CMD, "%s-cache absent", icache ? "I" : "D");
 		else
-			command_print(CMD_CTX, "%s-cache size: %" PRIu32 "K, %s",
+			command_print(CMD, "%s-cache size: %" PRIu32 "K, %s",
 				      icache ? "I" : "D", csize, bena ? "enabled" : "disabled");
 		return ERROR_OK;
 	}
@@ -659,7 +643,7 @@ COMMAND_HANDLER(arm946e_handle_idcache)
 
 	/* Do not invalidate or change state, if cache is absent */
 	if (csize == 0) {
-		command_print(CMD_CTX, "%s-cache absent, '%s' operation undefined", icache ? "I" : "D", CMD_ARGV[0]);
+		command_print(CMD, "%s-cache absent, '%s' operation undefined", icache ? "I" : "D", CMD_ARGV[0]);
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 
@@ -703,7 +687,7 @@ COMMAND_HANDLER(arm946e_handle_idcache)
 static const struct command_registration arm946e_exec_command_handlers[] = {
 	{
 		.name = "cp15",
-		.jim_handler = jim_arm946e_cp15,
+		.handler = arm946e_handle_cp15,
 		.mode = COMMAND_EXEC,
 		.usage = "regnum [value]",
 		.help = "read/modify cp15 register",
diff --git a/src/target/arm966e.c b/src/target/arm966e.c
index c9d7f01..8462f54 100644
--- a/src/target/arm966e.c
+++ b/src/target/arm966e.c
@@ -56,11 +56,11 @@ static int arm966e_target_create(struct target *target, Jim_Interp *interp)
 	return arm966e_init_arch_info(target, arm966e, target->tap);
 }
 
-static int arm966e_verify_pointer(struct command_context *cmd_ctx,
+static int arm966e_verify_pointer(struct command_invocation *cmd,
 		struct arm966e_common *arm966e)
 {
 	if (arm966e->common_magic != ARM966E_COMMON_MAGIC) {
-		command_print(cmd_ctx, "target is not an ARM966");
+		command_print(cmd, "target is not an ARM966");
 		return ERROR_TARGET_INVALID;
 	}
 	return ERROR_OK;
@@ -170,12 +170,12 @@ COMMAND_HANDLER(arm966e_handle_cp15_command)
 	struct target *target = get_current_target(CMD_CTX);
 	struct arm966e_common *arm966e = target_to_arm966(target);
 
-	retval = arm966e_verify_pointer(CMD_CTX, arm966e);
+	retval = arm966e_verify_pointer(CMD, arm966e);
 	if (retval != ERROR_OK)
 		return retval;
 
 	if (target->state != TARGET_HALTED) {
-		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+		command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
 		return ERROR_OK;
 	}
 
@@ -188,7 +188,7 @@ COMMAND_HANDLER(arm966e_handle_cp15_command)
 			uint32_t value;
 			retval = arm966e_read_cp15(target, address, &value);
 			if (retval != ERROR_OK) {
-				command_print(CMD_CTX,
+				command_print(CMD,
 						"couldn't access reg %" PRIi32,
 						address);
 				return ERROR_OK;
@@ -197,19 +197,19 @@ COMMAND_HANDLER(arm966e_handle_cp15_command)
 			if (retval != ERROR_OK)
 				return retval;
 
-			command_print(CMD_CTX, "%" PRIi32 ": %8.8" PRIx32,
+			command_print(CMD, "%" PRIi32 ": %8.8" PRIx32,
 					address, value);
 		} else if (CMD_ARGC == 2) {
 			uint32_t value;
 			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
 			retval = arm966e_write_cp15(target, address, value);
 			if (retval != ERROR_OK) {
-				command_print(CMD_CTX,
+				command_print(CMD,
 						"couldn't access reg %" PRIi32,
 						address);
 				return ERROR_OK;
 			}
-			command_print(CMD_CTX, "%" PRIi32 ": %8.8" PRIx32,
+			command_print(CMD, "%" PRIi32 ": %8.8" PRIx32,
 					address, value);
 		}
 	}
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 6425027..6ab06ed 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -801,7 +801,7 @@ COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command)
 	/* it's uncommon, but some ARM7 chips can support this */
 	if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC
 			|| !arm7_9->has_vector_catch) {
-		command_print(CMD_CTX, "target doesn't have EmbeddedICE "
+		command_print(CMD, "target doesn't have EmbeddedICE "
 				"with vector_catch");
 		return ERROR_TARGET_INVALID;
 	}
@@ -834,7 +834,7 @@ COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command)
 
 				/* complain if vector wasn't found */
 				if (!arm9tdmi_vectors[j].name) {
-					command_print(CMD_CTX, "vector '%s' not found, leaving current setting unchanged", CMD_ARGV[i]);
+					command_print(CMD, "vector '%s' not found, leaving current setting unchanged", CMD_ARGV[i]);
 
 					/* reread current setting */
 					vector_catch_value = buf_get_u32(
@@ -852,7 +852,7 @@ COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command)
 
 	/* output current settings */
 	for (unsigned i = 0; arm9tdmi_vectors[i].name; i++) {
-		command_print(CMD_CTX, "%s: %s", arm9tdmi_vectors[i].name,
+		command_print(CMD, "%s: %s", arm9tdmi_vectors[i].name,
 			(vector_catch_value & arm9tdmi_vectors[i].value)
 				? "catch" : "don't catch");
 	}
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 021d02a..d2ec960 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -914,7 +914,8 @@ int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_a
 			((id_val & IDR_TYPE) == type_to_find)) {      /* type matches*/
 
 			LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
-						(type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
+						(type_to_find == AP_TYPE_AHB3_AP)  ? "AHB3-AP"  :
+						(type_to_find == AP_TYPE_AHB5_AP)  ? "AHB5-AP"  :
 						(type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 						(type_to_find == AP_TYPE_AXI_AP)  ? "AXI-AP"  :
 						(type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
@@ -926,7 +927,8 @@ int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_a
 	}
 
 	LOG_DEBUG("No %s found",
-				(type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
+				(type_to_find == AP_TYPE_AHB3_AP)  ? "AHB3-AP"  :
+				(type_to_find == AP_TYPE_AHB5_AP)  ? "AHB5-AP"  :
 				(type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 				(type_to_find == AP_TYPE_AXI_AP)  ? "AXI-AP"  :
 				(type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
@@ -1190,7 +1192,7 @@ static const struct {
 	{ ANY_ID, 0x343, "TI DAPCTL",                  "", }, /* from OMAP3 memmap */
 };
 
-static int dap_rom_display(struct command_context *cmd_ctx,
+static int dap_rom_display(struct command_invocation *cmd,
 				struct adiv5_ap *ap, uint32_t dbgbase, int depth)
 {
 	int retval;
@@ -1199,7 +1201,7 @@ static int dap_rom_display(struct command_context *cmd_ctx,
 	char tabs[16] = "";
 
 	if (depth > 16) {
-		command_print(cmd_ctx, "\tTables too deep");
+		command_print(cmd, "\tTables too deep");
 		return ERROR_FAIL;
 	}
 
@@ -1207,25 +1209,25 @@ static int dap_rom_display(struct command_context *cmd_ctx,
 		snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
 
 	uint32_t base_addr = dbgbase & 0xFFFFF000;
-	command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr);
+	command_print(cmd, "\t\tComponent base address 0x%08" PRIx32, base_addr);
 
 	retval = dap_read_part_id(ap, base_addr, &cid, &pid);
 	if (retval != ERROR_OK) {
-		command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off");
+		command_print(cmd, "\t\tCan't read component, the corresponding core might be turned off");
 		return ERROR_OK; /* Don't abort recursion */
 	}
 
 	if (!is_dap_cid_ok(cid)) {
-		command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid);
+		command_print(cmd, "\t\tInvalid CID 0x%08" PRIx32, cid);
 		return ERROR_OK; /* Don't abort recursion */
 	}
 
 	/* component may take multiple 4K pages */
 	uint32_t size = (pid >> 36) & 0xf;
 	if (size > 0)
-		command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
+		command_print(cmd, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
 
-	command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid);
+	command_print(cmd, "\t\tPeripheral ID 0x%010" PRIx64, pid);
 
 	uint8_t class = (cid >> 12) & 0xf;
 	uint16_t part_num = pid & 0xfff;
@@ -1233,12 +1235,12 @@ static int dap_rom_display(struct command_context *cmd_ctx,
 
 	if (designer_id & 0x80) {
 		/* JEP106 code */
-		command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s",
+		command_print(cmd, "\t\tDesigner is 0x%03" PRIx16 ", %s",
 				designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
 	} else {
 		/* Legacy ASCII ID, clear invalid bits */
 		designer_id &= 0x7f;
-		command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
+		command_print(cmd, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
 				designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
 	}
 
@@ -1260,8 +1262,8 @@ static int dap_rom_display(struct command_context *cmd_ctx,
 		break;
 	}
 
-	command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
-	command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
+	command_print(cmd, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
+	command_print(cmd, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
 
 	if (class == 1) { /* ROM Table */
 		uint32_t memtype;
@@ -1270,9 +1272,9 @@ static int dap_rom_display(struct command_context *cmd_ctx,
 			return retval;
 
 		if (memtype & 0x01)
-			command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus");
+			command_print(cmd, "\t\tMEMTYPE system memory present on bus");
 		else
-			command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus");
+			command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus");
 
 		/* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
 		for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
@@ -1280,17 +1282,17 @@ static int dap_rom_display(struct command_context *cmd_ctx,
 			retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
 			if (retval != ERROR_OK)
 				return retval;
-			command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
+			command_print(cmd, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
 					tabs, entry_offset, romentry);
 			if (romentry & 0x01) {
 				/* Recurse */
-				retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
+				retval = dap_rom_display(cmd, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
 				if (retval != ERROR_OK)
 					return retval;
 			} else if (romentry != 0) {
-				command_print(cmd_ctx, "\t\tComponent not present");
+				command_print(cmd, "\t\tComponent not present");
 			} else {
-				command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
+				command_print(cmd, "\t%s\tEnd of ROM table", tabs);
 				break;
 			}
 		}
@@ -1412,7 +1414,7 @@ static int dap_rom_display(struct command_context *cmd_ctx,
 			}
 			break;
 		case 6:
-			major = "Perfomance Monitor";
+			major = "Performance Monitor";
 			switch (minor) {
 			case 0:
 				subtype = "other";
@@ -1435,7 +1437,7 @@ static int dap_rom_display(struct command_context *cmd_ctx,
 			}
 			break;
 		}
-		command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
+		command_print(cmd, "\t\tType is 0x%02" PRIx8 ", %s, %s",
 				(uint8_t)(devtype & 0xff),
 				major, subtype);
 		/* REVISIT also show 0xfc8 DevId */
@@ -1444,7 +1446,7 @@ static int dap_rom_display(struct command_context *cmd_ctx,
 	return ERROR_OK;
 }
 
-int dap_info_command(struct command_context *cmd_ctx,
+int dap_info_command(struct command_invocation *cmd,
 		struct adiv5_ap *ap)
 {
 	int retval;
@@ -1456,27 +1458,30 @@ int dap_info_command(struct command_context *cmd_ctx,
 	if (retval != ERROR_OK)
 		return retval;
 
-	command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
+	command_print(cmd, "AP ID register 0x%8.8" PRIx32, apid);
 	if (apid == 0) {
-		command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
+		command_print(cmd, "No AP found at this ap 0x%x", ap->ap_num);
 		return ERROR_FAIL;
 	}
 
 	switch (apid & (IDR_JEP106 | IDR_TYPE)) {
 	case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
-		command_print(cmd_ctx, "\tType is JTAG-AP");
+		command_print(cmd, "\tType is JTAG-AP");
 		break;
-	case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
-		command_print(cmd_ctx, "\tType is MEM-AP AHB");
+	case IDR_JEP106_ARM | AP_TYPE_AHB3_AP:
+		command_print(cmd, "\tType is MEM-AP AHB3");
+		break;
+	case IDR_JEP106_ARM | AP_TYPE_AHB5_AP:
+		command_print(cmd, "\tType is MEM-AP AHB5");
 		break;
 	case IDR_JEP106_ARM | AP_TYPE_APB_AP:
-		command_print(cmd_ctx, "\tType is MEM-AP APB");
+		command_print(cmd, "\tType is MEM-AP APB");
 		break;
 	case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
-		command_print(cmd_ctx, "\tType is MEM-AP AXI");
+		command_print(cmd, "\tType is MEM-AP AXI");
 		break;
 	default:
-		command_print(cmd_ctx, "\tUnknown AP type");
+		command_print(cmd, "\tUnknown AP type");
 		break;
 	}
 
@@ -1485,17 +1490,17 @@ int dap_info_command(struct command_context *cmd_ctx,
 	 */
 	mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
 	if (mem_ap) {
-		command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
+		command_print(cmd, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
 
 		if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
-			command_print(cmd_ctx, "\tNo ROM table present");
+			command_print(cmd, "\tNo ROM table present");
 		} else {
 			if (dbgbase & 0x01)
-				command_print(cmd_ctx, "\tValid ROM table present");
+				command_print(cmd, "\tValid ROM table present");
 			else
-				command_print(cmd_ctx, "\tROM table in legacy format");
+				command_print(cmd, "\tROM table in legacy format");
 
-			dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0);
+			dap_rom_display(cmd, ap, dbgbase & 0xFFFFF000, 0);
 		}
 	}
 
@@ -1646,7 +1651,7 @@ COMMAND_HANDLER(handle_dap_info_command)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
-	return dap_info_command(CMD_CTX, &dap->ap[apsel]);
+	return dap_info_command(CMD, &dap->ap[apsel]);
 }
 
 COMMAND_HANDLER(dap_baseaddr_command)
@@ -1681,7 +1686,7 @@ COMMAND_HANDLER(dap_baseaddr_command)
 	if (retval != ERROR_OK)
 		return retval;
 
-	command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
+	command_print(CMD, "0x%8.8" PRIx32, baseaddr);
 
 	return retval;
 }
@@ -1703,7 +1708,7 @@ COMMAND_HANDLER(dap_memaccess_command)
 	}
 	dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
 
-	command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
+	command_print(CMD, "memory bus access delay set to %" PRIi32 " tck",
 			dap->ap[dap->apsel].memaccess_tck);
 
 	return ERROR_OK;
@@ -1716,7 +1721,7 @@ COMMAND_HANDLER(dap_apsel_command)
 
 	switch (CMD_ARGC) {
 	case 0:
-		command_print(CMD_CTX, "%" PRIi32, dap->apsel);
+		command_print(CMD, "%" PRIi32, dap->apsel);
 		return ERROR_OK;
 	case 1:
 		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
@@ -1740,12 +1745,12 @@ COMMAND_HANDLER(dap_apcsw_command)
 
 	switch (CMD_ARGC) {
 	case 0:
-		command_print(CMD_CTX, "ap %" PRIi32 " selected, csw 0x%8.8" PRIx32,
+		command_print(CMD, "ap %" PRIi32 " selected, csw 0x%8.8" PRIx32,
 			dap->apsel, apcsw);
 		return ERROR_OK;
 	case 1:
 		if (strcmp(CMD_ARGV[0], "default") == 0)
-			csw_val = CSW_DEFAULT;
+			csw_val = CSW_AHB_DEFAULT;
 		else
 			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
 
@@ -1801,7 +1806,7 @@ COMMAND_HANDLER(dap_apid_command)
 	if (retval != ERROR_OK)
 		return retval;
 
-	command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
+	command_print(CMD, "0x%8.8" PRIx32, apid);
 
 	return retval;
 }
@@ -1853,7 +1858,7 @@ COMMAND_HANDLER(dap_apreg_command)
 		return retval;
 
 	if (CMD_ARGC == 2)
-		command_print(CMD_CTX, "0x%08" PRIx32, value);
+		command_print(CMD, "0x%08" PRIx32, value);
 
 	return retval;
 }
@@ -1884,7 +1889,7 @@ COMMAND_HANDLER(dap_dpreg_command)
 		return retval;
 
 	if (CMD_ARGC == 1)
-		command_print(CMD_CTX, "0x%08" PRIx32, value);
+		command_print(CMD, "0x%08" PRIx32, value);
 
 	return retval;
 }
@@ -1906,7 +1911,7 @@ COMMAND_HANDLER(dap_ti_be_32_quirks_command)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 	dap->ti_be_32_quirks = enable;
-	command_print(CMD_CTX, "TI BE-32 quirks mode %s",
+	command_print(CMD, "TI BE-32 quirks mode %s",
 		enable ? "enabled" : "disabled");
 
 	return 0;
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 96291a7..6e2d8a1 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -112,15 +112,34 @@
 #define CSW_ADDRINC_PACKED  (2UL << 4)
 #define CSW_DEVICE_EN       (1UL << 6)
 #define CSW_TRIN_PROG       (1UL << 7)
-/* all fields in bits 12 and above are implementation-defined! */
+
+/* All fields in bits 12 and above are implementation-defined
+ * Defaults for AHB/AXI in "Standard Memory Access Port Definitions" from ADI
+ * Some bits are shared between buses
+ */
 #define CSW_SPIDEN          (1UL << 23)
-#define CSW_HPROT1          (1UL << 25) /* AHB: Privileged */
-#define CSW_MASTER_DEBUG    (1UL << 29) /* AHB: set HMASTER signals to AHB-AP ID */
-#define CSW_SPROT           (1UL << 30)
 #define CSW_DBGSWENABLE     (1UL << 31)
 
-/* initial value of csw_default used for MEM-AP transfers */
-#define CSW_DEFAULT			(CSW_HPROT1 | CSW_MASTER_DEBUG | CSW_DBGSWENABLE)
+/* AHB: Privileged */
+#define CSW_AHB_HPROT1          (1UL << 25)
+/* AHB: set HMASTER signals to AHB-AP ID */
+#define CSW_AHB_MASTER_DEBUG    (1UL << 29)
+/* AHB5: non-secure access via HNONSEC
+ * AHB3: SBO, UNPREDICTABLE if zero */
+#define CSW_AHB_SPROT           (1UL << 30)
+/* AHB: initial value of csw_default */
+#define CSW_AHB_DEFAULT         (CSW_AHB_HPROT1 | CSW_AHB_MASTER_DEBUG | CSW_DBGSWENABLE)
+
+/* AXI: Privileged */
+#define CSW_AXI_ARPROT0_PRIV    (1UL << 28)
+/* AXI: Non-secure */
+#define CSW_AXI_ARPROT1_NONSEC  (1UL << 29)
+/* AXI: initial value of csw_default */
+#define CSW_AXI_DEFAULT         (CSW_AXI_ARPROT0_PRIV | CSW_AXI_ARPROT1_NONSEC | CSW_DBGSWENABLE)
+
+/* APB: initial value of csw_default */
+#define CSW_APB_DEFAULT         (CSW_DBGSWENABLE)
+
 
 /* Fields of the MEM-AP's IDR register */
 #define IDR_REV     (0xFUL << 28)
@@ -307,9 +326,10 @@ enum ap_class {
  */
 enum ap_type {
 	AP_TYPE_JTAG_AP = 0x0,  /* JTAG-AP - JTAG master for controlling other JTAG devices */
-	AP_TYPE_AHB_AP  = 0x1,  /* AHB Memory-AP */
+	AP_TYPE_AHB3_AP = 0x1,  /* AHB3 Memory-AP */
 	AP_TYPE_APB_AP  = 0x2,  /* APB Memory-AP */
 	AP_TYPE_AXI_AP  = 0x4,  /* AXI Memory-AP */
+	AP_TYPE_AHB5_AP = 0x5,  /* AHB5 Memory-AP. */
 };
 
 /**
@@ -526,7 +546,7 @@ extern const struct command_registration dap_instance_commands[];
 struct arm_dap_object;
 extern struct adiv5_dap *dap_instance_by_jim_obj(Jim_Interp *interp, Jim_Obj *o);
 extern struct adiv5_dap *adiv5_get_dap(struct arm_dap_object *obj);
-extern int dap_info_command(struct command_context *cmd_ctx,
+extern int dap_info_command(struct command_invocation *cmd,
 					 struct adiv5_ap *ap);
 extern int dap_register_commands(struct command_context *cmd_ctx);
 extern const char *adiv5_dap_name(struct adiv5_dap *self);
diff --git a/src/target/arm_cti.c b/src/target/arm_cti.c
index f333792..3f063b8 100644
--- a/src/target/arm_cti.c
+++ b/src/target/arm_cti.c
@@ -252,7 +252,7 @@ COMMAND_HANDLER(handle_cti_dump)
 		return JIM_ERR;
 
 	for (int i = 0; i < (int)ARRAY_SIZE(cti_names); i++)
-		command_print(CMD_CTX, "%8.8s (0x%04"PRIx32") 0x%08"PRIx32,
+		command_print(CMD, "%8.8s (0x%04"PRIx32") 0x%08"PRIx32,
 				cti_names[i].label, cti_names[i].offset, *cti_names[i].p_val);
 
 	return JIM_OK;
@@ -336,7 +336,7 @@ COMMAND_HANDLER(handle_cti_read)
 	if (retval != ERROR_OK)
 		return retval;
 
-	command_print(CMD_CTX, "0x%08"PRIx32, value);
+	command_print(CMD, "0x%08"PRIx32, value);
 
 	return ERROR_OK;
 }
@@ -576,6 +576,7 @@ static const struct command_registration cti_command_handlers[] = {
 		.mode = COMMAND_CONFIG,
 		.help = "CTI commands",
 		.chain = cti_subcommand_handlers,
+		.usage = "",
 	},
 	COMMAND_REGISTRATION_DONE
 };
diff --git a/src/target/arm_dap.c b/src/target/arm_dap.c
index 119e511..fbcfe0d 100644
--- a/src/target/arm_dap.c
+++ b/src/target/arm_dap.c
@@ -56,7 +56,7 @@ static void dap_instance_init(struct adiv5_dap *dap)
 		/* Number of bits for tar autoincrement, impl. dep. at least 10 */
 		dap->ap[i].tar_autoincr_block = (1<<10);
 		/* default CSW value */
-		dap->ap[i].csw_default = CSW_DEFAULT;
+		dap->ap[i].csw_default = CSW_AHB_DEFAULT;
 	}
 	INIT_LIST_HEAD(&dap->cmd_journal);
 }
@@ -331,7 +331,7 @@ COMMAND_HANDLER(handle_dap_info_command)
 			return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
-	return dap_info_command(CMD_CTX, &dap->ap[apsel]);
+	return dap_info_command(CMD, &dap->ap[apsel]);
 }
 
 static const struct command_registration dap_subcommand_handlers[] = {
@@ -373,6 +373,7 @@ static const struct command_registration dap_commands[] = {
 		.mode = COMMAND_CONFIG,
 		.help = "DAP commands",
 		.chain = dap_subcommand_handlers,
+		.usage = "",
 	},
 	COMMAND_REGISTRATION_DONE
 };
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index e16a9ec..53a6b22 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -778,17 +778,17 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
 	struct reg *regs;
 
 	if (!is_arm(arm)) {
-		command_print(CMD_CTX, "current target isn't an ARM");
+		command_print(CMD, "current target isn't an ARM");
 		return ERROR_FAIL;
 	}
 
 	if (target->state != TARGET_HALTED) {
-		command_print(CMD_CTX, "error: target must be halted for register accesses");
+		command_print(CMD, "error: target must be halted for register accesses");
 		return ERROR_FAIL;
 	}
 
 	if (arm->core_type != ARM_MODE_ANY) {
-		command_print(CMD_CTX,
+		command_print(CMD,
 			"Microcontroller Profile not supported - use standard reg cmd");
 		return ERROR_OK;
 	}
@@ -799,7 +799,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
 	}
 
 	if (!arm->full_context) {
-		command_print(CMD_CTX, "error: target doesn't support %s",
+		command_print(CMD, "error: target doesn't support %s",
 			CMD_NAME);
 		return ERROR_FAIL;
 	}
@@ -828,7 +828,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
 				shadow = "shadow ";
 				break;
 		}
-		command_print(CMD_CTX, "%s%s mode %sregisters",
+		command_print(CMD, "%s%s mode %sregisters",
 			sep, name, shadow);
 
 		/* display N rows of up to 4 registers each */
@@ -855,7 +855,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
 						"%8s: %8.8" PRIx32 " ",
 						reg->name, value);
 			}
-			command_print(CMD_CTX, "%s", output);
+			command_print(CMD, "%s", output);
 		}
 	}
 
@@ -868,13 +868,13 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command)
 	struct arm *arm = target_to_arm(target);
 
 	if (!is_arm(arm)) {
-		command_print(CMD_CTX, "current target isn't an ARM");
+		command_print(CMD, "current target isn't an ARM");
 		return ERROR_FAIL;
 	}
 
 	if (arm->core_type == ARM_MODE_THREAD) {
 		/* armv7m not supported */
-		command_print(CMD_CTX, "Unsupported Command");
+		command_print(CMD, "Unsupported Command");
 		return ERROR_OK;
 	}
 
@@ -885,7 +885,7 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command)
 			arm->core_state = ARM_STATE_THUMB;
 	}
 
-	command_print(CMD_CTX, "core state: %s", arm_state_strings[arm->core_state]);
+	command_print(CMD, "core state: %s", arm_state_strings[arm->core_state]);
 
 	return ERROR_OK;
 }
@@ -906,7 +906,7 @@ COMMAND_HANDLER(handle_arm_disassemble_command)
 	int thumb = 0;
 
 	if (!is_arm(arm)) {
-		command_print(CMD_CTX, "current target isn't an ARM");
+		command_print(CMD, "current target isn't an ARM");
 		return ERROR_FAIL;
 	}
 
@@ -928,7 +928,7 @@ COMMAND_HANDLER(handle_arm_disassemble_command)
 			COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
 			if (address & 0x01) {
 				if (!thumb) {
-					command_print(CMD_CTX, "Disassemble as Thumb");
+					command_print(CMD, "Disassemble as Thumb");
 					thumb = 1;
 				}
 				address &= ~1;
@@ -963,7 +963,7 @@ usage:
 			if (retval != ERROR_OK)
 				break;
 		}
-		command_print(CMD_CTX, "%s", cur_instruction.text);
+		command_print(CMD, "%s", cur_instruction.text);
 		address += cur_instruction.instruction_size;
 	}
 
@@ -1140,28 +1140,28 @@ static const struct command_registration arm_exec_command_handlers[] = {
 		.usage = "cpnum op1 CRn CRm op2",
 	},
 	{
-		"semihosting",
+		.name = "semihosting",
 		.handler = handle_common_semihosting_command,
 		.mode = COMMAND_EXEC,
 		.usage = "['enable'|'disable']",
 		.help = "activate support for semihosting operations",
 	},
 	{
-		"semihosting_cmdline",
+		.name = "semihosting_cmdline",
 		.handler = handle_common_semihosting_cmdline,
 		.mode = COMMAND_EXEC,
 		.usage = "arguments",
 		.help = "command line arguments to be passed to program",
 	},
 	{
-		"semihosting_fileio",
+		.name = "semihosting_fileio",
 		.handler = handle_common_semihosting_fileio_command,
 		.mode = COMMAND_EXEC,
 		.usage = "['enable'|'disable']",
 		.help = "activate support for semihosting fileio operations",
 	},
 	{
-		"semihosting_resexit",
+		.name = "semihosting_resexit",
 		.handler = handle_common_semihosting_resumable_exit_command,
 		.mode = COMMAND_EXEC,
 		.usage = "['enable'|'disable']",
diff --git a/src/target/armv4_5_cache.c b/src/target/armv4_5_cache.c
index bd0091d..eda8cb7 100644
--- a/src/target/armv4_5_cache.c
+++ b/src/target/armv4_5_cache.c
@@ -76,23 +76,23 @@ int armv4_5_identify_cache(uint32_t cache_type_reg, struct armv4_5_cache_common
 	return ERROR_OK;
 }
 
-int armv4_5_handle_cache_info_command(struct command_context *cmd_ctx, struct armv4_5_cache_common *armv4_5_cache)
+int armv4_5_handle_cache_info_command(struct command_invocation *cmd, struct armv4_5_cache_common *armv4_5_cache)
 {
 	if (armv4_5_cache->ctype == -1) {
-		command_print(cmd_ctx, "cache not yet identified");
+		command_print(cmd, "cache not yet identified");
 		return ERROR_OK;
 	}
 
-	command_print(cmd_ctx, "cache type: 0x%1.1x, %s", armv4_5_cache->ctype,
+	command_print(cmd, "cache type: 0x%1.1x, %s", armv4_5_cache->ctype,
 		(armv4_5_cache->separate) ? "separate caches" : "unified cache");
 
-	command_print(cmd_ctx, "D-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x",
+	command_print(cmd, "D-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x",
 		armv4_5_cache->d_u_size.linelen,
 		armv4_5_cache->d_u_size.associativity,
 		armv4_5_cache->d_u_size.nsets,
 		armv4_5_cache->d_u_size.cachesize);
 
-	command_print(cmd_ctx, "I-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x",
+	command_print(cmd, "I-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x",
 		armv4_5_cache->i_size.linelen,
 		armv4_5_cache->i_size.associativity,
 		armv4_5_cache->i_size.nsets,
diff --git a/src/target/armv4_5_cache.h b/src/target/armv4_5_cache.h
index 2fd1ca3..768938f 100644
--- a/src/target/armv4_5_cache.h
+++ b/src/target/armv4_5_cache.h
@@ -19,7 +19,7 @@
 #ifndef OPENOCD_TARGET_ARMV4_5_CACHE_H
 #define OPENOCD_TARGET_ARMV4_5_CACHE_H
 
-struct command_context;
+struct command_invocation;
 
 struct armv4_5_cachesize {
 	int linelen;
@@ -42,7 +42,7 @@ int armv4_5_identify_cache(uint32_t cache_type_reg,
 int armv4_5_cache_state(uint32_t cp15_control_reg,
 		struct armv4_5_cache_common *cache);
 
-int armv4_5_handle_cache_info_command(struct command_context *cmd_ctx,
+int armv4_5_handle_cache_info_command(struct command_invocation *cmd,
 		struct armv4_5_cache_common *armv4_5_cache);
 
 enum {
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index f9594c9..2be70b7 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -229,7 +229,7 @@ COMMAND_HANDLER(handle_cache_l2x)
 	if (CMD_ARGC != 2)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	/* command_print(CMD_CTX, "%s %s", CMD_ARGV[0], CMD_ARGV[1]); */
+	/* command_print(CMD, "%s %s", CMD_ARGV[0], CMD_ARGV[1]); */
 	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], base);
 	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], way);
 
@@ -239,7 +239,7 @@ COMMAND_HANDLER(handle_cache_l2x)
 	return ERROR_OK;
 }
 
-int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
+int armv7a_handle_cache_info_command(struct command_invocation *cmd,
 	struct armv7a_cache_common *armv7a_cache)
 {
 	struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
@@ -248,7 +248,7 @@ int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
 	int cl;
 
 	if (armv7a_cache->info == -1) {
-		command_print(cmd_ctx, "cache not yet identified");
+		command_print(cmd, "cache not yet identified");
 		return ERROR_OK;
 	}
 
@@ -256,7 +256,7 @@ int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
 		struct armv7a_arch_cache *arch = &(armv7a_cache->arch[cl]);
 
 		if (arch->ctype & 1) {
-			command_print(cmd_ctx,
+			command_print(cmd,
 				"L%d I-Cache: linelen %" PRIi32
 				", associativity %" PRIi32
 				", nsets %" PRIi32
@@ -269,7 +269,7 @@ int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
 		}
 
 		if (arch->ctype >= 2) {
-			command_print(cmd_ctx,
+			command_print(cmd,
 				"L%d D-Cache: linelen %" PRIi32
 				", associativity %" PRIi32
 				", nsets %" PRIi32
@@ -283,7 +283,7 @@ int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
 	}
 
 	if (l2x_cache != NULL)
-		command_print(cmd_ctx, "Outer unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways",
+		command_print(cmd, "Outer unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways",
 			l2x_cache->base, l2x_cache->way);
 
 	return ERROR_OK;
@@ -307,23 +307,21 @@ static int armv7a_read_mpidr(struct target *target)
 	if (retval != ERROR_OK)
 		goto done;
 
-	/* ARMv7R uses a different format for MPIDR.
-	 * When configured uniprocessor (most R cores) it reads as 0.
-	 * This will need to be implemented for multiprocessor ARMv7R cores. */
-	if (armv7a->is_armv7r) {
-		if (mpidr)
-			LOG_ERROR("MPIDR nonzero in ARMv7-R target");
-		goto done;
-	}
-
-	if (mpidr & 1<<31) {
+	/* Is register in Multiprocessing Extensions register format? */
+	if (mpidr & MPIDR_MP_EXT) {
+		LOG_DEBUG("%s: MPIDR 0x%" PRIx32, target_name(target), mpidr);
 		armv7a->multi_processor_system = (mpidr >> 30) & 1;
+		armv7a->multi_threading_processor = (mpidr >> 24) & 1;
+		armv7a->level2_id = (mpidr >> 16) & 0xf;
 		armv7a->cluster_id = (mpidr >> 8) & 0xf;
-		armv7a->cpu_id = mpidr & 0x3;
-		LOG_INFO("%s cluster %x core %x %s", target_name(target),
+		armv7a->cpu_id = mpidr & 0xf;
+		LOG_INFO("%s: MPIDR level2 %x, cluster %x, core %x, %s, %s",
+			target_name(target),
+			armv7a->level2_id,
 			armv7a->cluster_id,
 			armv7a->cpu_id,
-			armv7a->multi_processor_system == 0 ? "multi core" : "mono core");
+			armv7a->multi_processor_system == 0 ? "multi core" : "mono core",
+			armv7a->multi_threading_processor == 1 ? "SMT" : "no SMT");
 
 	} else
 		LOG_ERROR("MPIDR not in multiprocessor format");
@@ -584,8 +582,7 @@ static const struct command_registration l2_cache_commands[] = {
 		.name = "l2x",
 		.handler = handle_cache_l2x,
 		.mode = COMMAND_EXEC,
-		.help = "configure l2x cache "
-			"",
+		.help = "configure l2x cache",
 		.usage = "[base_addr] [number_of_way]",
 	},
 	COMMAND_REGISTRATION_DONE
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 1e88c98..0ef04c1 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -108,6 +108,8 @@ struct armv7a_common {
 	struct adiv5_ap *debug_ap;
 	/* mdir */
 	uint8_t multi_processor_system;
+	uint8_t multi_threading_processor;
+	uint8_t level2_id;
 	uint8_t cluster_id;
 	uint8_t cpu_id;
 	bool is_armv7r;
@@ -183,11 +185,14 @@ static inline bool is_armv7a(struct armv7a_common *armv7a)
 #define DBG_VCR_PREF_ABORT_MASK	((1 << 27) | (1 << 3))
 #define DBG_VCR_SVC_MASK	((1 << 26) | (1 << 2))
 
+/* Masks for Multiprocessor Affinity Register */
+#define MPIDR_MP_EXT		(1UL << 31)
+
 int armv7a_arch_state(struct target *target);
 int armv7a_identify_cache(struct target *target);
 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
 
-int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
+int armv7a_handle_cache_info_command(struct command_invocation *cmd,
 		struct armv7a_cache_common *armv7a_cache);
 int armv7a_read_ttbcr(struct target *target);
 
diff --git a/src/target/armv7a_cache.c b/src/target/armv7a_cache.c
index 7435aab..921ba9b 100644
--- a/src/target/armv7a_cache.c
+++ b/src/target/armv7a_cache.c
@@ -431,7 +431,7 @@ COMMAND_HANDLER(arm7a_l1_cache_info_cmd)
 	struct target *target = get_current_target(CMD_CTX);
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 
-	return armv7a_handle_cache_info_command(CMD_CTX,
+	return armv7a_handle_cache_info_command(CMD,
 			&armv7a->armv7a_mmu.armv7a_cache);
 }
 
@@ -513,7 +513,7 @@ COMMAND_HANDLER(arm7a_cache_disable_auto_cmd)
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 
 	if (CMD_ARGC == 0) {
-		command_print(CMD_CTX, "auto cache is %s",
+		command_print(CMD, "auto cache is %s",
 			armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled ? "enabled" : "disabled");
 		return ERROR_OK;
 	}
diff --git a/src/target/armv7a_cache_l2x.c b/src/target/armv7a_cache_l2x.c
index e181f26..72e12b4 100644
--- a/src/target/armv7a_cache_l2x.c
+++ b/src/target/armv7a_cache_l2x.c
@@ -173,18 +173,18 @@ done:
 	return retval;
 }
 
-static int arm7a_handle_l2x_cache_info_command(struct command_context *cmd_ctx,
+static int arm7a_handle_l2x_cache_info_command(struct command_invocation *cmd,
 	struct armv7a_cache_common *armv7a_cache)
 {
 	struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
 		(armv7a_cache->outer_cache);
 
 	if (armv7a_cache->info == -1) {
-		command_print(cmd_ctx, "cache not yet identified");
+		command_print(cmd, "cache not yet identified");
 		return ERROR_OK;
 	}
 
-	command_print(cmd_ctx,
+	command_print(cmd,
 		      "L2 unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways",
 		      l2x_cache->base, l2x_cache->way);
 
@@ -235,7 +235,7 @@ COMMAND_HANDLER(arm7a_l2x_cache_info_command)
 	if (retval)
 		return retval;
 
-	return arm7a_handle_l2x_cache_info_command(CMD_CTX,
+	return arm7a_handle_l2x_cache_info_command(CMD,
 			&armv7a->armv7a_mmu.armv7a_cache);
 }
 
@@ -312,7 +312,7 @@ COMMAND_HANDLER(armv7a_l2x_cache_conf_cmd)
 	if (CMD_ARGC != 2)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	/* command_print(CMD_CTX, "%s %s", CMD_ARGV[0], CMD_ARGV[1]); */
+	/* command_print(CMD, "%s %s", CMD_ARGV[0], CMD_ARGV[1]); */
 	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], base);
 	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], way);
 
diff --git a/src/target/armv7a_mmu.c b/src/target/armv7a_mmu.c
index 153bfcc..f83228d 100644
--- a/src/target/armv7a_mmu.c
+++ b/src/target/armv7a_mmu.c
@@ -34,101 +34,15 @@
 
 #define SCTLR_BIT_AFE (1 << 29)
 
-/*  method adapted to Cortex-A : reused ARM v4 v5 method */
-int armv7a_mmu_translate_va(struct target *target,  uint32_t va, uint32_t *val)
-{
-	uint32_t first_lvl_descriptor = 0x0;
-	uint32_t second_lvl_descriptor = 0x0;
-	int retval;
-	struct armv7a_common *armv7a = target_to_armv7a(target);
-	uint32_t ttbidx = 0;	/*  default to ttbr0 */
-	uint32_t ttb_mask;
-	uint32_t va_mask;
-	uint32_t ttb;
-
-	if (target->state != TARGET_HALTED)
-		LOG_INFO("target not halted, using cached values for translation table!");
-
-	/* if va is above the range handled by ttbr0, select ttbr1 */
-	if (va > armv7a->armv7a_mmu.ttbr_range[0]) {
-		/*  select ttb 1 */
-		ttbidx = 1;
-	}
-
-	ttb = armv7a->armv7a_mmu.ttbr[ttbidx];
-	ttb_mask = armv7a->armv7a_mmu.ttbr_mask[ttbidx];
-	va_mask = 0xfff00000 & armv7a->armv7a_mmu.ttbr_range[ttbidx];
-
-	LOG_DEBUG("ttb_mask %" PRIx32 " va_mask %" PRIx32 " ttbidx %i",
-		  ttb_mask, va_mask, ttbidx);
-	retval = armv7a->armv7a_mmu.read_physical_memory(target,
-			(ttb & ttb_mask) | ((va & va_mask) >> 18),
-			4, 1, (uint8_t *)&first_lvl_descriptor);
-	if (retval != ERROR_OK)
-		return retval;
-	first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)
-			&first_lvl_descriptor);
-	/*  reuse armv4_5 piece of code, specific armv7a changes may come later */
-	LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
-
-	if ((first_lvl_descriptor & 0x3) == 0) {
-		/* Avoid LOG_ERROR, probably GDB is guessing the stack frame */
-		LOG_WARNING("Address translation failure [1]: va %8.8" PRIx32 "", va);
-		return ERROR_TARGET_TRANSLATION_FAULT;
-	}
-
-	if ((first_lvl_descriptor & 0x40002) == 2) {
-		/* section descriptor */
-		*val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
-		return ERROR_OK;
-	} else if ((first_lvl_descriptor & 0x40002) == 0x40002) {
-		/* supersection descriptor */
-		if (first_lvl_descriptor & 0x00f001e0) {
-			LOG_ERROR("Physical address does not fit into 32 bits");
-			return ERROR_TARGET_TRANSLATION_FAULT;
-		}
-		*val = (first_lvl_descriptor & 0xff000000) | (va & 0x00ffffff);
-		return ERROR_OK;
-	}
-
-	/* page table */
-	retval = armv7a->armv7a_mmu.read_physical_memory(target,
-			(first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
-			4, 1, (uint8_t *)&second_lvl_descriptor);
-	if (retval != ERROR_OK)
-		return retval;
-
-	second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)
-			&second_lvl_descriptor);
-
-	LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
-
-	if ((second_lvl_descriptor & 0x3) == 0) {
-		/* Avoid LOG_ERROR, probably GDB is guessing the stack frame */
-		LOG_WARNING("Address translation failure [2]: va %8.8" PRIx32 "", va);
-		return ERROR_TARGET_TRANSLATION_FAULT;
-	}
-
-	if ((second_lvl_descriptor & 0x3) == 1) {
-		/* large page descriptor */
-		*val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
-	} else {
-		/* small page descriptor */
-		*val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
-	}
-
-	return ERROR_OK;
-}
-
 /*  V7 method VA TO PA  */
 int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
-	uint32_t *val, int meminfo)
+	target_addr_t *val, int meminfo)
 {
 	int retval = ERROR_FAIL;
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct arm_dpm *dpm = armv7a->arm.dpm;
-	uint32_t virt = va & ~0xfff;
-	uint32_t NOS, NS, INNER, OUTER;
+	uint32_t virt = va & ~0xfff, value;
+	uint32_t NOS, NS, INNER, OUTER, SS;
 	*val = 0xdeadbeef;
 	retval = dpm->prepare(dpm);
 	if (retval != ERROR_OK)
@@ -142,21 +56,39 @@ int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
 		goto done;
 	retval = dpm->instr_read_data_r0(dpm,
 			ARMV4_5_MRC(15, 0, 0, 7, 4, 0),
-			val);
-	/* decode memory attribute */
-	NOS = (*val >> 10) & 1;	/*  Not Outer shareable */
-	NS = (*val >> 9) & 1;	/* Non secure */
-	INNER = (*val >> 4) &  0x7;
-	OUTER = (*val >> 2) & 0x3;
-
+			&value);
 	if (retval != ERROR_OK)
 		goto done;
-	*val = (*val & ~0xfff)  +  (va & 0xfff);
+
+	/* decode memory attribute */
+	SS = (value >> 1) & 1;
+#if !BUILD_TARGET64
+	if (SS) {
+		LOG_ERROR("Super section found with no-64 bit address support");
+		return ERROR_FAIL;
+	}
+#endif
+	NOS = (value >> 10) & 1;	/*  Not Outer shareable */
+	NS = (value >> 9) & 1;	/* Non secure */
+	INNER = (value >> 4) &  0x7;
+	OUTER = (value >> 2) & 0x3;
+
+	if (SS) {
+		/* PAR[31:24] contains PA[31:24] */
+		*val = value & 0xff000000;
+		/* PAR [23:16] contains PA[39:32] */
+		*val |= (target_addr_t)(value & 0x00ff0000) << 16;
+		/* PA[23:12] is the same as VA[23:12] */
+		*val |= (va & 0xffffff);
+	} else {
+		*val = (value & ~0xfff)  +  (va & 0xfff);
+	}
 	if (meminfo) {
-		LOG_INFO("%" PRIx32 " : %" PRIx32 " %s outer shareable %s secured",
+		LOG_INFO("%" PRIx32 " : %" TARGET_PRIxADDR " %s outer shareable %s secured %s super section",
 			va, *val,
 			NOS == 1 ? "not" : " ",
-			NS == 1 ? "not" : "");
+			NS == 1 ? "not" : "",
+			SS == 0 ? "not" : "");
 		switch (OUTER) {
 			case 0:
 				LOG_INFO("outer: Non-Cacheable");
diff --git a/src/target/armv7a_mmu.h b/src/target/armv7a_mmu.h
index 4372aa8..36cd9d1 100644
--- a/src/target/armv7a_mmu.h
+++ b/src/target/armv7a_mmu.h
@@ -19,9 +19,8 @@
 #ifndef OPENOCD_TARGET_ARMV7A_MMU_H
 #define OPENOCD_TARGET_ARMV7A_MMU_H
 
-extern int armv7a_mmu_translate_va(struct target *target,  uint32_t va, uint32_t *val);
 extern int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
-	uint32_t *val, int meminfo);
+	target_addr_t *val, int meminfo);
 
 extern const struct command_registration armv7a_mmu_command_handlers[];
 
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 3d73b29..4b37774 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -191,7 +191,7 @@ static int armv7m_get_core_reg(struct reg *reg)
 	if (target->state != TARGET_HALTED)
 		return ERROR_TARGET_NOT_HALTED;
 
-	retval = arm->read_core_reg(target, reg, armv7m_reg->num, arm->core_mode);
+	retval = arm->read_core_reg(target, reg, reg->number, arm->core_mode);
 
 	return retval;
 }
diff --git a/src/target/armv8.c b/src/target/armv8.c
index c8cfcae..e736937 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -646,7 +646,7 @@ int armv8_read_mpidr(struct armv8_common *armv8)
 	retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_MPIDR), &mpidr);
 	if (retval != ERROR_OK)
 		goto done;
-	if (mpidr & 1<<31) {
+	if (mpidr & 1U<<31) {
 		armv8->multi_processor_system = (mpidr >> 30) & 1;
 		armv8->cluster_id = (mpidr >> 8) & 0xf;
 		armv8->cpu_id = mpidr & 0x3;
@@ -1054,7 +1054,7 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command)
 			return ERROR_FAIL;
 		}
 
-		command_print(CMD_CTX, "Exception Catch: Secure: %s, Non-Secure: %s", sec, nsec);
+		command_print(CMD, "Exception Catch: Secure: %s, Non-Secure: %s", sec, nsec);
 		return ERROR_OK;
 	}
 
@@ -1079,16 +1079,16 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command)
 	return ERROR_OK;
 }
 
-int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
+int armv8_handle_cache_info_command(struct command_invocation *cmd,
 	struct armv8_cache_common *armv8_cache)
 {
 	if (armv8_cache->info == -1) {
-		command_print(cmd_ctx, "cache not yet identified");
+		command_print(cmd, "cache not yet identified");
 		return ERROR_OK;
 	}
 
 	if (armv8_cache->display_cache_info)
-		armv8_cache->display_cache_info(cmd_ctx, armv8_cache);
+		armv8_cache->display_cache_info(cmd, armv8_cache);
 	return ERROR_OK;
 }
 
diff --git a/src/target/armv8.h b/src/target/armv8.h
index af00e52..1a61145 100644
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -170,7 +170,7 @@ struct armv8_cache_common {
 	/* l2 external unified cache if some */
 	void *l2_cache;
 	int (*flush_all_data_cache)(struct target *target);
-	int (*display_cache_info)(struct command_context *cmd_ctx,
+	int (*display_cache_info)(struct command_invocation *cmd,
 			struct armv8_cache_common *armv8_cache);
 };
 
@@ -301,7 +301,7 @@ int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
 		target_addr_t *val, int meminfo);
 int armv8_mmu_translate_va(struct target *target,  target_addr_t va, target_addr_t *val);
 
-int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
+int armv8_handle_cache_info_command(struct command_invocation *cmd,
 		struct armv8_cache_common *armv8_cache);
 
 void armv8_set_cpsr(struct arm *arm, uint32_t cpsr);
diff --git a/src/target/armv8_cache.c b/src/target/armv8_cache.c
index 40965eb..41c85c9 100644
--- a/src/target/armv8_cache.c
+++ b/src/target/armv8_cache.c
@@ -188,13 +188,13 @@ done:
 	return retval;
 }
 
-static int armv8_handle_inner_cache_info_command(struct command_context *cmd_ctx,
+static int armv8_handle_inner_cache_info_command(struct command_invocation *cmd,
 	struct armv8_cache_common *armv8_cache)
 {
 	int cl;
 
 	if (armv8_cache->info == -1) {
-		command_print(cmd_ctx, "cache not yet identified");
+		command_print(cmd, "cache not yet identified");
 		return ERROR_OK;
 	}
 
@@ -202,7 +202,7 @@ static int armv8_handle_inner_cache_info_command(struct command_context *cmd_ctx
 		struct armv8_arch_cache *arch = &(armv8_cache->arch[cl]);
 
 		if (arch->ctype & 1) {
-			command_print(cmd_ctx,
+			command_print(cmd,
 				"L%d I-Cache: linelen %" PRIi32
 				", associativity %" PRIi32
 				", nsets %" PRIi32
@@ -215,7 +215,7 @@ static int armv8_handle_inner_cache_info_command(struct command_context *cmd_ctx
 		}
 
 		if (arch->ctype >= 2) {
-			command_print(cmd_ctx,
+			command_print(cmd,
 				"L%d D-Cache: linelen %" PRIi32
 				", associativity %" PRIi32
 				", nsets %" PRIi32
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 6eb6aa9..b3a8a41 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -55,6 +55,7 @@
 #include "target_type.h"
 #include "arm_opcodes.h"
 #include "arm_semihosting.h"
+#include "jtag/interface.h"
 #include "transport/transport.h"
 #include "smp.h"
 #include <helper/time_support.h>
@@ -70,6 +71,8 @@ static int cortex_a_set_hybrid_breakpoint(struct target *target,
 	struct breakpoint *breakpoint);
 static int cortex_a_unset_breakpoint(struct target *target,
 	struct breakpoint *breakpoint);
+static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask,
+	uint32_t value, uint32_t *dscr);
 static int cortex_a_mmu(struct target *target, int *enabled);
 static int cortex_a_mmu_modify(struct target *target, int enable);
 static int cortex_a_virt2phys(struct target *target,
@@ -250,21 +253,21 @@ static int cortex_a_wait_instrcmpl(struct target *target, uint32_t *dscr, bool f
 	 * Writes final value of DSCR into *dscr. Pass force to force always
 	 * reading DSCR at least once. */
 	struct armv7a_common *armv7a = target_to_armv7a(target);
-	int64_t then = timeval_ms();
-	while ((*dscr & DSCR_INSTR_COMP) == 0 || force) {
-		force = false;
-		int retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
+	int retval;
+
+	if (force) {
+		retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
 				armv7a->debug_base + CPUDBG_DSCR, dscr);
 		if (retval != ERROR_OK) {
 			LOG_ERROR("Could not read DSCR register");
 			return retval;
 		}
-		if (timeval_ms() > then + 1000) {
-			LOG_ERROR("Timeout waiting for InstrCompl=1");
-			return ERROR_FAIL;
-		}
 	}
-	return ERROR_OK;
+
+	retval = cortex_a_wait_dscr_bits(target, DSCR_INSTR_COMP, DSCR_INSTR_COMP, dscr);
+	if (retval != ERROR_OK)
+		LOG_ERROR("Error waiting for InstrCompl=1");
+	return retval;
 }
 
 /* To reduce needless round-trips, pass in a pointer to the current
@@ -293,19 +296,12 @@ static int cortex_a_exec_opcode(struct target *target,
 	if (retval != ERROR_OK)
 		return retval;
 
-	int64_t then = timeval_ms();
-	do {
-		retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
-				armv7a->debug_base + CPUDBG_DSCR, &dscr);
-		if (retval != ERROR_OK) {
-			LOG_ERROR("Could not read DSCR register");
-			return retval;
-		}
-		if (timeval_ms() > then + 1000) {
-			LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
-			return ERROR_FAIL;
-		}
-	} while ((dscr & DSCR_INSTR_COMP) == 0);	/* Wait for InstrCompl bit to be set */
+	/* Wait for InstrCompl bit to be set */
+	retval = cortex_a_wait_instrcmpl(target, &dscr, true);
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Error waiting for cortex_a_exec_opcode");
+		return retval;
+	}
 
 	if (dscr_p)
 		*dscr_p = dscr;
@@ -359,17 +355,11 @@ static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data,
 		dscr = *dscr_p;
 
 	/* Wait for DTRRXfull */
-	int64_t then = timeval_ms();
-	while ((dscr & DSCR_DTR_TX_FULL) == 0) {
-		retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
-				a->armv7a_common.debug_base + CPUDBG_DSCR,
-				&dscr);
-		if (retval != ERROR_OK)
-			return retval;
-		if (timeval_ms() > then + 1000) {
-			LOG_ERROR("Timeout waiting for read dcc");
-			return ERROR_FAIL;
-		}
+	retval = cortex_a_wait_dscr_bits(a->armv7a_common.arm.target,
+			DSCR_DTR_TX_FULL, DSCR_DTR_TX_FULL, &dscr);
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Error waiting for read dcc");
+		return retval;
 	}
 
 	retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
@@ -391,19 +381,10 @@ static int cortex_a_dpm_prepare(struct arm_dpm *dpm)
 	int retval;
 
 	/* set up invariant:  INSTR_COMP is set after ever DPM operation */
-	int64_t then = timeval_ms();
-	for (;; ) {
-		retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
-				a->armv7a_common.debug_base + CPUDBG_DSCR,
-				&dscr);
-		if (retval != ERROR_OK)
-			return retval;
-		if ((dscr & DSCR_INSTR_COMP) != 0)
-			break;
-		if (timeval_ms() > then + 1000) {
-			LOG_ERROR("Timeout waiting for dpm prepare");
-			return ERROR_FAIL;
-		}
+	retval = cortex_a_wait_instrcmpl(dpm->arm->target, &dscr, true);
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Error waiting for dpm prepare");
+		return retval;
 	}
 
 	/* this "should never happen" ... */
@@ -752,7 +733,7 @@ static int cortex_a_poll(struct target *target)
 
 static int cortex_a_halt(struct target *target)
 {
-	int retval = ERROR_OK;
+	int retval;
 	uint32_t dscr;
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 
@@ -765,18 +746,12 @@ static int cortex_a_halt(struct target *target)
 	if (retval != ERROR_OK)
 		return retval;
 
-	int64_t then = timeval_ms();
-	for (;; ) {
-		retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
-				armv7a->debug_base + CPUDBG_DSCR, &dscr);
-		if (retval != ERROR_OK)
-			return retval;
-		if ((dscr & DSCR_CORE_HALTED) != 0)
-			break;
-		if (timeval_ms() > then + 1000) {
-			LOG_ERROR("Timeout waiting for halt");
-			return ERROR_FAIL;
-		}
+	dscr = 0; /* force read of dscr */
+	retval = cortex_a_wait_dscr_bits(target, DSCR_CORE_HALTED,
+			DSCR_CORE_HALTED, &dscr);
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Error waiting for halt");
+		return retval;
 	}
 
 	target->debug_reason = DBG_REASON_DBGRQ;
@@ -915,18 +890,12 @@ static int cortex_a_internal_restart(struct target *target)
 	if (retval != ERROR_OK)
 		return retval;
 
-	int64_t then = timeval_ms();
-	for (;; ) {
-		retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
-				armv7a->debug_base + CPUDBG_DSCR, &dscr);
-		if (retval != ERROR_OK)
-			return retval;
-		if ((dscr & DSCR_CORE_RESTARTED) != 0)
-			break;
-		if (timeval_ms() > then + 1000) {
-			LOG_ERROR("Timeout waiting for resume");
-			return ERROR_FAIL;
-		}
+	dscr = 0; /* force read of dscr */
+	retval = cortex_a_wait_dscr_bits(target, DSCR_CORE_RESTARTED,
+			DSCR_CORE_RESTARTED, &dscr);
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Error waiting for resume");
+		return retval;
 	}
 
 	target->debug_reason = DBG_REASON_NOTHALTED;
@@ -1206,6 +1175,8 @@ static int cortex_a_step(struct target *target, int current, target_addr_t addre
 		retval = cortex_a_poll(target);
 		if (retval != ERROR_OK)
 			return retval;
+		if (target->state == TARGET_HALTED)
+			break;
 		if (timeval_ms() > then + 1000) {
 			LOG_ERROR("timeout waiting for target halt");
 			return ERROR_FAIL;
@@ -1689,7 +1660,7 @@ static int cortex_a_assert_reset(struct target *target)
 		 */
 		if (transport_is_swd() ||
 				(target->reset_halt && (jtag_get_reset_config() & RESET_SRST_NO_GATING)))
-			jtag_add_reset(0, 1);
+			adapter_assert_reset();
 
 	} else {
 		LOG_ERROR("%s: how to reset?", target_name(target));
@@ -1712,7 +1683,7 @@ static int cortex_a_deassert_reset(struct target *target)
 	LOG_DEBUG(" ");
 
 	/* be certain SRST is off */
-	jtag_add_reset(0, 0);
+	adapter_deassert_reset();
 
 	if (target_was_examined(target)) {
 		retval = cortex_a_poll(target);
@@ -1763,14 +1734,22 @@ static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask,
 {
 	/* Waits until the specified bit(s) of DSCR take on a specified value. */
 	struct armv7a_common *armv7a = target_to_armv7a(target);
-	int64_t then = timeval_ms();
+	int64_t then;
 	int retval;
 
-	while ((*dscr & mask) != value) {
+	if ((*dscr & mask) == value)
+		return ERROR_OK;
+
+	then = timeval_ms();
+	while (1) {
 		retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
 				armv7a->debug_base + CPUDBG_DSCR, dscr);
-		if (retval != ERROR_OK)
+		if (retval != ERROR_OK) {
+			LOG_ERROR("Could not read DSCR register");
 			return retval;
+		}
+		if ((*dscr & mask) == value)
+			break;
 		if (timeval_ms() > then + 1000) {
 			LOG_ERROR("timeout waiting for DSCR bit change");
 			return ERROR_FAIL;
@@ -2944,7 +2923,7 @@ static int cortex_a_virt2phys(struct target *target,
 	if (retval != ERROR_OK)
 		return retval;
 	return armv7a_mmu_translate_va_pa(target, (uint32_t)virt,
-						    (uint32_t *)phys, 1);
+						    phys, 1);
 }
 
 COMMAND_HANDLER(cortex_a_handle_cache_info_command)
@@ -2952,7 +2931,7 @@ COMMAND_HANDLER(cortex_a_handle_cache_info_command)
 	struct target *target = get_current_target(CMD_CTX);
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 
-	return armv7a_handle_cache_info_command(CMD_CTX,
+	return armv7a_handle_cache_info_command(CMD,
 			&armv7a->armv7a_mmu.armv7a_cache);
 }
 
@@ -2991,7 +2970,7 @@ COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command)
 	}
 
 	n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_a->isrmasking_mode);
-	command_print(CMD_CTX, "cortex_a interrupt mask %s", n->name);
+	command_print(CMD, "cortex_a interrupt mask %s", n->name);
 
 	return ERROR_OK;
 }
@@ -3017,7 +2996,7 @@ COMMAND_HANDLER(handle_cortex_a_dacrfixup_command)
 	}
 
 	n = Jim_Nvp_value2name_simple(nvp_dacrfixup_modes, cortex_a->dacrfixup_mode);
-	command_print(CMD_CTX, "cortex_a domain access control fixup %s", n->name);
+	command_print(CMD, "cortex_a domain access control fixup %s", n->name);
 
 	return ERROR_OK;
 }
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index d341d45..7f59401 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -136,6 +136,83 @@ static int cortex_m_write_debug_halt_mask(struct target *target,
 	return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
 }
 
+static int cortex_m_set_maskints(struct target *target, bool mask)
+{
+	struct cortex_m_common *cortex_m = target_to_cm(target);
+	if (!!(cortex_m->dcb_dhcsr & C_MASKINTS) != mask)
+		return cortex_m_write_debug_halt_mask(target, mask ? C_MASKINTS : 0, mask ? 0 : C_MASKINTS);
+	else
+		return ERROR_OK;
+}
+
+static int cortex_m_set_maskints_for_halt(struct target *target)
+{
+	struct cortex_m_common *cortex_m = target_to_cm(target);
+	switch (cortex_m->isrmasking_mode) {
+		case CORTEX_M_ISRMASK_AUTO:
+			/* interrupts taken at resume, whether for step or run -> no mask */
+			return cortex_m_set_maskints(target, false);
+
+		case CORTEX_M_ISRMASK_OFF:
+			/* interrupts never masked */
+			return cortex_m_set_maskints(target, false);
+
+		case CORTEX_M_ISRMASK_ON:
+			/* interrupts always masked */
+			return cortex_m_set_maskints(target, true);
+
+		case CORTEX_M_ISRMASK_STEPONLY:
+			/* interrupts masked for single step only -> mask now if MASKINTS
+			 * erratum, otherwise only mask before stepping */
+			return cortex_m_set_maskints(target, cortex_m->maskints_erratum);
+	}
+	return ERROR_OK;
+}
+
+static int cortex_m_set_maskints_for_run(struct target *target)
+{
+	switch (target_to_cm(target)->isrmasking_mode) {
+		case CORTEX_M_ISRMASK_AUTO:
+			/* interrupts taken at resume, whether for step or run -> no mask */
+			return cortex_m_set_maskints(target, false);
+
+		case CORTEX_M_ISRMASK_OFF:
+			/* interrupts never masked */
+			return cortex_m_set_maskints(target, false);
+
+		case CORTEX_M_ISRMASK_ON:
+			/* interrupts always masked */
+			return cortex_m_set_maskints(target, true);
+
+		case CORTEX_M_ISRMASK_STEPONLY:
+			/* interrupts masked for single step only -> no mask */
+			return cortex_m_set_maskints(target, false);
+	}
+	return ERROR_OK;
+}
+
+static int cortex_m_set_maskints_for_step(struct target *target)
+{
+	switch (target_to_cm(target)->isrmasking_mode) {
+		case CORTEX_M_ISRMASK_AUTO:
+			/* the auto-interrupt should already be done -> mask */
+			return cortex_m_set_maskints(target, true);
+
+		case CORTEX_M_ISRMASK_OFF:
+			/* interrupts never masked */
+			return cortex_m_set_maskints(target, false);
+
+		case CORTEX_M_ISRMASK_ON:
+			/* interrupts always masked */
+			return cortex_m_set_maskints(target, true);
+
+		case CORTEX_M_ISRMASK_STEPONLY:
+			/* interrupts masked for single step only -> mask */
+			return cortex_m_set_maskints(target, true);
+	}
+	return ERROR_OK;
+}
+
 static int cortex_m_clear_halt(struct target *target)
 {
 	struct cortex_m_common *cortex_m = target_to_cm(target);
@@ -237,11 +314,8 @@ static int cortex_m_endreset_event(struct target *target)
 			return retval;
 	}
 
-	/* Restore proper interrupt masking setting. */
-	if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
-		cortex_m_write_debug_halt_mask(target, C_MASKINTS, 0);
-	else
-		cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
+	/* Restore proper interrupt masking setting for running CPU. */
+	cortex_m_set_maskints_for_run(target);
 
 	/* Enable features controlled by ITM and DWT blocks, and catch only
 	 * the vectors we were told to pay attention to.
@@ -318,7 +392,9 @@ static int cortex_m_examine_debug_reason(struct target *target)
 			target->debug_reason = DBG_REASON_WATCHPOINT;
 		else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
 			target->debug_reason = DBG_REASON_BREAKPOINT;
-		else	/* EXTERNAL, HALTED */
+		else if (cortex_m->nvic_dfsr & DFSR_EXTERNAL)
+			target->debug_reason = DBG_REASON_DBGRQ;
+		else	/* HALTED */
 			target->debug_reason = DBG_REASON_UNDEFINED;
 	}
 
@@ -405,6 +481,10 @@ static int cortex_m_debug_entry(struct target *target)
 
 	LOG_DEBUG(" ");
 
+	/* Do this really early to minimize the window where the MASKINTS erratum
+	 * can pile up pending interrupts. */
+	cortex_m_set_maskints_for_halt(target);
+
 	cortex_m_clear_halt(target);
 	retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
 	if (retval != ERROR_OK)
@@ -614,6 +694,10 @@ static int cortex_m_halt(struct target *target)
 	/* Write to Debug Halting Control and Status Register */
 	cortex_m_write_debug_halt_mask(target, C_HALT, 0);
 
+	/* Do this really early to minimize the window where the MASKINTS erratum
+	 * can pile up pending interrupts. */
+	cortex_m_set_maskints_for_halt(target);
+
 	target->debug_reason = DBG_REASON_DBGRQ;
 
 	return ERROR_OK;
@@ -632,6 +716,11 @@ static int cortex_m_soft_reset_halt(struct target *target)
 	 * core, not the peripherals */
 	LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
 
+	/* Set C_DEBUGEN */
+	retval = cortex_m_write_debug_halt_mask(target, 0, C_STEP | C_MASKINTS);
+	if (retval != ERROR_OK)
+		return retval;
+
 	/* Enter debug state on reset; restore DEMCR in endreset_event() */
 	retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
 			TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
@@ -767,6 +856,7 @@ static int cortex_m_resume(struct target *target, int current,
 	}
 
 	/* Restart core */
+	cortex_m_set_maskints_for_run(target);
 	cortex_m_write_debug_halt_mask(target, 0, C_HALT);
 
 	target->debug_reason = DBG_REASON_NOTHALTED;
@@ -829,10 +919,12 @@ static int cortex_m_step(struct target *target, int current,
 	 * a normal step, otherwise we have to manually step over the bkpt
 	 * instruction - as such simulate a step */
 	if (bkpt_inst_found == false) {
-		/* Automatic ISR masking mode off: Just step over the next instruction */
-		if ((cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO))
+		if ((cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO)) {
+			/* Automatic ISR masking mode off: Just step over the next
+			 * instruction, with interrupts on or off as appropriate. */
+			cortex_m_set_maskints_for_step(target);
 			cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
-		else {
+		} else {
 			/* Process interrupts during stepping in a way they don't interfere
 			 * debugging.
 			 *
@@ -871,8 +963,9 @@ static int cortex_m_step(struct target *target, int current,
 				LOG_DEBUG("Stepping over next instruction with interrupts disabled");
 				cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
 				cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
-				/* Re-enable interrupts */
-				cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
+				/* Re-enable interrupts if appropriate */
+				cortex_m_write_debug_halt_mask(target, C_HALT, 0);
+				cortex_m_set_maskints_for_halt(target);
 			}
 			else {
 
@@ -891,12 +984,17 @@ static int cortex_m_step(struct target *target, int current,
 				bool tmp_bp_set = (retval == ERROR_OK);
 
 				/* No more breakpoints left, just do a step */
-				if (!tmp_bp_set)
+				if (!tmp_bp_set) {
+					cortex_m_set_maskints_for_step(target);
 					cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
-				else {
+					/* Re-enable interrupts if appropriate */
+					cortex_m_write_debug_halt_mask(target, C_HALT, 0);
+					cortex_m_set_maskints_for_halt(target);
+				} else {
 					/* Start the core */
 					LOG_DEBUG("Starting core to serve pending interrupts");
 					int64_t t_start = timeval_ms();
+					cortex_m_set_maskints_for_run(target);
 					cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
 
 					/* Wait for pending handlers to complete or timeout */
@@ -924,12 +1022,14 @@ static int cortex_m_step(struct target *target, int current,
 							"leaving target running");
 					} else {
 						/* Step over next instruction with interrupts disabled */
+						cortex_m_set_maskints_for_step(target);
 						cortex_m_write_debug_halt_mask(target,
 							C_HALT | C_MASKINTS,
 							0);
 						cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
-						/* Re-enable interrupts */
-						cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
+						/* Re-enable interrupts if appropriate */
+						cortex_m_write_debug_halt_mask(target, C_HALT, 0);
+						cortex_m_set_maskints_for_halt(target);
 					}
 				}
 			}
@@ -1031,8 +1131,7 @@ static int cortex_m_assert_reset(struct target *target)
 
 	if (!target->reset_halt) {
 		/* Set/Clear C_MASKINTS in a separate operation */
-		if (cortex_m->dcb_dhcsr & C_MASKINTS)
-			cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
+		cortex_m_set_maskints_for_run(target);
 
 		/* clear any debug flags before resuming */
 		cortex_m_clear_halt(target);
@@ -1104,7 +1203,7 @@ static int cortex_m_assert_reset(struct target *target)
 	}
 
 	target->state = TARGET_RESET;
-	jtag_add_sleep(50000);
+	jtag_sleep(50000);
 
 	register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
 
@@ -1297,18 +1396,8 @@ int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpo
 int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
 {
 	int dwt_num = 0;
-	uint32_t mask, temp;
 	struct cortex_m_common *cortex_m = target_to_cm(target);
 
-	/* watchpoint params were validated earlier */
-	mask = 0;
-	temp = watchpoint->length;
-	while (temp) {
-		temp >>= 1;
-		mask++;
-	}
-	mask--;
-
 	/* REVISIT Don't fully trust these "not used" records ... users
 	 * may set up breakpoints by hand, e.g. dual-address data value
 	 * watchpoint using comparator #1; comparator #0 matching cycle
@@ -1331,11 +1420,22 @@ int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint
 	target_write_u32(target, comparator->dwt_comparator_address + 0,
 		comparator->comp);
 
-	comparator->mask = mask;
-	target_write_u32(target, comparator->dwt_comparator_address + 4,
-		comparator->mask);
+	if ((cortex_m->dwt_devarch & 0x1FFFFF) != DWT_DEVARCH_ARMV8M) {
+		uint32_t mask = 0, temp;
+
+		/* watchpoint params were validated earlier */
+		temp = watchpoint->length;
+		while (temp) {
+			temp >>= 1;
+			mask++;
+		}
+		mask--;
+
+		comparator->mask = mask;
+		target_write_u32(target, comparator->dwt_comparator_address + 4,
+			comparator->mask);
 
-	switch (watchpoint->rw) {
+		switch (watchpoint->rw) {
 		case WPT_READ:
 			comparator->function = 5;
 			break;
@@ -1345,7 +1445,26 @@ int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint
 		case WPT_ACCESS:
 			comparator->function = 7;
 			break;
+		}
+	} else {
+		uint32_t data_size = watchpoint->length >> 1;
+		comparator->mask = (watchpoint->length >> 1) | 1;
+
+		switch (watchpoint->rw) {
+		case WPT_ACCESS:
+			comparator->function = 4;
+			break;
+		case WPT_WRITE:
+			comparator->function = 5;
+			break;
+		case WPT_READ:
+			comparator->function = 6;
+			break;
+		}
+		comparator->function = comparator->function | (1 << 4) |
+				(data_size << 10);
 	}
+
 	target_write_u32(target, comparator->dwt_comparator_address + 8,
 		comparator->function);
 
@@ -1888,6 +2007,9 @@ void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
 		return;
 	}
 
+	target_read_u32(target, DWT_DEVARCH, &cm->dwt_devarch);
+	LOG_DEBUG("DWT_DEVARCH: 0x%" PRIx32, cm->dwt_devarch);
+
 	cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
 	cm->dwt_comp_available = cm->dwt_num_comp;
 	cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
@@ -1976,6 +2098,15 @@ static void cortex_m_dwt_free(struct target *target)
 #define MVFR1_DEFAULT_M7_SP 0x11000011
 #define MVFR1_DEFAULT_M7_DP 0x12000011
 
+static int cortex_m_find_mem_ap(struct adiv5_dap *swjdp,
+		struct adiv5_ap **debug_ap)
+{
+	if (dap_find_ap(swjdp, AP_TYPE_AHB3_AP, debug_ap) == ERROR_OK)
+		return ERROR_OK;
+
+	return dap_find_ap(swjdp, AP_TYPE_AHB5_AP, debug_ap);
+}
+
 int cortex_m_examine(struct target *target)
 {
 	int retval;
@@ -1990,7 +2121,7 @@ int cortex_m_examine(struct target *target)
 	if (!armv7m->stlink) {
 		if (cortex_m->apsel == DP_APSEL_INVALID) {
 			/* Search for the MEM-AP */
-			retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv7m->debug_ap);
+			retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
 			if (retval != ERROR_OK) {
 				LOG_ERROR("Could not find MEM-AP to control the core");
 				return retval;
@@ -2018,14 +2149,31 @@ int cortex_m_examine(struct target *target)
 		/* Get CPU Type */
 		i = (cpuid >> 4) & 0xf;
 
+		switch (cpuid & ARM_CPUID_PARTNO_MASK) {
+			case CORTEX_M23_PARTNO:
+				i = 23;
+				break;
+
+			case CORTEX_M33_PARTNO:
+				i = 33;
+				break;
+
+			default:
+				break;
+		}
+
+
 		LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
 				i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
+		cortex_m->maskints_erratum = false;
 		if (i == 7) {
 			uint8_t rev, patch;
 			rev = (cpuid >> 20) & 0xf;
 			patch = (cpuid >> 0) & 0xf;
-			if ((rev == 0) && (patch < 2))
-				LOG_WARNING("Silicon bug: single stepping will enter pending exception handler!");
+			if ((rev == 0) && (patch < 2)) {
+				LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
+				cortex_m->maskints_erratum = true;
+			}
 		}
 		LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
 
@@ -2041,7 +2189,7 @@ int cortex_m_examine(struct target *target)
 				LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
 				armv7m->fp_feature = FPv4_SP;
 			}
-		} else if (i == 7) {
+		} else if (i == 7 || i == 33) {
 			target_read_u32(target, MVFR0, &mvfr0);
 			target_read_u32(target, MVFR1, &mvfr1);
 
@@ -2271,11 +2419,11 @@ static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
 
 /*--------------------------------------------------------------------------*/
 
-static int cortex_m_verify_pointer(struct command_context *cmd_ctx,
+static int cortex_m_verify_pointer(struct command_invocation *cmd,
 	struct cortex_m_common *cm)
 {
 	if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
-		command_print(cmd_ctx, "target is not a Cortex-M");
+		command_print(cmd, "target is not a Cortex-M");
 		return ERROR_TARGET_INVALID;
 	}
 	return ERROR_OK;
@@ -2309,7 +2457,7 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
 		{ "reset",      VC_CORERESET, },
 	};
 
-	retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
+	retval = cortex_m_verify_pointer(CMD, cortex_m);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -2364,7 +2512,7 @@ write:
 	}
 
 	for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
-		command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
+		command_print(CMD, "%9s: %s", vec_ids[i].name,
 			(demcr & vec_ids[i].mask) ? "catch" : "ignore");
 	}
 
@@ -2381,17 +2529,18 @@ COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
 		{ .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
 		{ .name = "off", .value = CORTEX_M_ISRMASK_OFF },
 		{ .name = "on", .value = CORTEX_M_ISRMASK_ON },
+		{ .name = "steponly", .value = CORTEX_M_ISRMASK_STEPONLY },
 		{ .name = NULL, .value = -1 },
 	};
 	const Jim_Nvp *n;
 
 
-	retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
+	retval = cortex_m_verify_pointer(CMD, cortex_m);
 	if (retval != ERROR_OK)
 		return retval;
 
 	if (target->state != TARGET_HALTED) {
-		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+		command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
 		return ERROR_OK;
 	}
 
@@ -2400,16 +2549,11 @@ COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
 		if (n->name == NULL)
 			return ERROR_COMMAND_SYNTAX_ERROR;
 		cortex_m->isrmasking_mode = n->value;
-
-
-		if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
-			cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
-		else
-			cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
+		cortex_m_set_maskints_for_halt(target);
 	}
 
 	n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
-	command_print(CMD_CTX, "cortex_m interrupt mask %s", n->name);
+	command_print(CMD, "cortex_m interrupt mask %s", n->name);
 
 	return ERROR_OK;
 }
@@ -2421,7 +2565,7 @@ COMMAND_HANDLER(handle_cortex_m_reset_config_command)
 	int retval;
 	char *reset_config;
 
-	retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
+	retval = cortex_m_verify_pointer(CMD, cortex_m);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -2454,7 +2598,7 @@ COMMAND_HANDLER(handle_cortex_m_reset_config_command)
 			break;
 	}
 
-	command_print(CMD_CTX, "cortex_m reset_config %s", reset_config);
+	command_print(CMD, "cortex_m reset_config %s", reset_config);
 
 	return ERROR_OK;
 }
@@ -2465,7 +2609,7 @@ static const struct command_registration cortex_m_exec_command_handlers[] = {
 		.handler = handle_cortex_m_mask_interrupts_command,
 		.mode = COMMAND_EXEC,
 		.help = "mask cortex_m interrupts",
-		.usage = "['auto'|'on'|'off']",
+		.usage = "['auto'|'on'|'off'|'steponly']",
 	},
 	{
 		.name = "vector_catch",
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 4b20746..54d7a02 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -38,6 +38,12 @@
 #define ITM_LAR_KEY	0xC5ACCE55
 
 #define CPUID		0xE000ED00
+
+#define ARM_CPUID_PARTNO_MASK	0xFFF0
+
+#define CORTEX_M23_PARTNO	0xD200
+#define CORTEX_M33_PARTNO	0xD210
+
 /* Debug Control Block */
 #define DCB_DHCSR	0xE000EDF0
 #define DCB_DCRSR	0xE000EDF4
@@ -52,6 +58,9 @@
 #define DWT_COMP0	0xE0001020
 #define DWT_MASK0	0xE0001024
 #define DWT_FUNCTION0	0xE0001028
+#define DWT_DEVARCH		0xE0001FBC
+
+#define DWT_DEVARCH_ARMV8M	0x101A02
 
 #define FP_CTRL		0xE0002000
 #define FP_REMAP	0xE0002004
@@ -127,6 +136,7 @@
 #define DFSR_BKPT			2
 #define DFSR_DWTTRAP		4
 #define DFSR_VCATCH			8
+#define DFSR_EXTERNAL		16
 
 #define FPCR_CODE 0
 #define FPCR_LITERAL 1
@@ -159,6 +169,7 @@ enum cortex_m_isrmasking_mode {
 	CORTEX_M_ISRMASK_AUTO,
 	CORTEX_M_ISRMASK_OFF,
 	CORTEX_M_ISRMASK_ON,
+	CORTEX_M_ISRMASK_STEPONLY,
 };
 
 struct cortex_m_common {
@@ -179,6 +190,7 @@ struct cortex_m_common {
 	/* Data Watchpoint and Trace (DWT) */
 	int dwt_num_comp;
 	int dwt_comp_available;
+	uint32_t dwt_devarch;
 	struct cortex_m_dwt_comparator *dwt_comparator_list;
 	struct reg_cache *dwt_cache;
 
@@ -190,6 +202,10 @@ struct cortex_m_common {
 	struct armv7m_common armv7m;
 
 	int apsel;
+
+	/* Whether this target has the erratum that makes C_MASKINTS not apply to
+	 * already pending interrupts */
+	bool maskints_erratum;
 };
 
 static inline struct cortex_m_common *
diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c
index 5f13384..6a5c868 100644
--- a/src/target/dsp563xx.c
+++ b/src/target/dsp563xx.c
@@ -475,6 +475,7 @@ static void dsp563xx_build_reg_cache(struct target *target)
 		reg_list[i].value = calloc(1, 4);
 		reg_list[i].dirty = false;
 		reg_list[i].valid = false;
+		reg_list[i].exist = true;
 		reg_list[i].type = &dsp563xx_reg_type;
 		reg_list[i].arch_info = &arch_info[i];
 	}
@@ -1875,67 +1876,6 @@ static int dsp563xx_remove_watchpoint(struct target *target, struct watchpoint *
 	return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 }
 
-static void handle_md_output(struct command_context *cmd_ctx,
-	struct target *target,
-	uint32_t address,
-	unsigned size,
-	unsigned count,
-	const uint8_t *buffer)
-{
-	const unsigned line_bytecnt = 32;
-	unsigned line_modulo = line_bytecnt / size;
-
-	char output[line_bytecnt * 4 + 1];
-	unsigned output_len = 0;
-
-	const char *value_fmt;
-	switch (size) {
-		case 4:
-			value_fmt = "%8.8x ";
-			break;
-		case 2:
-			value_fmt = "%4.4x ";
-			break;
-		case 1:
-			value_fmt = "%2.2x ";
-			break;
-		default:
-			/* "can't happen", caller checked */
-			LOG_ERROR("invalid memory read size: %u", size);
-			return;
-	}
-
-	for (unsigned i = 0; i < count; i++) {
-		if (i % line_modulo == 0)
-			output_len += snprintf(output + output_len,
-					sizeof(output) - output_len,
-					"0x%8.8x: ",
-					(unsigned) (address + i));
-
-		uint32_t value = 0;
-		const uint8_t *value_ptr = buffer + i * size;
-		switch (size) {
-			case 4:
-				value = target_buffer_get_u32(target, value_ptr);
-				break;
-			case 2:
-				value = target_buffer_get_u16(target, value_ptr);
-				break;
-			case 1:
-				value = *value_ptr;
-		}
-		output_len += snprintf(output + output_len,
-				sizeof(output) - output_len,
-				value_fmt,
-				value);
-
-		if ((i % line_modulo == line_modulo - 1) || (i == count - 1)) {
-			command_print(cmd_ctx, "%s", output);
-			output_len = 0;
-		}
-	}
-}
-
 static int dsp563xx_add_custom_watchpoint(struct target *target, uint32_t address, uint32_t memType,
 		enum watchpoint_rw rw, enum watchpoint_condition cond)
 {
@@ -2208,7 +2148,7 @@ COMMAND_HANDLER(dsp563xx_mem_command)
 		err = dsp563xx_read_memory(target, mem_type, address, sizeof(uint32_t),
 				count, buffer);
 		if (err == ERROR_OK)
-			handle_md_output(CMD_CTX, target, address, sizeof(uint32_t), count, buffer);
+			target_handle_md_output(CMD, target, address, sizeof(uint32_t), count, buffer);
 
 	} else {
 		b = buffer;
diff --git a/src/target/esirisc.c b/src/target/esirisc.c
index 3d2954f..c928445 100644
--- a/src/target/esirisc.c
+++ b/src/target/esirisc.c
@@ -1680,7 +1680,7 @@ COMMAND_HANDLER(handle_esirisc_cache_arch_command)
 		}
 	}
 
-	command_print(CMD_CTX, "esirisc cache_arch %s", esirisc_cache_arch_name(esirisc));
+	command_print(CMD, "esirisc cache_arch %s", esirisc_cache_arch_name(esirisc));
 
 	return ERROR_OK;
 }
@@ -1698,7 +1698,7 @@ COMMAND_HANDLER(handle_esirisc_flush_caches_command)
 
 	retval = esirisc_flush_caches(target);
 
-	command_print(CMD_CTX, "cache flush %s",
+	command_print(CMD, "cache flush %s",
 			(retval == ERROR_OK) ? "successful" : "failed");
 
 	return retval;
@@ -1748,7 +1748,7 @@ COMMAND_HANDLER(handle_esirisc_hwdc_command)
 	}
 
 	for (size_t i = 0; i < ARRAY_SIZE(esirisc_hwdc_masks); ++i)
-		command_print(CMD_CTX, "%9s: %s", esirisc_hwdc_masks[i].name,
+		command_print(CMD, "%9s: %s", esirisc_hwdc_masks[i].name,
 				(esirisc->hwdc_save & esirisc_hwdc_masks[i].mask) ? "enabled" : "disabled");
 
 	return ERROR_OK;
diff --git a/src/target/esirisc_trace.c b/src/target/esirisc_trace.c
index 4e0a155..6a7d5a2 100644
--- a/src/target/esirisc_trace.c
+++ b/src/target/esirisc_trace.c
@@ -385,9 +385,9 @@ static int esirisc_trace_read_buffer(struct target *target, uint8_t *buffer)
 			buffer_cur - trace_info->buffer_start, buffer);
 }
 
-static int esirisc_trace_analyze_full(struct command_context *cmd_ctx, uint8_t *buffer, uint32_t size)
+static int esirisc_trace_analyze_full(struct command_invocation *cmd, uint8_t *buffer, uint32_t size)
 {
-	struct target *target = get_current_target(cmd_ctx);
+	struct target *target = get_current_target(cmd->ctx);
 	const uint32_t num_bits = size * 8;
 	int retval;
 
@@ -403,7 +403,7 @@ static int esirisc_trace_analyze_full(struct command_context *cmd_ctx, uint8_t *
 			case ESIRISC_TRACE_ID_EXECUTE:
 			case ESIRISC_TRACE_ID_STALL:
 			case ESIRISC_TRACE_ID_BRANCH:
-				command_print(cmd_ctx, "%s", esirisc_trace_id_strings[id]);
+				command_print(cmd, "%s", esirisc_trace_id_strings[id]);
 				break;
 
 			case ESIRISC_TRACE_ID_EXTENDED: {
@@ -417,7 +417,7 @@ static int esirisc_trace_analyze_full(struct command_context *cmd_ctx, uint8_t *
 					case ESIRISC_TRACE_EXT_ID_STOP:
 					case ESIRISC_TRACE_EXT_ID_WAIT:
 					case ESIRISC_TRACE_EXT_ID_MULTICYCLE:
-						command_print(cmd_ctx, "%s", esirisc_trace_ext_id_strings[ext_id]);
+						command_print(cmd, "%s", esirisc_trace_ext_id_strings[ext_id]);
 						break;
 
 					case ESIRISC_TRACE_EXT_ID_ERET:
@@ -430,11 +430,11 @@ static int esirisc_trace_analyze_full(struct command_context *cmd_ctx, uint8_t *
 						if (retval != ERROR_OK)
 							goto fail;
 
-						command_print(cmd_ctx, "%s PC: 0x%" PRIx32,
+						command_print(cmd, "%s PC: 0x%" PRIx32,
 								esirisc_trace_ext_id_strings[ext_id], pc);
 
 						if (ext_id == ESIRISC_TRACE_EXT_ID_END_PC) {
-							command_print(cmd_ctx, "--- end of trace ---");
+							command_print(cmd, "--- end of trace ---");
 							return ERROR_OK;
 						}
 						break;
@@ -450,7 +450,7 @@ static int esirisc_trace_analyze_full(struct command_context *cmd_ctx, uint8_t *
 						if (retval != ERROR_OK)
 							goto fail;
 
-						command_print(cmd_ctx, "%s EID: 0x%" PRIx32 ", EPC: 0x%" PRIx32,
+						command_print(cmd, "%s EID: 0x%" PRIx32 ", EPC: 0x%" PRIx32,
 								esirisc_trace_ext_id_strings[ext_id], eid, epc);
 						break;
 					}
@@ -461,34 +461,34 @@ static int esirisc_trace_analyze_full(struct command_context *cmd_ctx, uint8_t *
 						if (retval != ERROR_OK)
 							goto fail;
 
-						command_print(cmd_ctx, "repeats %" PRId32 " %s", count,
+						command_print(cmd, "repeats %" PRId32 " %s", count,
 								(count == 1) ? "time" : "times");
 						break;
 					}
 					case ESIRISC_TRACE_EXT_ID_END:
-						command_print(cmd_ctx, "--- end of trace ---");
+						command_print(cmd, "--- end of trace ---");
 						return ERROR_OK;
 
 					default:
-						command_print(cmd_ctx, "invalid extended trace ID: %" PRId32, ext_id);
+						command_print(cmd, "invalid extended trace ID: %" PRId32, ext_id);
 						return ERROR_FAIL;
 				}
 				break;
 			}
 			default:
-				command_print(cmd_ctx, "invalid trace ID: %" PRId32, id);
+				command_print(cmd, "invalid trace ID: %" PRId32, id);
 				return ERROR_FAIL;
 		}
 	}
 
 fail:
-	command_print(cmd_ctx, "trace buffer too small");
+	command_print(cmd, "trace buffer too small");
 	return ERROR_BUF_TOO_SMALL;
 }
 
-static int esirisc_trace_analyze_simple(struct command_context *cmd_ctx, uint8_t *buffer, uint32_t size)
+static int esirisc_trace_analyze_simple(struct command_invocation *cmd, uint8_t *buffer, uint32_t size)
 {
-	struct target *target = get_current_target(cmd_ctx);
+	struct target *target = get_current_target(cmd->ctx);
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct esirisc_trace *trace_info = &esirisc->trace_info;
 	const uint32_t end_of_trace = BIT_MASK(trace_info->pc_bits) << 1;
@@ -504,45 +504,45 @@ static int esirisc_trace_analyze_simple(struct command_context *cmd_ctx, uint8_t
 			break;
 
 		if (pc == end_of_trace) {
-			command_print(cmd_ctx, "--- end of trace ---");
+			command_print(cmd, "--- end of trace ---");
 			return ERROR_OK;
 		}
 
-		command_print(cmd_ctx, "PC: 0x%" PRIx32, pc);
+		command_print(cmd, "PC: 0x%" PRIx32, pc);
 	}
 
-	command_print(cmd_ctx, "trace buffer too small");
+	command_print(cmd, "trace buffer too small");
 	return ERROR_BUF_TOO_SMALL;
 }
 
-static int esirisc_trace_analyze(struct command_context *cmd_ctx, uint8_t *buffer, uint32_t size)
+static int esirisc_trace_analyze(struct command_invocation *cmd, uint8_t *buffer, uint32_t size)
 {
-	struct target *target = get_current_target(cmd_ctx);
+	struct target *target = get_current_target(cmd->ctx);
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct esirisc_trace *trace_info = &esirisc->trace_info;
 
 	switch (trace_info->format) {
 		case ESIRISC_TRACE_FORMAT_FULL:
-			command_print(cmd_ctx, "--- full pipeline ---");
-			return esirisc_trace_analyze_full(cmd_ctx, buffer, size);
+			command_print(cmd, "--- full pipeline ---");
+			return esirisc_trace_analyze_full(cmd, buffer, size);
 
 		case ESIRISC_TRACE_FORMAT_BRANCH:
-			command_print(cmd_ctx, "--- branches taken ---");
-			return esirisc_trace_analyze_full(cmd_ctx, buffer, size);
+			command_print(cmd, "--- branches taken ---");
+			return esirisc_trace_analyze_full(cmd, buffer, size);
 
 		case ESIRISC_TRACE_FORMAT_ICACHE:
-			command_print(cmd_ctx, "--- icache misses ---");
-			return esirisc_trace_analyze_simple(cmd_ctx, buffer, size);
+			command_print(cmd, "--- icache misses ---");
+			return esirisc_trace_analyze_simple(cmd, buffer, size);
 
 		default:
-			command_print(cmd_ctx, "invalid trace format: %i", trace_info->format);
+			command_print(cmd, "invalid trace format: %i", trace_info->format);
 			return ERROR_FAIL;
 	}
 }
 
-static int esirisc_trace_analyze_buffer(struct command_context *cmd_ctx)
+static int esirisc_trace_analyze_buffer(struct command_invocation *cmd)
 {
-	struct target *target = get_current_target(cmd_ctx);
+	struct target *target = get_current_target(cmd->ctx);
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct esirisc_trace *trace_info = &esirisc->trace_info;
 	uint8_t *buffer;
@@ -552,7 +552,7 @@ static int esirisc_trace_analyze_buffer(struct command_context *cmd_ctx)
 	size = esirisc_trace_buffer_size(trace_info);
 	buffer = calloc(1, size);
 	if (buffer == NULL) {
-		command_print(cmd_ctx, "out of memory");
+		command_print(cmd, "out of memory");
 		return ERROR_FAIL;
 	}
 
@@ -560,7 +560,7 @@ static int esirisc_trace_analyze_buffer(struct command_context *cmd_ctx)
 	if (retval != ERROR_OK)
 		goto done;
 
-	retval = esirisc_trace_analyze(cmd_ctx, buffer, size);
+	retval = esirisc_trace_analyze(cmd, buffer, size);
 
 done:
 	free(buffer);
@@ -568,16 +568,16 @@ done:
 	return retval;
 }
 
-static int esirisc_trace_analyze_memory(struct command_context *cmd_ctx,
+static int esirisc_trace_analyze_memory(struct command_invocation *cmd,
 		target_addr_t address, uint32_t size)
 {
-	struct target *target = get_current_target(cmd_ctx);
+	struct target *target = get_current_target(cmd->ctx);
 	uint8_t *buffer;
 	int retval;
 
 	buffer = calloc(1, size);
 	if (buffer == NULL) {
-		command_print(cmd_ctx, "out of memory");
+		command_print(cmd, "out of memory");
 		return ERROR_FAIL;
 	}
 
@@ -585,7 +585,7 @@ static int esirisc_trace_analyze_memory(struct command_context *cmd_ctx,
 	if (retval != ERROR_OK)
 		goto done;
 
-	retval = esirisc_trace_analyze(cmd_ctx, buffer, size);
+	retval = esirisc_trace_analyze(cmd, buffer, size);
 
 done:
 	free(buffer);
@@ -593,7 +593,7 @@ done:
 	return retval;
 }
 
-static int esirisc_trace_dump(struct command_context *cmd_ctx, const char *filename,
+static int esirisc_trace_dump(struct command_invocation *cmd, const char *filename,
 		uint8_t *buffer, uint32_t size)
 {
 	struct fileio *fileio;
@@ -602,24 +602,24 @@ static int esirisc_trace_dump(struct command_context *cmd_ctx, const char *filen
 
 	retval = fileio_open(&fileio, filename, FILEIO_WRITE, FILEIO_BINARY);
 	if (retval != ERROR_OK) {
-		command_print(cmd_ctx, "could not open dump file: %s", filename);
+		command_print(cmd, "could not open dump file: %s", filename);
 		return retval;
 	}
 
 	retval = fileio_write(fileio, size, buffer, &size_written);
 	if (retval == ERROR_OK)
-		command_print(cmd_ctx, "trace data dumped to: %s", filename);
+		command_print(cmd, "trace data dumped to: %s", filename);
 	else
-		command_print(cmd_ctx, "could not write dump file: %s", filename);
+		command_print(cmd, "could not write dump file: %s", filename);
 
 	fileio_close(fileio);
 
 	return retval;
 }
 
-static int esirisc_trace_dump_buffer(struct command_context *cmd_ctx, const char *filename)
+static int esirisc_trace_dump_buffer(struct command_invocation *cmd, const char *filename)
 {
-	struct target *target = get_current_target(cmd_ctx);
+	struct target *target = get_current_target(cmd->ctx);
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct esirisc_trace *trace_info = &esirisc->trace_info;
 	uint8_t *buffer;
@@ -629,7 +629,7 @@ static int esirisc_trace_dump_buffer(struct command_context *cmd_ctx, const char
 	size = esirisc_trace_buffer_size(trace_info);
 	buffer = calloc(1, size);
 	if (buffer == NULL) {
-		command_print(cmd_ctx, "out of memory");
+		command_print(cmd, "out of memory");
 		return ERROR_FAIL;
 	}
 
@@ -637,7 +637,7 @@ static int esirisc_trace_dump_buffer(struct command_context *cmd_ctx, const char
 	if (retval != ERROR_OK)
 		goto done;
 
-	retval = esirisc_trace_dump(cmd_ctx, filename, buffer, size);
+	retval = esirisc_trace_dump(cmd, filename, buffer, size);
 
 done:
 	free(buffer);
@@ -645,16 +645,16 @@ done:
 	return retval;
 }
 
-static int esirisc_trace_dump_memory(struct command_context *cmd_ctx, const char *filename,
+static int esirisc_trace_dump_memory(struct command_invocation *cmd, const char *filename,
 		target_addr_t address, uint32_t size)
 {
-	struct target *target = get_current_target(cmd_ctx);
+	struct target *target = get_current_target(cmd->ctx);
 	uint8_t *buffer;
 	int retval;
 
 	buffer = calloc(1, size);
 	if (buffer == NULL) {
-		command_print(cmd_ctx, "out of memory");
+		command_print(cmd, "out of memory");
 		return ERROR_FAIL;
 	}
 
@@ -662,7 +662,7 @@ static int esirisc_trace_dump_memory(struct command_context *cmd_ctx, const char
 	if (retval != ERROR_OK)
 		goto done;
 
-	retval = esirisc_trace_dump(cmd_ctx, filename, buffer, size);
+	retval = esirisc_trace_dump(cmd, filename, buffer, size);
 
 done:
 	free(buffer);
@@ -676,13 +676,13 @@ COMMAND_HANDLER(handle_esirisc_trace_init_command)
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 
 	if (!esirisc->has_trace) {
-		command_print(CMD_CTX, "target does not support trace");
+		command_print(CMD, "target does not support trace");
 		return ERROR_FAIL;
 	}
 
 	int retval = esirisc_trace_init(target);
 	if (retval == ERROR_OK)
-		command_print(CMD_CTX, "trace initialized");
+		command_print(CMD, "trace initialized");
 
 	return retval;
 }
@@ -694,42 +694,42 @@ COMMAND_HANDLER(handle_esirisc_trace_info_command)
 	struct esirisc_trace *trace_info = &esirisc->trace_info;
 
 	if (!esirisc->has_trace) {
-		command_print(CMD_CTX, "target does not support trace");
+		command_print(CMD, "target does not support trace");
 		return ERROR_FAIL;
 	}
 
 	if (esirisc_trace_is_fifo(trace_info))
-		command_print(CMD_CTX, "trace FIFO address: 0x%" TARGET_PRIxADDR,
+		command_print(CMD, "trace FIFO address: 0x%" TARGET_PRIxADDR,
 				trace_info->buffer_start);
 	else {
-		command_print(CMD_CTX, "trace buffer start: 0x%" TARGET_PRIxADDR,
+		command_print(CMD, "trace buffer start: 0x%" TARGET_PRIxADDR,
 				trace_info->buffer_start);
-		command_print(CMD_CTX, "trace buffer end: 0x%" TARGET_PRIxADDR,
+		command_print(CMD, "trace buffer end: 0x%" TARGET_PRIxADDR,
 				trace_info->buffer_end);
-		command_print(CMD_CTX, "trace buffer will %swrap",
+		command_print(CMD, "trace buffer will %swrap",
 				trace_info->buffer_wrap ? "" : "not ");
 	}
 
-	command_print(CMD_CTX, "flow control: %s",
+	command_print(CMD, "flow control: %s",
 			trace_info->flow_control ? "enabled" : "disabled");
 
-	command_print(CMD_CTX, "trace format: %s",
+	command_print(CMD, "trace format: %s",
 			esirisc_trace_format_strings[trace_info->format]);
-	command_print(CMD_CTX, "number of PC bits: %i", trace_info->pc_bits);
+	command_print(CMD, "number of PC bits: %i", trace_info->pc_bits);
 
-	command_print(CMD_CTX, "start trigger: %s",
+	command_print(CMD, "start trigger: %s",
 			esirisc_trace_trigger_strings[trace_info->start_trigger]);
-	command_print(CMD_CTX, "start data: 0x%" PRIx32, trace_info->start_data);
-	command_print(CMD_CTX, "start mask: 0x%" PRIx32, trace_info->start_mask);
+	command_print(CMD, "start data: 0x%" PRIx32, trace_info->start_data);
+	command_print(CMD, "start mask: 0x%" PRIx32, trace_info->start_mask);
 
-	command_print(CMD_CTX, "stop trigger: %s",
+	command_print(CMD, "stop trigger: %s",
 			esirisc_trace_trigger_strings[trace_info->stop_trigger]);
-	command_print(CMD_CTX, "stop data: 0x%" PRIx32, trace_info->stop_data);
-	command_print(CMD_CTX, "stop mask: 0x%" PRIx32, trace_info->stop_mask);
+	command_print(CMD, "stop data: 0x%" PRIx32, trace_info->stop_data);
+	command_print(CMD, "stop mask: 0x%" PRIx32, trace_info->stop_mask);
 
-	command_print(CMD_CTX, "trigger delay: %s",
+	command_print(CMD, "trigger delay: %s",
 			esirisc_trace_delay_strings[trace_info->delay]);
-	command_print(CMD_CTX, "trigger delay cycles: %i", trace_info->delay_cycles);
+	command_print(CMD, "trigger delay cycles: %i", trace_info->delay_cycles);
 
 	return ERROR_OK;
 }
@@ -741,7 +741,7 @@ COMMAND_HANDLER(handle_esirisc_trace_status_command)
 	uint32_t status;
 
 	if (!esirisc->has_trace) {
-		command_print(CMD_CTX, "target does not support trace");
+		command_print(CMD, "target does not support trace");
 		return ERROR_FAIL;
 	}
 
@@ -749,7 +749,7 @@ COMMAND_HANDLER(handle_esirisc_trace_status_command)
 	if (retval != ERROR_OK)
 		return retval;
 
-	command_print(CMD_CTX, "trace is %s%s%s%s",
+	command_print(CMD, "trace is %s%s%s%s",
 			(status & STATUS_T)  ? "started" : "stopped",
 			(status & STATUS_TD) ? ", disabled"   : "",
 			(status & STATUS_W)  ? ", wrapped"    : "",
@@ -764,13 +764,13 @@ COMMAND_HANDLER(handle_esirisc_trace_start_command)
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 
 	if (!esirisc->has_trace) {
-		command_print(CMD_CTX, "target does not support trace");
+		command_print(CMD, "target does not support trace");
 		return ERROR_FAIL;
 	}
 
 	int retval = esirisc_trace_start(target);
 	if (retval == ERROR_OK)
-		command_print(CMD_CTX, "trace started");
+		command_print(CMD, "trace started");
 
 	return retval;
 }
@@ -781,13 +781,13 @@ COMMAND_HANDLER(handle_esirisc_trace_stop_command)
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 
 	if (!esirisc->has_trace) {
-		command_print(CMD_CTX, "target does not support trace");
+		command_print(CMD, "target does not support trace");
 		return ERROR_FAIL;
 	}
 
 	int retval = esirisc_trace_stop(target);
 	if (retval == ERROR_OK)
-		command_print(CMD_CTX, "trace stopped");
+		command_print(CMD, "trace stopped");
 
 	return retval;
 }
@@ -801,7 +801,7 @@ COMMAND_HANDLER(handle_esirisc_trace_analyze_command)
 	uint32_t size;
 
 	if (!esirisc->has_trace) {
-		command_print(CMD_CTX, "target does not support trace");
+		command_print(CMD, "target does not support trace");
 		return ERROR_FAIL;
 	}
 
@@ -817,16 +817,16 @@ COMMAND_HANDLER(handle_esirisc_trace_analyze_command)
 		 * as arguments as a workaround.
 		 */
 		if (esirisc_trace_is_fifo(trace_info)) {
-			command_print(CMD_CTX, "analyze from FIFO not supported");
+			command_print(CMD, "analyze from FIFO not supported");
 			return ERROR_FAIL;
 		}
 
-		return esirisc_trace_analyze_buffer(CMD_CTX);
+		return esirisc_trace_analyze_buffer(CMD);
 	} else {
 		COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
 		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
 
-		return esirisc_trace_analyze_memory(CMD_CTX, address, size);
+		return esirisc_trace_analyze_memory(CMD, address, size);
 	}
 }
 
@@ -839,7 +839,7 @@ COMMAND_HANDLER(handle_esirisc_trace_dump_command)
 	uint32_t size;
 
 	if (!esirisc->has_trace) {
-		command_print(CMD_CTX, "target does not support trace");
+		command_print(CMD, "target does not support trace");
 		return ERROR_FAIL;
 	}
 
@@ -849,16 +849,16 @@ COMMAND_HANDLER(handle_esirisc_trace_dump_command)
 	if (CMD_ARGC == 1) {
 		/* also see: handle_esirisc_trace_analyze_command() */
 		if (esirisc_trace_is_fifo(trace_info)) {
-			command_print(CMD_CTX, "dump from FIFO not supported");
+			command_print(CMD, "dump from FIFO not supported");
 			return ERROR_FAIL;
 		}
 
-		return esirisc_trace_dump_buffer(CMD_CTX, CMD_ARGV[0]);
+		return esirisc_trace_dump_buffer(CMD, CMD_ARGV[0]);
 	} else {
 		COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
 		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
 
-		return esirisc_trace_dump_memory(CMD_CTX, CMD_ARGV[2], address, size);
+		return esirisc_trace_dump_memory(CMD, CMD_ARGV[2], address, size);
 	}
 }
 
@@ -946,7 +946,7 @@ COMMAND_HANDLER(handle_esirisc_trace_format_command)
 	COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], pc_bits);
 
 	if (pc_bits < 1 || pc_bits > 31) {
-		command_print(CMD_CTX, "invalid pc_bits: %i; must be 1..31", pc_bits);
+		command_print(CMD, "invalid pc_bits: %i; must be 1..31", pc_bits);
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
diff --git a/src/target/etb.c b/src/target/etb.c
index 98a90a5..392c6ad 100644
--- a/src/target/etb.c
+++ b/src/target/etb.c
@@ -344,13 +344,13 @@ COMMAND_HANDLER(handle_etb_config_command)
 
 	arm = target_to_arm(target);
 	if (!is_arm(arm)) {
-		command_print(CMD_CTX, "ETB: '%s' isn't an ARM", CMD_ARGV[0]);
+		command_print(CMD, "ETB: '%s' isn't an ARM", CMD_ARGV[0]);
 		return ERROR_FAIL;
 	}
 
 	tap = jtag_tap_by_string(CMD_ARGV[1]);
 	if (tap == NULL) {
-		command_print(CMD_CTX, "ETB: TAP %s does not exist", CMD_ARGV[1]);
+		command_print(CMD, "ETB: TAP %s does not exist", CMD_ARGV[1]);
 		return ERROR_FAIL;
 	}
 
@@ -382,17 +382,17 @@ COMMAND_HANDLER(handle_etb_trigger_percent_command)
 	target = get_current_target(CMD_CTX);
 	arm = target_to_arm(target);
 	if (!is_arm(arm)) {
-		command_print(CMD_CTX, "ETB: current target isn't an ARM");
+		command_print(CMD, "ETB: current target isn't an ARM");
 		return ERROR_FAIL;
 	}
 
 	etm = arm->etm;
 	if (!etm) {
-		command_print(CMD_CTX, "ETB: target has no ETM configured");
+		command_print(CMD, "ETB: target has no ETM configured");
 		return ERROR_FAIL;
 	}
 	if (etm->capture_driver != &etb_capture_driver) {
-		command_print(CMD_CTX, "ETB: target not using ETB");
+		command_print(CMD, "ETB: target not using ETB");
 		return ERROR_FAIL;
 	}
 	etb = arm->etm->capture_driver_priv;
@@ -402,13 +402,13 @@ COMMAND_HANDLER(handle_etb_trigger_percent_command)
 
 		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], new_value);
 		if ((new_value < 2) || (new_value > 100))
-			command_print(CMD_CTX,
+			command_print(CMD,
 				"valid percentages are 2%% to 100%%");
 		else
 			etb->trigger_percent = (unsigned) new_value;
 	}
 
-	command_print(CMD_CTX, "%d percent of tracebuffer fills after trigger",
+	command_print(CMD, "%d percent of tracebuffer fills after trigger",
 		etb->trigger_percent);
 
 	return ERROR_OK;
@@ -441,6 +441,7 @@ static const struct command_registration etb_command_handlers[] = {
 		.mode = COMMAND_ANY,
 		.help = "Embedded Trace Buffer command group",
 		.chain = etb_config_command_handlers,
+		.usage = "",
 	},
 	COMMAND_REGISTRATION_DONE
 };
diff --git a/src/target/etm.c b/src/target/etm.c
index 6a00c23..5751348 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -859,7 +859,7 @@ static int etmv1_data(struct etm_context *ctx, int size, uint32_t *data)
 	return 0;
 }
 
-static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *cmd_ctx)
+static int etmv1_analyze_trace(struct etm_context *ctx, struct command_invocation *cmd)
 {
 	int retval;
 	struct arm_instruction instruction;
@@ -869,7 +869,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *
 		ctx->capture_driver->read_trace(ctx);
 
 	if (ctx->trace_depth == 0) {
-		command_print(cmd_ctx, "Trace is empty.");
+		command_print(cmd, "Trace is empty.");
 		return ERROR_OK;
 	}
 
@@ -893,7 +893,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *
 		int current_pc_ok = ctx->pc_ok;
 
 		if (ctx->trace_data[ctx->pipe_index].flags & ETMV1_TRIGGER_CYCLE)
-			command_print(cmd_ctx, "--- trigger ---");
+			command_print(cmd, "--- trigger ---");
 
 		/* instructions execute in IE/D or BE/D cycles */
 		if ((pipestat == STAT_IE) || (pipestat == STAT_ID))
@@ -942,7 +942,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *
 					next_pc = ctx->last_branch;
 					break;
 				case 0x1:	/* tracing enabled */
-					command_print(cmd_ctx,
+					command_print(cmd,
 						"--- tracing enabled at 0x%8.8" PRIx32 " ---",
 						ctx->last_branch);
 					ctx->current_pc = ctx->last_branch;
@@ -950,7 +950,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *
 					continue;
 					break;
 				case 0x2:	/* trace restarted after FIFO overflow */
-					command_print(cmd_ctx,
+					command_print(cmd,
 						"--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---",
 						ctx->last_branch);
 					ctx->current_pc = ctx->last_branch;
@@ -958,7 +958,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *
 					continue;
 					break;
 				case 0x3:	/* exit from debug state */
-					command_print(cmd_ctx,
+					command_print(cmd,
 						"--- exit from debug state at 0x%8.8" PRIx32 " ---",
 						ctx->last_branch);
 					ctx->current_pc = ctx->last_branch;
@@ -971,7 +971,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *
 					 * we have to move on with the next trace cycle
 					 */
 					if (!current_pc_ok) {
-						command_print(cmd_ctx,
+						command_print(cmd,
 							"--- periodic synchronization point at 0x%8.8" PRIx32 " ---",
 							next_pc);
 						ctx->current_pc = next_pc;
@@ -998,9 +998,9 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *
 				|| ((ctx->last_branch >= 0xffff0000) &&
 				(ctx->last_branch <= 0xffff0020))) {
 				if ((ctx->last_branch & 0xff) == 0x10)
-					command_print(cmd_ctx, "data abort");
+					command_print(cmd, "data abort");
 				else {
-					command_print(cmd_ctx,
+					command_print(cmd,
 						"exception vector 0x%2.2" PRIx32 "",
 						ctx->last_branch);
 					ctx->current_pc = ctx->last_branch;
@@ -1058,7 +1058,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *
 					ctx->ptr_ok = 1;
 
 				if (ctx->ptr_ok)
-					command_print(cmd_ctx,
+					command_print(cmd,
 						"address: 0x%8.8" PRIx32 "",
 						ctx->last_ptr);
 			}
@@ -1073,7 +1073,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *
 							uint32_t data;
 							if (etmv1_data(ctx, 4, &data) != 0)
 								return ERROR_ETM_ANALYSIS_FAILED;
-							command_print(cmd_ctx,
+							command_print(cmd,
 								"data: 0x%8.8" PRIx32 "",
 								data);
 						}
@@ -1084,7 +1084,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *
 					if (etmv1_data(ctx, arm_access_size(&instruction),
 						&data) != 0)
 						return ERROR_ETM_ANALYSIS_FAILED;
-					command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
+					command_print(cmd, "data: 0x%8.8" PRIx32 "", data);
 				}
 			}
 
@@ -1119,7 +1119,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *
 					(cycles == 1) ? "cycle" : "cycles");
 			}
 
-			command_print(cmd_ctx, "%s%s%s",
+			command_print(cmd, "%s%s%s",
 				instruction.text,
 				(pipestat == STAT_IN) ? " (not executed)" : "",
 				cycles_text);
@@ -1156,7 +1156,7 @@ static COMMAND_HELPER(handle_etm_tracemode_command_update,
 	else if (strcmp(CMD_ARGV[0], "all") == 0)
 		tracemode = ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR;
 	else {
-		command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[0]);
+		command_print(CMD, "invalid option '%s'", CMD_ARGV[0]);
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
@@ -1176,7 +1176,7 @@ static COMMAND_HELPER(handle_etm_tracemode_command_update,
 			tracemode |= ETM_CTRL_CONTEXTID_32;
 			break;
 		default:
-			command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[1]);
+			command_print(CMD, "invalid option '%s'", CMD_ARGV[1]);
 			return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
@@ -1207,13 +1207,13 @@ COMMAND_HANDLER(handle_etm_tracemode_command)
 	struct etm_context *etm;
 
 	if (!is_arm(arm)) {
-		command_print(CMD_CTX, "ETM: current target isn't an ARM");
+		command_print(CMD, "ETM: current target isn't an ARM");
 		return ERROR_FAIL;
 	}
 
 	etm = arm->etm;
 	if (!etm) {
-		command_print(CMD_CTX, "current target doesn't have an ETM configured");
+		command_print(CMD, "current target doesn't have an ETM configured");
 		return ERROR_FAIL;
 	}
 
@@ -1235,47 +1235,47 @@ COMMAND_HANDLER(handle_etm_tracemode_command)
 	 * or couldn't be written; display actual hardware state...
 	 */
 
-	command_print(CMD_CTX, "current tracemode configuration:");
+	command_print(CMD, "current tracemode configuration:");
 
 	switch (tracemode & ETM_CTRL_TRACE_MASK) {
 		default:
-			command_print(CMD_CTX, "data tracing: none");
+			command_print(CMD, "data tracing: none");
 			break;
 		case ETM_CTRL_TRACE_DATA:
-			command_print(CMD_CTX, "data tracing: data only");
+			command_print(CMD, "data tracing: data only");
 			break;
 		case ETM_CTRL_TRACE_ADDR:
-			command_print(CMD_CTX, "data tracing: address only");
+			command_print(CMD, "data tracing: address only");
 			break;
 		case ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR:
-			command_print(CMD_CTX, "data tracing: address and data");
+			command_print(CMD, "data tracing: address and data");
 			break;
 	}
 
 	switch (tracemode & ETM_CTRL_CONTEXTID_MASK) {
 		case ETM_CTRL_CONTEXTID_NONE:
-			command_print(CMD_CTX, "contextid tracing: none");
+			command_print(CMD, "contextid tracing: none");
 			break;
 		case ETM_CTRL_CONTEXTID_8:
-			command_print(CMD_CTX, "contextid tracing: 8 bit");
+			command_print(CMD, "contextid tracing: 8 bit");
 			break;
 		case ETM_CTRL_CONTEXTID_16:
-			command_print(CMD_CTX, "contextid tracing: 16 bit");
+			command_print(CMD, "contextid tracing: 16 bit");
 			break;
 		case ETM_CTRL_CONTEXTID_32:
-			command_print(CMD_CTX, "contextid tracing: 32 bit");
+			command_print(CMD, "contextid tracing: 32 bit");
 			break;
 	}
 
 	if (tracemode & ETM_CTRL_CYCLE_ACCURATE)
-		command_print(CMD_CTX, "cycle-accurate tracing enabled");
+		command_print(CMD, "cycle-accurate tracing enabled");
 	else
-		command_print(CMD_CTX, "cycle-accurate tracing disabled");
+		command_print(CMD, "cycle-accurate tracing disabled");
 
 	if (tracemode & ETM_CTRL_BRANCH_OUTPUT)
-		command_print(CMD_CTX, "full branch address output enabled");
+		command_print(CMD, "full branch address output enabled");
 	else
-		command_print(CMD_CTX, "full branch address output disabled");
+		command_print(CMD, "full branch address output disabled");
 
 #define TRACEMODE_MASK ( \
 		ETM_CTRL_CONTEXTID_MASK	\
@@ -1331,7 +1331,7 @@ COMMAND_HANDLER(handle_etm_config_command)
 
 	arm = target_to_arm(target);
 	if (!is_arm(arm)) {
-		command_print(CMD_CTX, "target '%s' is '%s'; not an ARM",
+		command_print(CMD, "target '%s' is '%s'; not an ARM",
 			target_name(target),
 			target_type_name(target));
 		return ERROR_FAIL;
@@ -1382,7 +1382,7 @@ COMMAND_HANDLER(handle_etm_config_command)
 			portmode |= ETM_PORT_2BIT;
 			break;
 		default:
-			command_print(CMD_CTX,
+			command_print(CMD,
 				"unsupported ETM port width '%s'", CMD_ARGV[1]);
 			return ERROR_FAIL;
 	}
@@ -1394,7 +1394,7 @@ COMMAND_HANDLER(handle_etm_config_command)
 	else if (strcmp("demultiplexed", CMD_ARGV[2]) == 0)
 		portmode |= ETM_PORT_DEMUXED;
 	else {
-		command_print(CMD_CTX,
+		command_print(CMD,
 			"unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'",
 			CMD_ARGV[2]);
 		return ERROR_FAIL;
@@ -1405,7 +1405,7 @@ COMMAND_HANDLER(handle_etm_config_command)
 	else if (strcmp("full", CMD_ARGV[3]) == 0)
 		portmode |= ETM_PORT_FULL_CLOCK;
 	else {
-		command_print(CMD_CTX,
+		command_print(CMD,
 			"unsupported ETM port clocking '%s', must be 'full' or 'half'",
 			CMD_ARGV[3]);
 		return ERROR_FAIL;
@@ -1461,44 +1461,44 @@ COMMAND_HANDLER(handle_etm_info_command)
 	target = get_current_target(CMD_CTX);
 	arm = target_to_arm(target);
 	if (!is_arm(arm)) {
-		command_print(CMD_CTX, "ETM: current target isn't an ARM");
+		command_print(CMD, "ETM: current target isn't an ARM");
 		return ERROR_FAIL;
 	}
 
 	etm = arm->etm;
 	if (!etm) {
-		command_print(CMD_CTX, "current target doesn't have an ETM configured");
+		command_print(CMD, "current target doesn't have an ETM configured");
 		return ERROR_FAIL;
 	}
 
-	command_print(CMD_CTX, "ETM v%d.%d",
+	command_print(CMD, "ETM v%d.%d",
 		etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
-	command_print(CMD_CTX, "pairs of address comparators: %i",
+	command_print(CMD, "pairs of address comparators: %i",
 		(int) (etm->config >> 0) & 0x0f);
-	command_print(CMD_CTX, "data comparators: %i",
+	command_print(CMD, "data comparators: %i",
 		(int) (etm->config >> 4) & 0x0f);
-	command_print(CMD_CTX, "memory map decoders: %i",
+	command_print(CMD, "memory map decoders: %i",
 		(int) (etm->config >> 8) & 0x1f);
-	command_print(CMD_CTX, "number of counters: %i",
+	command_print(CMD, "number of counters: %i",
 		(int) (etm->config >> 13) & 0x07);
-	command_print(CMD_CTX, "sequencer %spresent",
+	command_print(CMD, "sequencer %spresent",
 		(int) (etm->config & (1 << 16)) ? "" : "not ");
-	command_print(CMD_CTX, "number of ext. inputs: %i",
+	command_print(CMD, "number of ext. inputs: %i",
 		(int) (etm->config >> 17) & 0x07);
-	command_print(CMD_CTX, "number of ext. outputs: %i",
+	command_print(CMD, "number of ext. outputs: %i",
 		(int) (etm->config >> 20) & 0x07);
-	command_print(CMD_CTX, "FIFO full %spresent",
+	command_print(CMD, "FIFO full %spresent",
 		(int) (etm->config & (1 << 23)) ? "" : "not ");
 	if (etm->bcd_vers < 0x20)
-		command_print(CMD_CTX, "protocol version: %i",
+		command_print(CMD, "protocol version: %i",
 			(int) (etm->config >> 28) & 0x07);
 	else {
-		command_print(CMD_CTX,
+		command_print(CMD,
 			"coprocessor and memory access %ssupported",
 			(etm->config & (1 << 26)) ? "" : "not ");
-		command_print(CMD_CTX, "trace start/stop %spresent",
+		command_print(CMD, "trace start/stop %spresent",
 			(etm->config & (1 << 26)) ? "" : "not ");
-		command_print(CMD_CTX, "number of context comparators: %i",
+		command_print(CMD, "number of context comparators: %i",
 			(int) (etm->config >> 24) & 0x03);
 	}
 
@@ -1549,30 +1549,30 @@ COMMAND_HANDLER(handle_etm_info_command)
 			LOG_ERROR("Illegal max_port_size");
 			return ERROR_FAIL;
 	}
-	command_print(CMD_CTX, "max. port size: %i", max_port_size);
+	command_print(CMD, "max. port size: %i", max_port_size);
 
 	if (etm->bcd_vers < 0x30) {
-		command_print(CMD_CTX, "half-rate clocking %ssupported",
+		command_print(CMD, "half-rate clocking %ssupported",
 			(config & (1 << 3)) ? "" : "not ");
-		command_print(CMD_CTX, "full-rate clocking %ssupported",
+		command_print(CMD, "full-rate clocking %ssupported",
 			(config & (1 << 4)) ? "" : "not ");
-		command_print(CMD_CTX, "normal trace format %ssupported",
+		command_print(CMD, "normal trace format %ssupported",
 			(config & (1 << 5)) ? "" : "not ");
-		command_print(CMD_CTX, "multiplex trace format %ssupported",
+		command_print(CMD, "multiplex trace format %ssupported",
 			(config & (1 << 6)) ? "" : "not ");
-		command_print(CMD_CTX, "demultiplex trace format %ssupported",
+		command_print(CMD, "demultiplex trace format %ssupported",
 			(config & (1 << 7)) ? "" : "not ");
 	} else {
 		/* REVISIT show which size and format are selected ... */
-		command_print(CMD_CTX, "current port size %ssupported",
+		command_print(CMD, "current port size %ssupported",
 			(config & (1 << 10)) ? "" : "not ");
-		command_print(CMD_CTX, "current trace format %ssupported",
+		command_print(CMD, "current trace format %ssupported",
 			(config & (1 << 11)) ? "" : "not ");
 	}
 	if (etm->bcd_vers >= 0x21)
-		command_print(CMD_CTX, "fetch comparisons %ssupported",
+		command_print(CMD, "fetch comparisons %ssupported",
 			(config & (1 << 17)) ? "not " : "");
-	command_print(CMD_CTX, "FIFO full %ssupported",
+	command_print(CMD, "FIFO full %ssupported",
 		(config & (1 << 8)) ? "" : "not ");
 
 	return ERROR_OK;
@@ -1588,13 +1588,13 @@ COMMAND_HANDLER(handle_etm_status_command)
 	target = get_current_target(CMD_CTX);
 	arm = target_to_arm(target);
 	if (!is_arm(arm)) {
-		command_print(CMD_CTX, "ETM: current target isn't an ARM");
+		command_print(CMD, "ETM: current target isn't an ARM");
 		return ERROR_FAIL;
 	}
 
 	etm = arm->etm;
 	if (!etm) {
-		command_print(CMD_CTX, "current target doesn't have an ETM configured");
+		command_print(CMD, "current target doesn't have an ETM configured");
 		return ERROR_FAIL;
 	}
 
@@ -1608,7 +1608,7 @@ COMMAND_HANDLER(handle_etm_status_command)
 		if (etm_get_reg(reg) == ERROR_OK) {
 			unsigned s = buf_get_u32(reg->value, 0, reg->size);
 
-			command_print(CMD_CTX, "etm: %s%s%s%s",
+			command_print(CMD, "etm: %s%s%s%s",
 				/* bit(1) == progbit */
 				(etm->bcd_vers >= 0x12)
 				? ((s & (1 << 1))
@@ -1626,21 +1626,21 @@ COMMAND_HANDLER(handle_etm_status_command)
 	/* Trace Port Driver status */
 	trace_status = etm->capture_driver->status(etm);
 	if (trace_status == TRACE_IDLE)
-		command_print(CMD_CTX, "%s: idle", etm->capture_driver->name);
+		command_print(CMD, "%s: idle", etm->capture_driver->name);
 	else {
 		static char *completed = " completed";
 		static char *running = " is running";
 		static char *overflowed = ", overflowed";
 		static char *triggered = ", triggered";
 
-		command_print(CMD_CTX, "%s: trace collection%s%s%s",
+		command_print(CMD, "%s: trace collection%s%s%s",
 			etm->capture_driver->name,
 			(trace_status & TRACE_RUNNING) ? running : completed,
 			(trace_status & TRACE_OVERFLOWED) ? overflowed : "",
 			(trace_status & TRACE_TRIGGERED) ? triggered : "");
 
 		if (etm->trace_depth > 0) {
-			command_print(CMD_CTX, "%i frames of trace data read",
+			command_print(CMD, "%i frames of trace data read",
 				(int)(etm->trace_depth));
 		}
 	}
@@ -1660,20 +1660,20 @@ COMMAND_HANDLER(handle_etm_image_command)
 	target = get_current_target(CMD_CTX);
 	arm = target_to_arm(target);
 	if (!is_arm(arm)) {
-		command_print(CMD_CTX, "ETM: current target isn't an ARM");
+		command_print(CMD, "ETM: current target isn't an ARM");
 		return ERROR_FAIL;
 	}
 
 	etm_ctx = arm->etm;
 	if (!etm_ctx) {
-		command_print(CMD_CTX, "current target doesn't have an ETM configured");
+		command_print(CMD, "current target doesn't have an ETM configured");
 		return ERROR_FAIL;
 	}
 
 	if (etm_ctx->image) {
 		image_close(etm_ctx->image);
 		free(etm_ctx->image);
-		command_print(CMD_CTX, "previously loaded image found and closed");
+		command_print(CMD, "previously loaded image found and closed");
 	}
 
 	etm_ctx->image = malloc(sizeof(struct image));
@@ -1711,24 +1711,24 @@ COMMAND_HANDLER(handle_etm_dump_command)
 	target = get_current_target(CMD_CTX);
 	arm = target_to_arm(target);
 	if (!is_arm(arm)) {
-		command_print(CMD_CTX, "ETM: current target isn't an ARM");
+		command_print(CMD, "ETM: current target isn't an ARM");
 		return ERROR_FAIL;
 	}
 
 	etm_ctx = arm->etm;
 	if (!etm_ctx) {
-		command_print(CMD_CTX, "current target doesn't have an ETM configured");
+		command_print(CMD, "current target doesn't have an ETM configured");
 		return ERROR_FAIL;
 	}
 
 	if (etm_ctx->capture_driver->status == TRACE_IDLE) {
-		command_print(CMD_CTX, "trace capture wasn't enabled, no trace data captured");
+		command_print(CMD, "trace capture wasn't enabled, no trace data captured");
 		return ERROR_OK;
 	}
 
 	if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING) {
 		/* TODO: if on-the-fly capture is to be supported, this needs to be changed */
-		command_print(CMD_CTX, "trace capture not completed");
+		command_print(CMD, "trace capture not completed");
 		return ERROR_FAIL;
 	}
 
@@ -1768,18 +1768,18 @@ COMMAND_HANDLER(handle_etm_load_command)
 	target = get_current_target(CMD_CTX);
 	arm = target_to_arm(target);
 	if (!is_arm(arm)) {
-		command_print(CMD_CTX, "ETM: current target isn't an ARM");
+		command_print(CMD, "ETM: current target isn't an ARM");
 		return ERROR_FAIL;
 	}
 
 	etm_ctx = arm->etm;
 	if (!etm_ctx) {
-		command_print(CMD_CTX, "current target doesn't have an ETM configured");
+		command_print(CMD, "current target doesn't have an ETM configured");
 		return ERROR_FAIL;
 	}
 
 	if (etm_ctx->capture_driver->status(etm_ctx) & TRACE_RUNNING) {
-		command_print(CMD_CTX, "trace capture running, stop first");
+		command_print(CMD, "trace capture running, stop first");
 		return ERROR_FAIL;
 	}
 
@@ -1794,7 +1794,7 @@ COMMAND_HANDLER(handle_etm_load_command)
 	}
 
 	if (filesize % 4) {
-		command_print(CMD_CTX, "size isn't a multiple of 4, no valid trace data");
+		command_print(CMD, "size isn't a multiple of 4, no valid trace data");
 		fileio_close(file);
 		return ERROR_FAIL;
 	}
@@ -1812,7 +1812,7 @@ COMMAND_HANDLER(handle_etm_load_command)
 	}
 	etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
 	if (etm_ctx->trace_data == NULL) {
-		command_print(CMD_CTX, "not enough memory to perform operation");
+		command_print(CMD, "not enough memory to perform operation");
 		fileio_close(file);
 		return ERROR_FAIL;
 	}
@@ -1842,13 +1842,13 @@ COMMAND_HANDLER(handle_etm_start_command)
 	target = get_current_target(CMD_CTX);
 	arm = target_to_arm(target);
 	if (!is_arm(arm)) {
-		command_print(CMD_CTX, "ETM: current target isn't an ARM");
+		command_print(CMD, "ETM: current target isn't an ARM");
 		return ERROR_FAIL;
 	}
 
 	etm_ctx = arm->etm;
 	if (!etm_ctx) {
-		command_print(CMD_CTX, "current target doesn't have an ETM configured");
+		command_print(CMD, "current target doesn't have an ETM configured");
 		return ERROR_FAIL;
 	}
 
@@ -1887,13 +1887,13 @@ COMMAND_HANDLER(handle_etm_stop_command)
 	target = get_current_target(CMD_CTX);
 	arm = target_to_arm(target);
 	if (!is_arm(arm)) {
-		command_print(CMD_CTX, "ETM: current target isn't an ARM");
+		command_print(CMD, "ETM: current target isn't an ARM");
 		return ERROR_FAIL;
 	}
 
 	etm_ctx = arm->etm;
 	if (!etm_ctx) {
-		command_print(CMD_CTX, "current target doesn't have an ETM configured");
+		command_print(CMD, "current target doesn't have an ETM configured");
 		return ERROR_FAIL;
 	}
 
@@ -1923,14 +1923,14 @@ COMMAND_HANDLER(handle_etm_trigger_debug_command)
 	target = get_current_target(CMD_CTX);
 	arm = target_to_arm(target);
 	if (!is_arm(arm)) {
-		command_print(CMD_CTX, "ETM: %s isn't an ARM",
+		command_print(CMD, "ETM: %s isn't an ARM",
 			target_name(target));
 		return ERROR_FAIL;
 	}
 
 	etm = arm->etm;
 	if (!etm) {
-		command_print(CMD_CTX, "ETM: no ETM configured for %s",
+		command_print(CMD, "ETM: no ETM configured for %s",
 			target_name(target));
 		return ERROR_FAIL;
 	}
@@ -1955,7 +1955,7 @@ COMMAND_HANDLER(handle_etm_trigger_debug_command)
 		buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
 	}
 
-	command_print(CMD_CTX, "ETM: %s debug halt",
+	command_print(CMD, "ETM: %s debug halt",
 		(etm->control & ETM_CTRL_DBGRQ)
 		? "triggers"
 		: "does not trigger");
@@ -1972,33 +1972,33 @@ COMMAND_HANDLER(handle_etm_analyze_command)
 	target = get_current_target(CMD_CTX);
 	arm = target_to_arm(target);
 	if (!is_arm(arm)) {
-		command_print(CMD_CTX, "ETM: current target isn't an ARM");
+		command_print(CMD, "ETM: current target isn't an ARM");
 		return ERROR_FAIL;
 	}
 
 	etm_ctx = arm->etm;
 	if (!etm_ctx) {
-		command_print(CMD_CTX, "current target doesn't have an ETM configured");
+		command_print(CMD, "current target doesn't have an ETM configured");
 		return ERROR_FAIL;
 	}
 
-	retval = etmv1_analyze_trace(etm_ctx, CMD_CTX);
+	retval = etmv1_analyze_trace(etm_ctx, CMD);
 	if (retval != ERROR_OK) {
 		/* FIX! error should be reported inside etmv1_analyze_trace() */
 		switch (retval) {
 			case ERROR_ETM_ANALYSIS_FAILED:
-				command_print(CMD_CTX,
+				command_print(CMD,
 					"further analysis failed (corrupted trace data or just end of data");
 				break;
 			case ERROR_TRACE_INSTRUCTION_UNAVAILABLE:
-				command_print(CMD_CTX,
+				command_print(CMD,
 					"no instruction for current address available, analysis aborted");
 				break;
 			case ERROR_TRACE_IMAGE_UNAVAILABLE:
-				command_print(CMD_CTX, "no image available for trace analysis");
+				command_print(CMD, "no image available for trace analysis");
 				break;
 			default:
-				command_print(CMD_CTX, "unknown error");
+				command_print(CMD, "unknown error");
 		}
 	}
 
diff --git a/src/target/etm_dummy.c b/src/target/etm_dummy.c
index b18ce17..ba53c7a 100644
--- a/src/target/etm_dummy.c
+++ b/src/target/etm_dummy.c
@@ -37,7 +37,7 @@ COMMAND_HANDLER(handle_etm_dummy_config_command)
 
 	arm = target_to_arm(target);
 	if (!is_arm(arm)) {
-		command_print(CMD_CTX, "target '%s' isn't an ARM", CMD_ARGV[0]);
+		command_print(CMD, "target '%s' isn't an ARM", CMD_ARGV[0]);
 		return ERROR_FAIL;
 	}
 
@@ -66,6 +66,7 @@ static const struct command_registration etm_dummy_command_handlers[] = {
 		.mode = COMMAND_ANY,
 		.help = "Dummy ETM capture driver command group",
 		.chain = etm_dummy_config_command_handlers,
+		.usage = "",
 	},
 	COMMAND_REGISTRATION_DONE
 };
diff --git a/src/target/mem_ap.c b/src/target/mem_ap.c
index 584e19d..29cd37a 100644
--- a/src/target/mem_ap.c
+++ b/src/target/mem_ap.c
@@ -140,7 +140,7 @@ static int mem_ap_read_memory(struct target *target, target_addr_t address,
 {
 	struct mem_ap *mem_ap = target->arch_info;
 
-	LOG_DEBUG("Reading memory at physical address 0x" TARGET_ADDR_FMT
+	LOG_DEBUG("Reading memory at physical address " TARGET_ADDR_FMT
 		  "; size %" PRId32 "; count %" PRId32, address, size, count);
 
 	if (count == 0 || buffer == NULL)
@@ -155,7 +155,7 @@ static int mem_ap_write_memory(struct target *target, target_addr_t address,
 {
 	struct mem_ap *mem_ap = target->arch_info;
 
-	LOG_DEBUG("Writing memory at physical address 0x" TARGET_ADDR_FMT
+	LOG_DEBUG("Writing memory at physical address " TARGET_ADDR_FMT
 		  "; size %" PRId32 "; count %" PRId32, address, size, count);
 
 	if (count == 0 || buffer == NULL)
diff --git a/src/target/mips32.c b/src/target/mips32.c
index d9d8ba9..5260032 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -905,11 +905,11 @@ cleanup:
 	return 1;       /* only one block has been checked */
 }
 
-static int mips32_verify_pointer(struct command_context *cmd_ctx,
+static int mips32_verify_pointer(struct command_invocation *cmd,
 		struct mips32_common *mips32)
 {
 	if (mips32->common_magic != MIPS32_COMMON_MAGIC) {
-		command_print(cmd_ctx, "target is not an MIPS32");
+		command_print(cmd, "target is not an MIPS32");
 		return ERROR_TARGET_INVALID;
 	}
 	return ERROR_OK;
@@ -927,12 +927,12 @@ COMMAND_HANDLER(mips32_handle_cp0_command)
 	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 
 
-	retval = mips32_verify_pointer(CMD_CTX, mips32);
+	retval = mips32_verify_pointer(CMD, mips32);
 	if (retval != ERROR_OK)
 		return retval;
 
 	if (target->state != TARGET_HALTED) {
-		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+		command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
 		return ERROR_OK;
 	}
 
@@ -949,12 +949,12 @@ COMMAND_HANDLER(mips32_handle_cp0_command)
 
 			retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
 			if (retval != ERROR_OK) {
-				command_print(CMD_CTX,
+				command_print(CMD,
 						"couldn't access reg %" PRIi32,
 						cp0_reg);
 				return ERROR_OK;
 			}
-			command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
+			command_print(CMD, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
 					cp0_reg, cp0_sel, value);
 
 		} else if (CMD_ARGC == 3) {
@@ -962,12 +962,12 @@ COMMAND_HANDLER(mips32_handle_cp0_command)
 			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
 			retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
 			if (retval != ERROR_OK) {
-				command_print(CMD_CTX,
+				command_print(CMD,
 						"couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
 						cp0_reg,  cp0_sel);
 				return ERROR_OK;
 			}
-			command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
+			command_print(CMD, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
 					cp0_reg, cp0_sel, value);
 		}
 	}
@@ -986,13 +986,13 @@ COMMAND_HANDLER(mips32_handle_scan_delay_command)
 	else if (CMD_ARGC > 1)
 			return ERROR_COMMAND_SYNTAX_ERROR;
 
-	command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay);
+	command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay);
 	if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {
 		ejtag_info->mode = 0;
-		command_print(CMD_CTX, "running in legacy mode");
+		command_print(CMD, "running in legacy mode");
 	} else {
 		ejtag_info->mode = 1;
-		command_print(CMD_CTX, "running in fast queued mode");
+		command_print(CMD, "running in fast queued mode");
 	}
 
 	return ERROR_OK;
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 653d732..ad27520 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -1270,11 +1270,11 @@ static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t addre
 	return retval;
 }
 
-static int mips_m4k_verify_pointer(struct command_context *cmd_ctx,
+static int mips_m4k_verify_pointer(struct command_invocation *cmd,
 		struct mips_m4k_common *mips_m4k)
 {
 	if (mips_m4k->common_magic != MIPSM4K_COMMON_MAGIC) {
-		command_print(cmd_ctx, "target is not an MIPS_M4K");
+		command_print(cmd, "target is not an MIPS_M4K");
 		return ERROR_TARGET_INVALID;
 	}
 	return ERROR_OK;
@@ -1287,12 +1287,12 @@ COMMAND_HANDLER(mips_m4k_handle_cp0_command)
 	struct mips_m4k_common *mips_m4k = target_to_m4k(target);
 	struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
 
-	retval = mips_m4k_verify_pointer(CMD_CTX, mips_m4k);
+	retval = mips_m4k_verify_pointer(CMD, mips_m4k);
 	if (retval != ERROR_OK)
 		return retval;
 
 	if (target->state != TARGET_HALTED) {
-		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+		command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
 		return ERROR_OK;
 	}
 
@@ -1308,12 +1308,12 @@ COMMAND_HANDLER(mips_m4k_handle_cp0_command)
 			uint32_t value;
 			retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
 			if (retval != ERROR_OK) {
-				command_print(CMD_CTX,
+				command_print(CMD,
 						"couldn't access reg %" PRIi32,
 						cp0_reg);
 				return ERROR_OK;
 			}
-			command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
+			command_print(CMD, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
 					cp0_reg, cp0_sel, value);
 
 		} else if (CMD_ARGC == 3) {
@@ -1321,12 +1321,12 @@ COMMAND_HANDLER(mips_m4k_handle_cp0_command)
 			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
 			retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
 			if (retval != ERROR_OK) {
-				command_print(CMD_CTX,
+				command_print(CMD,
 						"couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
 						cp0_reg,  cp0_sel);
 				return ERROR_OK;
 			}
-			command_print(CMD_CTX, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
+			command_print(CMD, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
 					cp0_reg, cp0_sel, value);
 		}
 	}
@@ -1345,13 +1345,13 @@ COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)
 	else if (CMD_ARGC > 1)
 			return ERROR_COMMAND_SYNTAX_ERROR;
 
-	command_print(CMD_CTX, "scan delay: %d nsec", ejtag_info->scan_delay);
+	command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay);
 	if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {
 		ejtag_info->mode = 0;
-		command_print(CMD_CTX, "running in legacy mode");
+		command_print(CMD, "running in legacy mode");
 	} else {
 		ejtag_info->mode = 1;
-		command_print(CMD_CTX, "running in fast queued mode");
+		command_print(CMD, "running in fast queued mode");
 	}
 
 	return ERROR_OK;
diff --git a/src/target/nds32_cmd.c b/src/target/nds32_cmd.c
index 500651d..1accf6f 100644
--- a/src/target/nds32_cmd.c
+++ b/src/target/nds32_cmd.c
@@ -46,7 +46,7 @@ COMMAND_HANDLER(handle_nds32_dssim_command)
 	struct nds32 *nds32 = target_to_nds32(target);
 
 	if (!is_nds32(nds32)) {
-		command_print(CMD_CTX, "current target isn't an Andes core");
+		command_print(CMD, "current target isn't an Andes core");
 		return ERROR_FAIL;
 	}
 
@@ -57,7 +57,7 @@ COMMAND_HANDLER(handle_nds32_dssim_command)
 			nds32->step_isr_enable = false;
 	}
 
-	command_print(CMD_CTX, "%s: $INT_MASK.DSSIM: %d", target_name(target),
+	command_print(CMD, "%s: $INT_MASK.DSSIM: %d", target_name(target),
 			nds32->step_isr_enable);
 
 	return ERROR_OK;
@@ -71,7 +71,7 @@ COMMAND_HANDLER(handle_nds32_memory_access_command)
 	struct nds32_memory *memory = &(nds32->memory);
 
 	if (!is_nds32(nds32)) {
-		command_print(CMD_CTX, "current target isn't an Andes core");
+		command_print(CMD, "current target isn't an Andes core");
 		return ERROR_FAIL;
 	}
 
@@ -88,7 +88,7 @@ COMMAND_HANDLER(handle_nds32_memory_access_command)
 
 		aice_memory_access(aice, memory->access_channel);
 	} else {
-		command_print(CMD_CTX, "%s: memory access channel: %s",
+		command_print(CMD, "%s: memory access channel: %s",
 				target_name(target),
 				NDS_MEMORY_ACCESS_NAME[memory->access_channel]);
 	}
@@ -103,18 +103,18 @@ COMMAND_HANDLER(handle_nds32_memory_mode_command)
 	struct aice_port_s *aice = target_to_aice(target);
 
 	if (!is_nds32(nds32)) {
-		command_print(CMD_CTX, "current target isn't an Andes core");
+		command_print(CMD, "current target isn't an Andes core");
 		return ERROR_FAIL;
 	}
 
 	if (CMD_ARGC > 0) {
 
 		if (nds32->edm.access_control == false) {
-			command_print(CMD_CTX, "%s does not support ACC_CTL. "
+			command_print(CMD, "%s does not support ACC_CTL. "
 					"Set memory mode to MEMORY", target_name(target));
 			nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
 		} else if (nds32->edm.direct_access_local_memory == false) {
-			command_print(CMD_CTX, "%s does not support direct access "
+			command_print(CMD, "%s does not support direct access "
 					"local memory. Set memory mode to MEMORY",
 					target_name(target));
 			nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
@@ -128,13 +128,13 @@ COMMAND_HANDLER(handle_nds32_memory_mode_command)
 				nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
 			} else if (strcmp(CMD_ARGV[0], "ilm") == 0) {
 				if (nds32->memory.ilm_base == 0)
-					command_print(CMD_CTX, "%s does not support ILM",
+					command_print(CMD, "%s does not support ILM",
 							target_name(target));
 				else
 					nds32->memory.mode = NDS_MEMORY_SELECT_ILM;
 			} else if (strcmp(CMD_ARGV[0], "dlm") == 0) {
 				if (nds32->memory.dlm_base == 0)
-					command_print(CMD_CTX, "%s does not support DLM",
+					command_print(CMD, "%s does not support DLM",
 							target_name(target));
 				else
 					nds32->memory.mode = NDS_MEMORY_SELECT_DLM;
@@ -145,7 +145,7 @@ COMMAND_HANDLER(handle_nds32_memory_mode_command)
 		}
 	}
 
-	command_print(CMD_CTX, "%s: memory mode: %s",
+	command_print(CMD, "%s: memory mode: %s",
 			target_name(target),
 			NDS_MEMORY_SELECT_NAME[nds32->memory.mode]);
 
@@ -162,7 +162,7 @@ COMMAND_HANDLER(handle_nds32_cache_command)
 	int result;
 
 	if (!is_nds32(nds32)) {
-		command_print(CMD_CTX, "current target isn't an Andes core");
+		command_print(CMD, "current target isn't an Andes core");
 		return ERROR_FAIL;
 	}
 
@@ -173,30 +173,30 @@ COMMAND_HANDLER(handle_nds32_cache_command)
 				/* D$ write back */
 				result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_WBALL, 0);
 				if (result != ERROR_OK) {
-					command_print(CMD_CTX, "%s: Write back data cache...failed",
+					command_print(CMD, "%s: Write back data cache...failed",
 							target_name(target));
 					return result;
 				}
 
-				command_print(CMD_CTX, "%s: Write back data cache...done",
+				command_print(CMD, "%s: Write back data cache...done",
 						target_name(target));
 
 				/* D$ invalidate */
 				result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_INVALALL, 0);
 				if (result != ERROR_OK) {
-					command_print(CMD_CTX, "%s: Invalidate data cache...failed",
+					command_print(CMD, "%s: Invalidate data cache...failed",
 							target_name(target));
 					return result;
 				}
 
-				command_print(CMD_CTX, "%s: Invalidate data cache...done",
+				command_print(CMD, "%s: Invalidate data cache...done",
 						target_name(target));
 			} else {
 				if (dcache->line_size == 0)
-					command_print(CMD_CTX, "%s: No data cache",
+					command_print(CMD, "%s: No data cache",
 							target_name(target));
 				else
-					command_print(CMD_CTX, "%s: Data cache disabled",
+					command_print(CMD, "%s: Data cache disabled",
 							target_name(target));
 			}
 
@@ -204,23 +204,23 @@ COMMAND_HANDLER(handle_nds32_cache_command)
 				/* I$ invalidate */
 				result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1I_INVALALL, 0);
 				if (result != ERROR_OK) {
-					command_print(CMD_CTX, "%s: Invalidate instruction cache...failed",
+					command_print(CMD, "%s: Invalidate instruction cache...failed",
 							target_name(target));
 					return result;
 				}
 
-				command_print(CMD_CTX, "%s: Invalidate instruction cache...done",
+				command_print(CMD, "%s: Invalidate instruction cache...done",
 						target_name(target));
 			} else {
 				if (icache->line_size == 0)
-					command_print(CMD_CTX, "%s: No instruction cache",
+					command_print(CMD, "%s: No instruction cache",
 							target_name(target));
 				else
-					command_print(CMD_CTX, "%s: Instruction cache disabled",
+					command_print(CMD, "%s: Instruction cache disabled",
 							target_name(target));
 			}
 		} else
-			command_print(CMD_CTX, "No valid parameter");
+			command_print(CMD, "No valid parameter");
 	}
 
 	return ERROR_OK;
@@ -235,14 +235,14 @@ COMMAND_HANDLER(handle_nds32_icache_command)
 	int result;
 
 	if (!is_nds32(nds32)) {
-		command_print(CMD_CTX, "current target isn't an Andes core");
+		command_print(CMD, "current target isn't an Andes core");
 		return ERROR_FAIL;
 	}
 
 	if (CMD_ARGC > 0) {
 
 		if (icache->line_size == 0) {
-			command_print(CMD_CTX, "%s: No instruction cache",
+			command_print(CMD, "%s: No instruction cache",
 					target_name(target));
 			return ERROR_OK;
 		}
@@ -252,15 +252,15 @@ COMMAND_HANDLER(handle_nds32_icache_command)
 				/* I$ invalidate */
 				result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1I_INVALALL, 0);
 				if (result != ERROR_OK) {
-					command_print(CMD_CTX, "%s: Invalidate instruction cache...failed",
+					command_print(CMD, "%s: Invalidate instruction cache...failed",
 							target_name(target));
 					return result;
 				}
 
-				command_print(CMD_CTX, "%s: Invalidate instruction cache...done",
+				command_print(CMD, "%s: Invalidate instruction cache...done",
 						target_name(target));
 			} else {
-				command_print(CMD_CTX, "%s: Instruction cache disabled",
+				command_print(CMD, "%s: Instruction cache disabled",
 						target_name(target));
 			}
 		} else if (strcmp(CMD_ARGV[0], "enable") == 0) {
@@ -274,7 +274,7 @@ COMMAND_HANDLER(handle_nds32_icache_command)
 		} else if (strcmp(CMD_ARGV[0], "dump") == 0) {
 			/* TODO: dump cache content */
 		} else {
-			command_print(CMD_CTX, "%s: No valid parameter", target_name(target));
+			command_print(CMD, "%s: No valid parameter", target_name(target));
 		}
 	}
 
@@ -290,14 +290,14 @@ COMMAND_HANDLER(handle_nds32_dcache_command)
 	int result;
 
 	if (!is_nds32(nds32)) {
-		command_print(CMD_CTX, "current target isn't an Andes core");
+		command_print(CMD, "current target isn't an Andes core");
 		return ERROR_FAIL;
 	}
 
 	if (CMD_ARGC > 0) {
 
 		if (dcache->line_size == 0) {
-			command_print(CMD_CTX, "%s: No data cache", target_name(target));
+			command_print(CMD, "%s: No data cache", target_name(target));
 			return ERROR_OK;
 		}
 
@@ -306,26 +306,26 @@ COMMAND_HANDLER(handle_nds32_dcache_command)
 				/* D$ write back */
 				result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_WBALL, 0);
 				if (result != ERROR_OK) {
-					command_print(CMD_CTX, "%s: Write back data cache...failed",
+					command_print(CMD, "%s: Write back data cache...failed",
 							target_name(target));
 					return result;
 				}
 
-				command_print(CMD_CTX, "%s: Write back data cache...done",
+				command_print(CMD, "%s: Write back data cache...done",
 						target_name(target));
 
 				/* D$ invalidate */
 				result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_INVALALL, 0);
 				if (result != ERROR_OK) {
-					command_print(CMD_CTX, "%s: Invalidate data cache...failed",
+					command_print(CMD, "%s: Invalidate data cache...failed",
 							target_name(target));
 					return result;
 				}
 
-				command_print(CMD_CTX, "%s: Invalidate data cache...done",
+				command_print(CMD, "%s: Invalidate data cache...done",
 						target_name(target));
 			} else {
-				command_print(CMD_CTX, "%s: Data cache disabled",
+				command_print(CMD, "%s: Data cache disabled",
 						target_name(target));
 			}
 		} else if (strcmp(CMD_ARGV[0], "enable") == 0) {
@@ -339,7 +339,7 @@ COMMAND_HANDLER(handle_nds32_dcache_command)
 		} else if (strcmp(CMD_ARGV[0], "dump") == 0) {
 			/* TODO: dump cache content */
 		} else {
-			command_print(CMD_CTX, "%s: No valid parameter", target_name(target));
+			command_print(CMD, "%s: No valid parameter", target_name(target));
 		}
 	}
 
@@ -352,7 +352,7 @@ COMMAND_HANDLER(handle_nds32_auto_break_command)
 	struct nds32 *nds32 = target_to_nds32(target);
 
 	if (!is_nds32(nds32)) {
-		command_print(CMD_CTX, "current target isn't an Andes core");
+		command_print(CMD, "current target isn't an Andes core");
 		return ERROR_FAIL;
 	}
 
@@ -364,10 +364,10 @@ COMMAND_HANDLER(handle_nds32_auto_break_command)
 	}
 
 	if (nds32->auto_convert_hw_bp)
-		command_print(CMD_CTX, "%s: convert sw break to hw break on ROM: on",
+		command_print(CMD, "%s: convert sw break to hw break on ROM: on",
 				target_name(target));
 	else
-		command_print(CMD_CTX, "%s: convert sw break to hw break on ROM: off",
+		command_print(CMD, "%s: convert sw break to hw break on ROM: off",
 				target_name(target));
 
 	return ERROR_OK;
@@ -379,7 +379,7 @@ COMMAND_HANDLER(handle_nds32_virtual_hosting_command)
 	struct nds32 *nds32 = target_to_nds32(target);
 
 	if (!is_nds32(nds32)) {
-		command_print(CMD_CTX, "current target isn't an Andes core");
+		command_print(CMD, "current target isn't an Andes core");
 		return ERROR_FAIL;
 	}
 
@@ -391,9 +391,9 @@ COMMAND_HANDLER(handle_nds32_virtual_hosting_command)
 	}
 
 	if (nds32->virtual_hosting)
-		command_print(CMD_CTX, "%s: virtual hosting: on", target_name(target));
+		command_print(CMD, "%s: virtual hosting: on", target_name(target));
 	else
-		command_print(CMD_CTX, "%s: virtual hosting: off", target_name(target));
+		command_print(CMD, "%s: virtual hosting: off", target_name(target));
 
 	return ERROR_OK;
 }
@@ -404,7 +404,7 @@ COMMAND_HANDLER(handle_nds32_global_stop_command)
 	struct nds32 *nds32 = target_to_nds32(target);
 
 	if (!is_nds32(nds32)) {
-		command_print(CMD_CTX, "current target isn't an Andes core");
+		command_print(CMD, "current target isn't an Andes core");
 		return ERROR_FAIL;
 	}
 
@@ -429,7 +429,7 @@ COMMAND_HANDLER(handle_nds32_soft_reset_halt_command)
 	struct nds32 *nds32 = target_to_nds32(target);
 
 	if (!is_nds32(nds32)) {
-		command_print(CMD_CTX, "current target isn't an Andes core");
+		command_print(CMD, "current target isn't an Andes core");
 		return ERROR_FAIL;
 	}
 
@@ -454,7 +454,7 @@ COMMAND_HANDLER(handle_nds32_boot_time_command)
 	struct nds32 *nds32 = target_to_nds32(target);
 
 	if (!is_nds32(nds32)) {
-		command_print(CMD_CTX, "current target isn't an Andes core");
+		command_print(CMD, "current target isn't an Andes core");
 		return ERROR_FAIL;
 	}
 
@@ -470,7 +470,7 @@ COMMAND_HANDLER(handle_nds32_login_edm_passcode_command)
 	struct nds32 *nds32 = target_to_nds32(target);
 
 	if (!is_nds32(nds32)) {
-		command_print(CMD_CTX, "current target isn't an Andes core");
+		command_print(CMD, "current target isn't an Andes core");
 		return ERROR_FAIL;
 	}
 
@@ -485,7 +485,7 @@ COMMAND_HANDLER(handle_nds32_login_edm_operation_command)
 	struct nds32 *nds32 = target_to_nds32(target);
 
 	if (!is_nds32(nds32)) {
-		command_print(CMD_CTX, "current target isn't an Andes core");
+		command_print(CMD, "current target isn't an Andes core");
 		return ERROR_FAIL;
 	}
 
@@ -516,7 +516,7 @@ COMMAND_HANDLER(handle_nds32_reset_halt_as_init_command)
 	struct nds32 *nds32 = target_to_nds32(target);
 
 	if (!is_nds32(nds32)) {
-		command_print(CMD_CTX, "current target isn't an Andes core");
+		command_print(CMD, "current target isn't an Andes core");
 		return ERROR_FAIL;
 	}
 
@@ -536,7 +536,7 @@ COMMAND_HANDLER(handle_nds32_keep_target_edm_ctl_command)
 	struct nds32 *nds32 = target_to_nds32(target);
 
 	if (!is_nds32(nds32)) {
-		command_print(CMD_CTX, "current target isn't an Andes core");
+		command_print(CMD, "current target isn't an Andes core");
 		return ERROR_FAIL;
 	}
 
@@ -556,7 +556,7 @@ COMMAND_HANDLER(handle_nds32_decode_command)
 	struct nds32 *nds32 = target_to_nds32(target);
 
 	if (!is_nds32(nds32)) {
-		command_print(CMD_CTX, "current target isn't an Andes core");
+		command_print(CMD, "current target isn't an Andes core");
 		return ERROR_FAIL;
 	}
 
@@ -581,7 +581,7 @@ COMMAND_HANDLER(handle_nds32_decode_command)
 						read_addr, &instruction))
 				return ERROR_FAIL;
 
-			command_print(CMD_CTX, "%s", instruction.text);
+			command_print(CMD, "%s", instruction.text);
 
 			read_addr += instruction.instruction_size;
 			i++;
@@ -599,7 +599,7 @@ COMMAND_HANDLER(handle_nds32_decode_command)
 		if (ERROR_OK != nds32_evaluate_opcode(nds32, opcode, addr, &instruction))
 			return ERROR_FAIL;
 
-		command_print(CMD_CTX, "%s", instruction.text);
+		command_print(CMD, "%s", instruction.text);
 	} else
 		return ERROR_FAIL;
 
@@ -612,7 +612,7 @@ COMMAND_HANDLER(handle_nds32_word_access_mem_command)
 	struct nds32 *nds32 = target_to_nds32(target);
 
 	if (!is_nds32(nds32)) {
-		command_print(CMD_CTX, "current target isn't an Andes core");
+		command_print(CMD, "current target isn't an Andes core");
 		return ERROR_FAIL;
 	}
 
@@ -632,11 +632,11 @@ COMMAND_HANDLER(handle_nds32_query_target_command)
 	struct nds32 *nds32 = target_to_nds32(target);
 
 	if (!is_nds32(nds32)) {
-		command_print(CMD_CTX, "current target isn't an Andes core");
+		command_print(CMD, "current target isn't an Andes core");
 		return ERROR_FAIL;
 	}
 
-	command_print(CMD_CTX, "OCD");
+	command_print(CMD, "OCD");
 
 	return ERROR_OK;
 }
@@ -647,7 +647,7 @@ COMMAND_HANDLER(handle_nds32_query_endian_command)
 	struct nds32 *nds32 = target_to_nds32(target);
 
 	if (!is_nds32(nds32)) {
-		command_print(CMD_CTX, "current target isn't an Andes core");
+		command_print(CMD, "current target isn't an Andes core");
 		return ERROR_FAIL;
 	}
 
@@ -655,9 +655,9 @@ COMMAND_HANDLER(handle_nds32_query_endian_command)
 	nds32_get_mapped_reg(nds32, IR0, &value_psw);
 
 	if (value_psw & 0x20)
-		command_print(CMD_CTX, "%s: BE", target_name(target));
+		command_print(CMD, "%s: BE", target_name(target));
 	else
-		command_print(CMD_CTX, "%s: LE", target_name(target));
+		command_print(CMD, "%s: LE", target_name(target));
 
 	return ERROR_OK;
 }
@@ -668,11 +668,11 @@ COMMAND_HANDLER(handle_nds32_query_cpuid_command)
 	struct nds32 *nds32 = target_to_nds32(target);
 
 	if (!is_nds32(nds32)) {
-		command_print(CMD_CTX, "current target isn't an Andes core");
+		command_print(CMD, "current target isn't an Andes core");
 		return ERROR_FAIL;
 	}
 
-	command_print(CMD_CTX, "CPUID: %s", target_name(target));
+	command_print(CMD, "CPUID: %s", target_name(target));
 
 	return ERROR_OK;
 }
diff --git a/src/target/oocd_trace.c b/src/target/oocd_trace.c
index 627366d..f38916a 100644
--- a/src/target/oocd_trace.c
+++ b/src/target/oocd_trace.c
@@ -277,7 +277,7 @@ COMMAND_HANDLER(handle_oocd_trace_config_command)
 	target = get_current_target(CMD_CTX);
 	arm = target_to_arm(target);
 	if (!is_arm(arm)) {
-		command_print(CMD_CTX, "current target isn't an ARM");
+		command_print(CMD, "current target isn't an ARM");
 		return ERROR_FAIL;
 	}
 
@@ -306,17 +306,17 @@ COMMAND_HANDLER(handle_oocd_trace_status_command)
 
 	arm = target_to_arm(target);
 	if (!is_arm(arm)) {
-		command_print(CMD_CTX, "current target isn't an ARM");
+		command_print(CMD, "current target isn't an ARM");
 		return ERROR_FAIL;
 	}
 
 	if (!arm->etm) {
-		command_print(CMD_CTX, "current target doesn't have an ETM configured");
+		command_print(CMD, "current target doesn't have an ETM configured");
 		return ERROR_FAIL;
 	}
 
 	if (strcmp(arm->etm->capture_driver->name, "oocd_trace") != 0) {
-		command_print(CMD_CTX, "current target's ETM capture driver isn't 'oocd_trace'");
+		command_print(CMD, "current target's ETM capture driver isn't 'oocd_trace'");
 		return ERROR_FAIL;
 	}
 
@@ -325,9 +325,9 @@ COMMAND_HANDLER(handle_oocd_trace_status_command)
 	oocd_trace_read_reg(oocd_trace, OOCD_TRACE_STATUS, &status);
 
 	if (status & 0x8)
-		command_print(CMD_CTX, "trace clock locked");
+		command_print(CMD, "trace clock locked");
 	else
-		command_print(CMD_CTX, "no trace clock");
+		command_print(CMD, "no trace clock");
 
 	return ERROR_OK;
 }
@@ -344,17 +344,17 @@ COMMAND_HANDLER(handle_oocd_trace_resync_command)
 
 	arm = target_to_arm(target);
 	if (!is_arm(arm)) {
-		command_print(CMD_CTX, "current target isn't an ARM");
+		command_print(CMD, "current target isn't an ARM");
 		return ERROR_FAIL;
 	}
 
 	if (!arm->etm) {
-		command_print(CMD_CTX, "current target doesn't have an ETM configured");
+		command_print(CMD, "current target doesn't have an ETM configured");
 		return ERROR_FAIL;
 	}
 
 	if (strcmp(arm->etm->capture_driver->name, "oocd_trace") != 0) {
-		command_print(CMD_CTX, "current target's ETM capture driver isn't 'oocd_trace'");
+		command_print(CMD, "current target's ETM capture driver isn't 'oocd_trace'");
 		return ERROR_FAIL;
 	}
 
@@ -366,7 +366,7 @@ COMMAND_HANDLER(handle_oocd_trace_resync_command)
 	if (bytes_written < 1)
 		return ERROR_FAIL;
 
-	command_print(CMD_CTX, "requesting traceclock resync");
+	command_print(CMD, "requesting traceclock resync");
 	LOG_DEBUG("resyncing traceclk pll");
 
 	return ERROR_OK;
diff --git a/src/target/openrisc/or1k.c b/src/target/openrisc/or1k.c
index 34b1b07..1e5db8c 100644
--- a/src/target/openrisc/or1k.c
+++ b/src/target/openrisc/or1k.c
@@ -1291,7 +1291,7 @@ COMMAND_HANDLER(or1k_tap_list_command_handler)
 
 	list_for_each_entry(or1k_tap, &tap_list, list) {
 		if (or1k_tap->name)
-			command_print(CMD_CTX, "%s", or1k_tap->name);
+			command_print(CMD, "%s", or1k_tap->name);
 	}
 
 	return ERROR_OK;
@@ -1339,7 +1339,7 @@ COMMAND_HANDLER(or1k_du_list_command_handler)
 
 	list_for_each_entry(or1k_du, &du_list, list) {
 		if (or1k_du->name)
-			command_print(CMD_CTX, "%s", or1k_du->name);
+			command_print(CMD, "%s", or1k_du->name);
 	}
 
 	return ERROR_OK;
@@ -1374,28 +1374,28 @@ COMMAND_HANDLER(or1k_addreg_command_handler)
 
 static const struct command_registration or1k_hw_ip_command_handlers[] = {
 	{
-		"tap_select",
+		.name = "tap_select",
 		.handler = or1k_tap_select_command_handler,
 		.mode = COMMAND_ANY,
 		.usage = "tap_select name",
 		.help = "Select the TAP core to use",
 	},
 	{
-		"tap_list",
+		.name = "tap_list",
 		.handler = or1k_tap_list_command_handler,
 		.mode = COMMAND_ANY,
 		.usage = "tap_list",
 		.help = "Display available TAP core",
 	},
 	{
-		"du_select",
+		.name = "du_select",
 		.handler = or1k_du_select_command_handler,
 		.mode = COMMAND_ANY,
 		.usage = "du_select name",
 		.help = "Select the Debug Unit core to use",
 	},
 	{
-		"du_list",
+		.name = "du_list",
 		.handler = or1k_du_list_command_handler,
 		.mode = COMMAND_ANY,
 		.usage = "select_tap name",
@@ -1406,7 +1406,7 @@ static const struct command_registration or1k_hw_ip_command_handlers[] = {
 
 static const struct command_registration or1k_reg_command_handlers[] = {
 	{
-		"addreg",
+		.name = "addreg",
 		.handler = or1k_addreg_command_handler,
 		.mode = COMMAND_ANY,
 		.usage = "addreg name addr feature group",
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 0c9b84c..6392774 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -455,16 +455,8 @@ static int riscv_init_target(struct command_context *cmd_ctx,
 	return ERROR_OK;
 }
 
-static void riscv_deinit_target(struct target *target)
+static void riscv_free_registers(struct target *target)
 {
-	LOG_DEBUG("riscv_deinit_target()");
-	struct target_type *tt = get_target_type(target);
-	if (tt) {
-		tt->deinit_target(target);
-		riscv_info_t *info = (riscv_info_t *) target->arch_info;
-		free(info->reg_names);
-		free(info);
-	}
 	/* Free the shared structure use for most registers. */
 	if (target->reg_cache) {
 		if (target->reg_cache->reg_list) {
@@ -477,6 +469,21 @@ static void riscv_deinit_target(struct target *target)
 		}
 		free(target->reg_cache);
 	}
+}
+
+static void riscv_deinit_target(struct target *target)
+{
+	LOG_DEBUG("riscv_deinit_target()");
+	struct target_type *tt = get_target_type(target);
+	if (tt) {
+		tt->deinit_target(target);
+		riscv_info_t *info = (riscv_info_t *) target->arch_info;
+		free(info->reg_names);
+		free(info);
+	}
+
+	riscv_free_registers(target);
+
 	target->arch_info = NULL;
 }
 
@@ -2046,7 +2053,7 @@ COMMAND_HANDLER(riscv_authdata_read)
 		uint32_t value;
 		if (r->authdata_read(target, &value) != ERROR_OK)
 			return ERROR_FAIL;
-		command_print(CMD_CTX, "0x%" PRIx32, value);
+		command_print(CMD, "0x%" PRIx32, value);
 		return ERROR_OK;
 	} else {
 		LOG_ERROR("authdata_read is not implemented for this target.");
@@ -2099,7 +2106,7 @@ COMMAND_HANDLER(riscv_dmi_read)
 		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
 		if (r->dmi_read(target, &value, address) != ERROR_OK)
 			return ERROR_FAIL;
-		command_print(CMD_CTX, "0x%" PRIx32, value);
+		command_print(CMD, "0x%" PRIx32, value);
 		return ERROR_OK;
 	} else {
 		LOG_ERROR("dmi_read is not implemented for this target.");
@@ -2402,28 +2409,28 @@ extern __COMMAND_HANDLER(handle_common_semihosting_cmdline);
  */
 static const struct command_registration arm_exec_command_handlers[] = {
 	{
-		"semihosting",
+		.name = "semihosting",
 		.handler = handle_common_semihosting_command,
 		.mode = COMMAND_EXEC,
 		.usage = "['enable'|'disable']",
 		.help = "activate support for semihosting operations",
 	},
 	{
-		"semihosting_cmdline",
+		.name = "semihosting_cmdline",
 		.handler = handle_common_semihosting_cmdline,
 		.mode = COMMAND_EXEC,
 		.usage = "arguments",
 		.help = "command line arguments to be passed to program",
 	},
 	{
-		"semihosting_fileio",
+		.name = "semihosting_fileio",
 		.handler = handle_common_semihosting_fileio_command,
 		.mode = COMMAND_EXEC,
 		.usage = "['enable'|'disable']",
 		.help = "activate support for semihosting fileio operations",
 	},
 	{
-		"semihosting_resexit",
+		.name = "semihosting_resexit",
 		.handler = handle_common_semihosting_resumable_exit_command,
 		.mode = COMMAND_EXEC,
 		.usage = "['enable'|'disable']",
@@ -3065,11 +3072,7 @@ int riscv_init_registers(struct target *target)
 {
 	RISCV_INFO(info);
 
-	if (target->reg_cache) {
-		if (target->reg_cache->reg_list)
-			free(target->reg_cache->reg_list);
-		free(target->reg_cache);
-	}
+	riscv_free_registers(target);
 
 	target->reg_cache = calloc(1, sizeof(*target->reg_cache));
 	target->reg_cache->name = "RISC-V Registers";
diff --git a/src/target/semihosting_common.c b/src/target/semihosting_common.c
index 5920789..ce6a791 100644
--- a/src/target/semihosting_common.c
+++ b/src/target/semihosting_common.c
@@ -1470,7 +1470,7 @@ __COMMAND_HANDLER(handle_common_semihosting_command)
 
 	struct semihosting *semihosting = target->semihosting;
 	if (!semihosting) {
-		command_print(CMD_CTX, "semihosting not supported for current target");
+		command_print(CMD, "semihosting not supported for current target");
 		return ERROR_FAIL;
 	}
 
@@ -1493,7 +1493,7 @@ __COMMAND_HANDLER(handle_common_semihosting_command)
 		semihosting->is_active = is_active;
 	}
 
-	command_print(CMD_CTX, "semihosting is %s",
+	command_print(CMD, "semihosting is %s",
 		semihosting->is_active
 		? "enabled" : "disabled");
 
@@ -1512,19 +1512,19 @@ __COMMAND_HANDLER(handle_common_semihosting_fileio_command)
 
 	struct semihosting *semihosting = target->semihosting;
 	if (!semihosting) {
-		command_print(CMD_CTX, "semihosting not supported for current target");
+		command_print(CMD, "semihosting not supported for current target");
 		return ERROR_FAIL;
 	}
 
 	if (!semihosting->is_active) {
-		command_print(CMD_CTX, "semihosting not yet enabled for current target");
+		command_print(CMD, "semihosting not yet enabled for current target");
 		return ERROR_FAIL;
 	}
 
 	if (CMD_ARGC > 0)
 		COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting->is_fileio);
 
-	command_print(CMD_CTX, "semihosting fileio is %s",
+	command_print(CMD, "semihosting fileio is %s",
 		semihosting->is_fileio
 		? "enabled" : "disabled");
 
@@ -1543,7 +1543,7 @@ __COMMAND_HANDLER(handle_common_semihosting_cmdline)
 
 	struct semihosting *semihosting = target->semihosting;
 	if (!semihosting) {
-		command_print(CMD_CTX, "semihosting not supported for current target");
+		command_print(CMD, "semihosting not supported for current target");
 		return ERROR_FAIL;
 	}
 
@@ -1558,7 +1558,7 @@ __COMMAND_HANDLER(handle_common_semihosting_cmdline)
 		semihosting->cmdline = cmdline;
 	}
 
-	command_print(CMD_CTX, "semihosting command line is [%s]",
+	command_print(CMD, "semihosting command line is [%s]",
 		semihosting->cmdline);
 
 	return ERROR_OK;
@@ -1575,19 +1575,19 @@ __COMMAND_HANDLER(handle_common_semihosting_resumable_exit_command)
 
 	struct semihosting *semihosting = target->semihosting;
 	if (!semihosting) {
-		command_print(CMD_CTX, "semihosting not supported for current target");
+		command_print(CMD, "semihosting not supported for current target");
 		return ERROR_FAIL;
 	}
 
 	if (!semihosting->is_active) {
-		command_print(CMD_CTX, "semihosting not yet enabled for current target");
+		command_print(CMD, "semihosting not yet enabled for current target");
 		return ERROR_FAIL;
 	}
 
 	if (CMD_ARGC > 0)
 		COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting->has_resumable_exit);
 
-	command_print(CMD_CTX, "semihosting resumable exit is %s",
+	command_print(CMD, "semihosting resumable exit is %s",
 		semihosting->has_resumable_exit
 		? "enabled" : "disabled");
 
diff --git a/src/target/smp.c b/src/target/smp.c
index f42d8ab..acd4628 100644
--- a/src/target/smp.c
+++ b/src/target/smp.c
@@ -106,7 +106,7 @@ COMMAND_HANDLER(default_handle_smp_command)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
 	if (!CMD_ARGC) {
-		command_print(CMD_CTX, "%s", target->smp ? "on" : "off");
+		command_print(CMD, "%s", target->smp ? "on" : "off");
 		return ERROR_OK;
 	}
 
@@ -166,7 +166,7 @@ COMMAND_HANDLER(handle_smp_gdb_command)
 			target->gdb_service->core[1] = coreid;
 
 		}
-		command_print(CMD_CTX, "gdb coreid  %" PRId32 " -> %" PRId32, target->gdb_service->core[0]
+		command_print(CMD, "gdb coreid  %" PRId32 " -> %" PRId32, target->gdb_service->core[0]
 			, target->gdb_service->core[1]);
 	}
 	return ERROR_OK;
diff --git a/src/target/stm8.c b/src/target/stm8.c
index b62ff13..fcfc170 100644
--- a/src/target/stm8.c
+++ b/src/target/stm8.c
@@ -2147,7 +2147,7 @@ COMMAND_HANDLER(stm8_handle_enable_step_irq_command)
 		stm8->enable_step_irq = enable;
 	}
 	msg = stm8->enable_step_irq ? "enabled" : "disabled";
-	command_print(CMD_CTX, "enable_step_irq = %s", msg);
+	command_print(CMD, "enable_step_irq = %s", msg);
 	return ERROR_OK;
 }
 
@@ -2163,7 +2163,7 @@ COMMAND_HANDLER(stm8_handle_enable_stm8l_command)
 		stm8->enable_stm8l = enable;
 	}
 	msg = stm8->enable_stm8l ? "enabled" : "disabled";
-	command_print(CMD_CTX, "enable_stm8l = %s", msg);
+	command_print(CMD, "enable_stm8l = %s", msg);
 	stm8_init_flash_regs(stm8->enable_stm8l, stm8);
 	return ERROR_OK;
 }
diff --git a/src/target/target.c b/src/target/target.c
index 36e63f9..cec46cc 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -375,12 +375,6 @@ uint16_t target_buffer_get_u16(struct target *target, const uint8_t *buffer)
 		return be_to_h_u16(buffer);
 }
 
-/* read a uint8_t from a buffer in target memory endianness */
-static uint8_t target_buffer_get_u8(struct target *target, const uint8_t *buffer)
-{
-	return *buffer & 0x0ff;
-}
-
 /* write a uint64_t to a buffer in target memory endianness */
 void target_buffer_set_u64(struct target *target, uint8_t *buffer, uint64_t value)
 {
@@ -640,7 +634,7 @@ int target_resume(struct target *target, int current, target_addr_t address,
 	return retval;
 }
 
-static int target_process_reset(struct command_context *cmd_ctx, enum target_reset_mode reset_mode)
+static int target_process_reset(struct command_invocation *cmd, enum target_reset_mode reset_mode)
 {
 	char buf[100];
 	int retval;
@@ -664,13 +658,13 @@ static int target_process_reset(struct command_context *cmd_ctx, enum target_res
 	jtag_poll_set_enabled(false);
 
 	sprintf(buf, "ocd_process_reset %s", n->name);
-	retval = Jim_Eval(cmd_ctx->interp, buf);
+	retval = Jim_Eval(cmd->ctx->interp, buf);
 
 	jtag_poll_set_enabled(save_poll);
 
 	if (retval != JIM_OK) {
-		Jim_MakeErrorMessage(cmd_ctx->interp);
-		command_print(NULL, "%s\n", Jim_GetString(Jim_GetResult(cmd_ctx->interp), NULL));
+		Jim_MakeErrorMessage(cmd->ctx->interp);
+		command_print(cmd, "%s", Jim_GetString(Jim_GetResult(cmd->ctx->interp), NULL));
 		return ERROR_FAIL;
 	}
 
@@ -1221,7 +1215,24 @@ int target_get_gdb_reg_list(struct target *target,
 		struct reg **reg_list[], int *reg_list_size,
 		enum target_register_class reg_class)
 {
-	return target->type->get_gdb_reg_list(target, reg_list, reg_list_size, reg_class);
+	int result = target->type->get_gdb_reg_list(target, reg_list,
+			reg_list_size, reg_class);
+	if (result != ERROR_OK) {
+		*reg_list = NULL;
+		*reg_list_size = 0;
+	}
+	return result;
+}
+
+int target_get_gdb_reg_list_noread(struct target *target,
+		struct reg **reg_list[], int *reg_list_size,
+		enum target_register_class reg_class)
+{
+	if (target->type->get_gdb_reg_list_noread &&
+			target->type->get_gdb_reg_list_noread(target, reg_list,
+				reg_list_size, reg_class) == ERROR_OK)
+		return ERROR_OK;
+	return target_get_gdb_reg_list(target, reg_list, reg_list_size, reg_class);
 }
 
 int target_get_gdb_reg_list_noread(struct target *target,
@@ -1604,9 +1615,9 @@ int target_call_event_callbacks(struct target *target, enum target_event event)
 		target_call_event_callbacks(target, TARGET_EVENT_GDB_HALT);
 	}
 
-	LOG_DEBUG("target event %i (%s) for core %d", event,
+	LOG_DEBUG("target event %i (%s) for core %s", event,
 			Jim_Nvp_value2name_simple(nvp_target_event, event)->name,
-			target->coreid);
+			target_name(target));
 
 	target_handle_event(target, event);
 
@@ -2590,23 +2601,23 @@ int target_write_phys_u8(struct target *target, target_addr_t address, uint8_t v
 	return retval;
 }
 
-static int find_target(struct command_context *cmd_ctx, const char *name)
+static int find_target(struct command_invocation *cmd, const char *name)
 {
 	struct target *target = get_target(name);
 	if (target == NULL) {
-		LOG_ERROR("Target: %s is unknown, try one of:\n", name);
+		command_print(cmd, "Target: %s is unknown, try one of:\n", name);
 		return ERROR_FAIL;
 	}
 	if (!target->tap->enabled) {
-		LOG_USER("Target: TAP %s is disabled, "
+		command_print(cmd, "Target: TAP %s is disabled, "
 			 "can't be the current target\n",
 			 target->tap->dotted_name);
 		return ERROR_FAIL;
 	}
 
-	cmd_ctx->current_target = target;
-	if (cmd_ctx->current_target_override)
-		cmd_ctx->current_target_override = target;
+	cmd->ctx->current_target = target;
+	if (cmd->ctx->current_target_override)
+		cmd->ctx->current_target_override = target;
 
 	return ERROR_OK;
 }
@@ -2616,7 +2627,7 @@ COMMAND_HANDLER(handle_targets_command)
 {
 	int retval = ERROR_OK;
 	if (CMD_ARGC == 1) {
-		retval = find_target(CMD_CTX, CMD_ARGV[0]);
+		retval = find_target(CMD, CMD_ARGV[0]);
 		if (retval == ERROR_OK) {
 			/* we're done! */
 			return retval;
@@ -2624,8 +2635,8 @@ COMMAND_HANDLER(handle_targets_command)
 	}
 
 	struct target *target = all_targets;
-	command_print(CMD_CTX, "    TargetName         Type       Endian TapName            State       ");
-	command_print(CMD_CTX, "--  ------------------ ---------- ------ ------------------ ------------");
+	command_print(CMD, "    TargetName         Type       Endian TapName            State       ");
+	command_print(CMD, "--  ------------------ ---------- ------ ------------------ ------------");
 	while (target) {
 		const char *state;
 		char marker = ' ';
@@ -2639,7 +2650,7 @@ COMMAND_HANDLER(handle_targets_command)
 			marker = '*';
 
 		/* keep columns lined up to match the headers above */
-		command_print(CMD_CTX,
+		command_print(CMD,
 				"%2d%c %-18s %-10s %-6s %-18s %s",
 				target->target_number,
 				marker,
@@ -2850,7 +2861,7 @@ COMMAND_HANDLER(handle_reg_command)
 		while (cache) {
 			unsigned i;
 
-			command_print(CMD_CTX, "===== %s", cache->name);
+			command_print(CMD, "===== %s", cache->name);
 
 			for (i = 0, reg = cache->reg_list;
 					i < cache->num_regs;
@@ -2904,7 +2915,7 @@ COMMAND_HANDLER(handle_reg_command)
 		}
 
 		if (!reg) {
-			command_print(CMD_CTX, "%i is out of bounds, the current target "
+			command_print(CMD, "%i is out of bounds, the current target "
 					"has only %i registers (0 - %i)", num, count, count - 1);
 			return ERROR_OK;
 		}
@@ -2935,7 +2946,7 @@ COMMAND_HANDLER(handle_reg_command)
 			}
 		}
 		value = buf_to_str(reg->value, reg->size, 16);
-		command_print(CMD_CTX, "%s (/%i): 0x%s", reg->name, (int)(reg->size), value);
+		command_print(CMD, "%s (/%i): 0x%s", reg->name, (int)(reg->size), value);
 		free(value);
 		return ERROR_OK;
 	}
@@ -2955,7 +2966,7 @@ COMMAND_HANDLER(handle_reg_command)
 		}
 
 		value = buf_to_str(reg->value, reg->size, 16);
-		command_print(CMD_CTX, "%s (/%i): 0x%s", reg->name, (int)(reg->size), value);
+		command_print(CMD, "%s (/%i): 0x%s", reg->name, (int)(reg->size), value);
 		free(value);
 
 		free(buf);
@@ -2966,7 +2977,7 @@ COMMAND_HANDLER(handle_reg_command)
 	return ERROR_COMMAND_SYNTAX_ERROR;
 
 not_found:
-	command_print(CMD_CTX, "register %s not found in current target", CMD_ARGV[0]);
+	command_print(CMD, "register %s not found in current target", CMD_ARGV[0]);
 	return ERROR_OK;
 }
 
@@ -2976,9 +2987,9 @@ COMMAND_HANDLER(handle_poll_command)
 	struct target *target = get_current_target(CMD_CTX);
 
 	if (CMD_ARGC == 0) {
-		command_print(CMD_CTX, "background polling: %s",
+		command_print(CMD, "background polling: %s",
 				jtag_poll_get_enabled() ? "on" : "off");
-		command_print(CMD_CTX, "TAP: %s (%s)",
+		command_print(CMD, "TAP: %s (%s)",
 				target->tap->dotted_name,
 				target->tap->enabled ? "enabled" : "disabled");
 		if (!target->tap->enabled)
@@ -3104,7 +3115,7 @@ COMMAND_HANDLER(handle_reset_command)
 	}
 
 	/* reset *all* targets */
-	return target_process_reset(CMD_CTX, reset_mode);
+	return target_process_reset(CMD, reset_mode);
 }
 
 
@@ -3150,7 +3161,7 @@ COMMAND_HANDLER(handle_step_command)
 	return target->type->step(target, current_pc, addr, 1);
 }
 
-static void handle_md_output(struct command_context *cmd_ctx,
+void target_handle_md_output(struct command_invocation *cmd,
 		struct target *target, target_addr_t address, unsigned size,
 		unsigned count, const uint8_t *buffer)
 {
@@ -3208,7 +3219,7 @@ static void handle_md_output(struct command_context *cmd_ctx,
 				value_fmt, value);
 
 		if ((i % line_modulo == line_modulo - 1) || (i == count - 1)) {
-			command_print(cmd_ctx, "%s", output);
+			command_print(cmd, "%s", output);
 			output_len = 0;
 		}
 	}
@@ -3265,7 +3276,7 @@ COMMAND_HANDLER(handle_md_command)
 	struct target *target = get_current_target(CMD_CTX);
 	int retval = fn(target, address, size, count, buffer);
 	if (ERROR_OK == retval)
-		handle_md_output(CMD_CTX, target, address, size, count, buffer);
+		target_handle_md_output(CMD, target, address, size, count, buffer);
 
 	free(buffer);
 
@@ -3438,7 +3449,7 @@ COMMAND_HANDLER(handle_load_image_command)
 	for (i = 0; i < image.num_sections; i++) {
 		buffer = malloc(image.sections[i].size);
 		if (buffer == NULL) {
-			command_print(CMD_CTX,
+			command_print(CMD,
 						  "error allocating buffer for section (%d bytes)",
 						  (int)(image.sections[i].size));
 			retval = ERROR_FAIL;
@@ -3475,7 +3486,7 @@ COMMAND_HANDLER(handle_load_image_command)
 				break;
 			}
 			image_size += length;
-			command_print(CMD_CTX, "%u bytes written at address " TARGET_ADDR_FMT "",
+			command_print(CMD, "%u bytes written at address " TARGET_ADDR_FMT "",
 					(unsigned int)length,
 					image.sections[i].base_address + offset);
 		}
@@ -3484,7 +3495,7 @@ COMMAND_HANDLER(handle_load_image_command)
 	}
 
 	if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) {
-		command_print(CMD_CTX, "downloaded %" PRIu32 " bytes "
+		command_print(CMD, "downloaded %" PRIu32 " bytes "
 				"in %fs (%0.3f KiB/s)", image_size,
 				duration_elapsed(&bench), duration_kbps(&bench, image_size));
 	}
@@ -3545,7 +3556,7 @@ COMMAND_HANDLER(handle_dump_image_command)
 		retval = fileio_size(fileio, &filesize);
 		if (retval != ERROR_OK)
 			return retval;
-		command_print(CMD_CTX,
+		command_print(CMD,
 				"dumped %zu bytes in %fs (%0.3f KiB/s)", filesize,
 				duration_elapsed(&bench), duration_kbps(&bench, filesize));
 	}
@@ -3610,7 +3621,7 @@ static COMMAND_HELPER(handle_verify_image_command_internal, enum verify_mode ver
 	for (i = 0; i < image.num_sections; i++) {
 		buffer = malloc(image.sections[i].size);
 		if (buffer == NULL) {
-			command_print(CMD_CTX,
+			command_print(CMD,
 					"error allocating buffer for section (%d bytes)",
 					(int)(image.sections[i].size));
 			break;
@@ -3661,14 +3672,14 @@ static COMMAND_HELPER(handle_verify_image_command_internal, enum verify_mode ver
 					uint32_t t;
 					for (t = 0; t < buf_cnt; t++) {
 						if (data[t] != buffer[t]) {
-							command_print(CMD_CTX,
+							command_print(CMD,
 										  "diff %d address 0x%08x. Was 0x%02x instead of 0x%02x",
 										  diffs,
 										  (unsigned)(t + image.sections[i].base_address),
 										  data[t],
 										  buffer[t]);
 							if (diffs++ >= 127) {
-								command_print(CMD_CTX, "More than 128 errors, the rest are not printed.");
+								command_print(CMD, "More than 128 errors, the rest are not printed.");
 								free(data);
 								free(buffer);
 								goto done;
@@ -3680,7 +3691,7 @@ static COMMAND_HELPER(handle_verify_image_command_internal, enum verify_mode ver
 				free(data);
 			}
 		} else {
-			command_print(CMD_CTX, "address " TARGET_ADDR_FMT " length 0x%08zx",
+			command_print(CMD, "address " TARGET_ADDR_FMT " length 0x%08zx",
 						  image.sections[i].base_address,
 						  buf_cnt);
 		}
@@ -3689,12 +3700,12 @@ static COMMAND_HELPER(handle_verify_image_command_internal, enum verify_mode ver
 		image_size += buf_cnt;
 	}
 	if (diffs > 0)
-		command_print(CMD_CTX, "No more differences found.");
+		command_print(CMD, "No more differences found.");
 done:
 	if (diffs > 0)
 		retval = ERROR_FAIL;
 	if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) {
-		command_print(CMD_CTX, "verified %" PRIu32 " bytes "
+		command_print(CMD, "verified %" PRIu32 " bytes "
 				"in %fs (%0.3f KiB/s)", image_size,
 				duration_elapsed(&bench), duration_kbps(&bench, image_size));
 	}
@@ -3719,32 +3730,32 @@ COMMAND_HANDLER(handle_test_image_command)
 	return CALL_COMMAND_HANDLER(handle_verify_image_command_internal, IMAGE_TEST);
 }
 
-static int handle_bp_command_list(struct command_context *cmd_ctx)
+static int handle_bp_command_list(struct command_invocation *cmd)
 {
-	struct target *target = get_current_target(cmd_ctx);
+	struct target *target = get_current_target(cmd->ctx);
 	struct breakpoint *breakpoint = target->breakpoints;
 	while (breakpoint) {
 		if (breakpoint->type == BKPT_SOFT) {
 			char *buf = buf_to_str(breakpoint->orig_instr,
 					breakpoint->length, 16);
-			command_print(cmd_ctx, "IVA breakpoint: " TARGET_ADDR_FMT ", 0x%x, %i, 0x%s",
+			command_print(cmd, "IVA breakpoint: " TARGET_ADDR_FMT ", 0x%x, %i, 0x%s",
 					breakpoint->address,
 					breakpoint->length,
 					breakpoint->set, buf);
 			free(buf);
 		} else {
 			if ((breakpoint->address == 0) && (breakpoint->asid != 0))
-				command_print(cmd_ctx, "Context breakpoint: 0x%8.8" PRIx32 ", 0x%x, %i",
+				command_print(cmd, "Context breakpoint: 0x%8.8" PRIx32 ", 0x%x, %i",
 							breakpoint->asid,
 							breakpoint->length, breakpoint->set);
 			else if ((breakpoint->address != 0) && (breakpoint->asid != 0)) {
-				command_print(cmd_ctx, "Hybrid breakpoint(IVA): " TARGET_ADDR_FMT ", 0x%x, %i",
+				command_print(cmd, "Hybrid breakpoint(IVA): " TARGET_ADDR_FMT ", 0x%x, %i",
 							breakpoint->address,
 							breakpoint->length, breakpoint->set);
-				command_print(cmd_ctx, "\t|--->linked with ContextID: 0x%8.8" PRIx32,
+				command_print(cmd, "\t|--->linked with ContextID: 0x%8.8" PRIx32,
 							breakpoint->asid);
 			} else
-				command_print(cmd_ctx, "Breakpoint(IVA): " TARGET_ADDR_FMT ", 0x%x, %i",
+				command_print(cmd, "Breakpoint(IVA): " TARGET_ADDR_FMT ", 0x%x, %i",
 							breakpoint->address,
 							breakpoint->length, breakpoint->set);
 		}
@@ -3754,17 +3765,17 @@ static int handle_bp_command_list(struct command_context *cmd_ctx)
 	return ERROR_OK;
 }
 
-static int handle_bp_command_set(struct command_context *cmd_ctx,
+static int handle_bp_command_set(struct command_invocation *cmd,
 		target_addr_t addr, uint32_t asid, uint32_t length, int hw)
 {
-	struct target *target = get_current_target(cmd_ctx);
+	struct target *target = get_current_target(cmd->ctx);
 	int retval;
 
 	if (asid == 0) {
 		retval = breakpoint_add(target, addr, length, hw);
 		/* error is always logged in breakpoint_add(), do not print it again */
 		if (ERROR_OK == retval)
-			command_print(cmd_ctx, "breakpoint set at " TARGET_ADDR_FMT "", addr);
+			command_print(cmd, "breakpoint set at " TARGET_ADDR_FMT "", addr);
 
 	} else if (addr == 0) {
 		if (target->type->add_context_breakpoint == NULL) {
@@ -3774,7 +3785,7 @@ static int handle_bp_command_set(struct command_context *cmd_ctx,
 		retval = context_breakpoint_add(target, asid, length, hw);
 		/* error is always logged in context_breakpoint_add(), do not print it again */
 		if (ERROR_OK == retval)
-			command_print(cmd_ctx, "Context breakpoint set at 0x%8.8" PRIx32 "", asid);
+			command_print(cmd, "Context breakpoint set at 0x%8.8" PRIx32 "", asid);
 
 	} else {
 		if (target->type->add_hybrid_breakpoint == NULL) {
@@ -3784,7 +3795,7 @@ static int handle_bp_command_set(struct command_context *cmd_ctx,
 		retval = hybrid_breakpoint_add(target, addr, asid, length, hw);
 		/* error is always logged in hybrid_breakpoint_add(), do not print it again */
 		if (ERROR_OK == retval)
-			command_print(cmd_ctx, "Hybrid breakpoint set at 0x%8.8" PRIx32 "", asid);
+			command_print(cmd, "Hybrid breakpoint set at 0x%8.8" PRIx32 "", asid);
 	}
 	return retval;
 }
@@ -3798,13 +3809,13 @@ COMMAND_HANDLER(handle_bp_command)
 
 	switch (CMD_ARGC) {
 		case 0:
-			return handle_bp_command_list(CMD_CTX);
+			return handle_bp_command_list(CMD);
 
 		case 2:
 			asid = 0;
 			COMMAND_PARSE_ADDRESS(CMD_ARGV[0], addr);
 			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length);
-			return handle_bp_command_set(CMD_CTX, addr, asid, length, hw);
+			return handle_bp_command_set(CMD, addr, asid, length, hw);
 
 		case 3:
 			if (strcmp(CMD_ARGV[2], "hw") == 0) {
@@ -3812,13 +3823,13 @@ COMMAND_HANDLER(handle_bp_command)
 				COMMAND_PARSE_ADDRESS(CMD_ARGV[0], addr);
 				COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length);
 				asid = 0;
-				return handle_bp_command_set(CMD_CTX, addr, asid, length, hw);
+				return handle_bp_command_set(CMD, addr, asid, length, hw);
 			} else if (strcmp(CMD_ARGV[2], "hw_ctx") == 0) {
 				hw = BKPT_HARD;
 				COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], asid);
 				COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length);
 				addr = 0;
-				return handle_bp_command_set(CMD_CTX, addr, asid, length, hw);
+				return handle_bp_command_set(CMD, addr, asid, length, hw);
 			}
 			/* fallthrough */
 		case 4:
@@ -3826,7 +3837,7 @@ COMMAND_HANDLER(handle_bp_command)
 			COMMAND_PARSE_ADDRESS(CMD_ARGV[0], addr);
 			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], asid);
 			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], length);
-			return handle_bp_command_set(CMD_CTX, addr, asid, length, hw);
+			return handle_bp_command_set(CMD, addr, asid, length, hw);
 
 		default:
 			return ERROR_COMMAND_SYNTAX_ERROR;
@@ -3855,7 +3866,7 @@ COMMAND_HANDLER(handle_wp_command)
 		struct watchpoint *watchpoint = target->watchpoints;
 
 		while (watchpoint) {
-			command_print(CMD_CTX, "address: " TARGET_ADDR_FMT
+			command_print(CMD, "address: " TARGET_ADDR_FMT
 					", len: 0x%8.8" PRIx32
 					", r/w/a: %i, value: 0x%8.8" PRIx32
 					", mask: 0x%8.8" PRIx32,
@@ -3947,7 +3958,7 @@ COMMAND_HANDLER(handle_virt2phys_command)
 	struct target *target = get_current_target(CMD_CTX);
 	int retval = target->type->virt2phys(target, va, &pa);
 	if (retval == ERROR_OK)
-		command_print(CMD_CTX, "Physical address " TARGET_ADDR_FMT "", pa);
+		command_print(CMD, "Physical address " TARGET_ADDR_FMT "", pa);
 
 	return retval;
 }
@@ -4140,7 +4151,7 @@ COMMAND_HANDLER(handle_profile_command)
 
 	write_gmon(samples, num_of_samples, CMD_ARGV[1],
 		   with_range, start_address, end_address, target, duration_ms);
-	command_print(CMD_CTX, "Wrote %s", CMD_ARGV[1]);
+	command_print(CMD, "Wrote %s", CMD_ARGV[1]);
 
 	free(samples);
 	return retval;
@@ -4557,6 +4568,7 @@ static int target_array2mem(Jim_Interp *interp, struct target *target,
 void target_handle_event(struct target *target, enum target_event e)
 {
 	struct target_event_action *teap;
+	int retval;
 
 	for (teap = target->event_action; teap != NULL; teap = teap->next) {
 		if (teap->event == e) {
@@ -4575,10 +4587,19 @@ void target_handle_event(struct target *target, enum target_event e)
 			struct command_context *cmd_ctx = current_command_context(teap->interp);
 			struct target *saved_target_override = cmd_ctx->current_target_override;
 			cmd_ctx->current_target_override = target;
+			retval = Jim_EvalObj(teap->interp, teap->body);
 
-			if (Jim_EvalObj(teap->interp, teap->body) != JIM_OK) {
+			if (retval == JIM_RETURN)
+				retval = teap->interp->returnCode;
+
+			if (retval != JIM_OK) {
 				Jim_MakeErrorMessage(teap->interp);
-				command_print(NULL, "%s\n", Jim_GetString(Jim_GetResult(teap->interp), NULL));
+				LOG_USER("Error executing event %s on target %s:\n%s",
+						  Jim_Nvp_value2name_simple(nvp_target_event, e)->name,
+						  target_name(target),
+						  Jim_GetString(Jim_GetResult(teap->interp), NULL));
+				/* clean both error code and stacktrace before return */
+				Jim_Eval(teap->interp, "error \"\" \"\"");
 			}
 
 			cmd_ctx->current_target_override = saved_target_override;
@@ -4856,7 +4877,7 @@ no_params:
 				if (goi->argc != 0)
 					goto no_params;
 			}
-			Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, target->working_area_size));
+			Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, target->coreid));
 			/* loop for more */
 			break;
 
@@ -4919,6 +4940,12 @@ no_params:
 
 		case TCFG_GDB_PORT:
 			if (goi->isconfigure) {
+				struct command_context *cmd_ctx = current_command_context(goi->interp);
+				if (cmd_ctx->mode != COMMAND_CONFIG) {
+					Jim_SetResultString(goi->interp, "-gdb-port must be configured before 'init'", -1);
+					return JIM_ERR;
+				}
+
 				const char *s;
 				e = Jim_GetOpt_String(goi, &s, NULL);
 				if (e != JIM_OK)
@@ -4954,228 +4981,6 @@ static int jim_target_configure(Jim_Interp *interp, int argc, Jim_Obj * const *a
 	return target_configure(&goi, target);
 }
 
-static int jim_target_mw(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
-{
-	const char *cmd_name = Jim_GetString(argv[0], NULL);
-
-	Jim_GetOptInfo goi;
-	Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1);
-
-	if (goi.argc < 2 || goi.argc > 4) {
-		Jim_SetResultFormatted(goi.interp,
-				"usage: %s [phys] <address> <data> [<count>]", cmd_name);
-		return JIM_ERR;
-	}
-
-	target_write_fn fn;
-	fn = target_write_memory;
-
-	int e;
-	if (strcmp(Jim_GetString(argv[1], NULL), "phys") == 0) {
-		/* consume it */
-		struct Jim_Obj *obj;
-		e = Jim_GetOpt_Obj(&goi, &obj);
-		if (e != JIM_OK)
-			return e;
-
-		fn = target_write_phys_memory;
-	}
-
-	jim_wide a;
-	e = Jim_GetOpt_Wide(&goi, &a);
-	if (e != JIM_OK)
-		return e;
-
-	jim_wide b;
-	e = Jim_GetOpt_Wide(&goi, &b);
-	if (e != JIM_OK)
-		return e;
-
-	jim_wide c = 1;
-	if (goi.argc == 1) {
-		e = Jim_GetOpt_Wide(&goi, &c);
-		if (e != JIM_OK)
-			return e;
-	}
-
-	/* all args must be consumed */
-	if (goi.argc != 0)
-		return JIM_ERR;
-
-	struct target *target = Jim_CmdPrivData(goi.interp);
-	unsigned data_size;
-	if (strcasecmp(cmd_name, "mww") == 0)
-		data_size = 4;
-	else if (strcasecmp(cmd_name, "mwh") == 0)
-		data_size = 2;
-	else if (strcasecmp(cmd_name, "mwb") == 0)
-		data_size = 1;
-	else {
-		LOG_ERROR("command '%s' unknown: ", cmd_name);
-		return JIM_ERR;
-	}
-
-	return (target_fill_mem(target, a, fn, data_size, b, c) == ERROR_OK) ? JIM_OK : JIM_ERR;
-}
-
-/**
-*  @brief Reads an array of words/halfwords/bytes from target memory starting at specified address.
-*
-*  Usage: mdw [phys] <address> [<count>] - for 32 bit reads
-*         mdh [phys] <address> [<count>] - for 16 bit reads
-*         mdb [phys] <address> [<count>] - for  8 bit reads
-*
-*  Count defaults to 1.
-*
-*  Calls target_read_memory or target_read_phys_memory depending on
-*  the presence of the "phys" argument
-*  Reads the target memory in blocks of max. 32 bytes, and returns an array of ints formatted
-*  to int representation in base16.
-*  Also outputs read data in a human readable form using command_print
-*
-*  @param phys if present target_read_phys_memory will be used instead of target_read_memory
-*  @param address address where to start the read. May be specified in decimal or hex using the standard "0x" prefix
-*  @param count optional count parameter to read an array of values. If not specified, defaults to 1.
-*  @returns:  JIM_ERR on error or JIM_OK on success and sets the result string to an array of ascii formatted numbers
-*  on success, with [<count>] number of elements.
-*
-*  In case of little endian target:
-*      Example1: "mdw 0x00000000"  returns "10123456"
-*      Exmaple2: "mdh 0x00000000 1" returns "3456"
-*      Example3: "mdb 0x00000000" returns "56"
-*      Example4: "mdh 0x00000000 2" returns "3456 1012"
-*      Example5: "mdb 0x00000000 3" returns "56 34 12"
-**/
-static int jim_target_md(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
-{
-	const char *cmd_name = Jim_GetString(argv[0], NULL);
-
-	Jim_GetOptInfo goi;
-	Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1);
-
-	if ((goi.argc < 1) || (goi.argc > 3)) {
-		Jim_SetResultFormatted(goi.interp,
-				"usage: %s [phys] <address> [<count>]", cmd_name);
-		return JIM_ERR;
-	}
-
-	int (*fn)(struct target *target,
-			target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-	fn = target_read_memory;
-
-	int e;
-	if (strcmp(Jim_GetString(argv[1], NULL), "phys") == 0) {
-		/* consume it */
-		struct Jim_Obj *obj;
-		e = Jim_GetOpt_Obj(&goi, &obj);
-		if (e != JIM_OK)
-			return e;
-
-		fn = target_read_phys_memory;
-	}
-
-	/* Read address parameter */
-	jim_wide addr;
-	e = Jim_GetOpt_Wide(&goi, &addr);
-	if (e != JIM_OK)
-		return JIM_ERR;
-
-	/* If next parameter exists, read it out as the count parameter, if not, set it to 1 (default) */
-	jim_wide count;
-	if (goi.argc == 1) {
-		e = Jim_GetOpt_Wide(&goi, &count);
-		if (e != JIM_OK)
-			return JIM_ERR;
-	} else
-		count = 1;
-
-	/* all args must be consumed */
-	if (goi.argc != 0)
-		return JIM_ERR;
-
-	jim_wide dwidth = 1; /* shut up gcc */
-	if (strcasecmp(cmd_name, "mdw") == 0)
-		dwidth = 4;
-	else if (strcasecmp(cmd_name, "mdh") == 0)
-		dwidth = 2;
-	else if (strcasecmp(cmd_name, "mdb") == 0)
-		dwidth = 1;
-	else {
-		LOG_ERROR("command '%s' unknown: ", cmd_name);
-		return JIM_ERR;
-	}
-
-	/* convert count to "bytes" */
-	int bytes = count * dwidth;
-
-	struct target *target = Jim_CmdPrivData(goi.interp);
-	uint8_t  target_buf[32];
-	jim_wide x, y, z;
-	while (bytes > 0) {
-		y = (bytes < 16) ? bytes : 16; /* y = min(bytes, 16); */
-
-		/* Try to read out next block */
-		e = fn(target, addr, dwidth, y / dwidth, target_buf);
-
-		if (e != ERROR_OK) {
-			Jim_SetResultFormatted(interp, "error reading target @ 0x%08lx", (long)addr);
-			return JIM_ERR;
-		}
-
-		command_print_sameline(NULL, "0x%08x ", (int)(addr));
-		switch (dwidth) {
-		case 4:
-			for (x = 0; x < 16 && x < y; x += 4) {
-				z = target_buffer_get_u32(target, &(target_buf[x]));
-				command_print_sameline(NULL, "%08x ", (int)(z));
-			}
-			for (; (x < 16) ; x += 4)
-				command_print_sameline(NULL, "         ");
-			break;
-		case 2:
-			for (x = 0; x < 16 && x < y; x += 2) {
-				z = target_buffer_get_u16(target, &(target_buf[x]));
-				command_print_sameline(NULL, "%04x ", (int)(z));
-			}
-			for (; (x < 16) ; x += 2)
-				command_print_sameline(NULL, "     ");
-			break;
-		case 1:
-		default:
-			for (x = 0 ; (x < 16) && (x < y) ; x += 1) {
-				z = target_buffer_get_u8(target, &(target_buf[x]));
-				command_print_sameline(NULL, "%02x ", (int)(z));
-			}
-			for (; (x < 16) ; x += 1)
-				command_print_sameline(NULL, "   ");
-			break;
-		}
-		/* ascii-ify the bytes */
-		for (x = 0 ; x < y ; x++) {
-			if ((target_buf[x] >= 0x20) &&
-				(target_buf[x] <= 0x7e)) {
-				/* good */
-			} else {
-				/* smack it */
-				target_buf[x] = '.';
-			}
-		}
-		/* space pad  */
-		while (x < 16) {
-			target_buf[x] = ' ';
-			x++;
-		}
-		/* terminate */
-		target_buf[16] = 0;
-		/* print - with a newline */
-		command_print_sameline(NULL, "%s\n", target_buf);
-		/* NEXT... */
-		bytes -= 16;
-		addr += 16;
-	}
-	return JIM_OK;
-}
-
 static int jim_target_mem2array(Jim_Interp *interp,
 		int argc, Jim_Obj *const *argv)
 {
@@ -5389,27 +5194,25 @@ static int jim_target_wait_state(Jim_Interp *interp, int argc, Jim_Obj *const *a
 /* List for human, Events defined for this target.
  * scripts/programs should use 'name cget -event NAME'
  */
-static int jim_target_event_list(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
+COMMAND_HANDLER(handle_target_event_list)
 {
-	struct command_context *cmd_ctx = current_command_context(interp);
-	assert(cmd_ctx != NULL);
-
-	struct target *target = Jim_CmdPrivData(interp);
+	struct target *target = get_current_target(CMD_CTX);
 	struct target_event_action *teap = target->event_action;
-	command_print(cmd_ctx, "Event actions for target (%d) %s\n",
+
+	command_print(CMD, "Event actions for target (%d) %s\n",
 				   target->target_number,
 				   target_name(target));
-	command_print(cmd_ctx, "%-25s | Body", "Event");
-	command_print(cmd_ctx, "------------------------- | "
+	command_print(CMD, "%-25s | Body", "Event");
+	command_print(CMD, "------------------------- | "
 			"----------------------------------------");
 	while (teap) {
 		Jim_Nvp *opt = Jim_Nvp_value2name_simple(nvp_target_event, teap->event);
-		command_print(cmd_ctx, "%-25s | %s",
+		command_print(CMD, "%-25s | %s",
 				opt->name, Jim_GetString(teap->body, NULL));
 		teap = teap->next;
 	}
-	command_print(cmd_ctx, "***END***");
-	return JIM_OK;
+	command_print(CMD, "***END***");
+	return ERROR_OK;
 }
 static int jim_target_current_state(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 {
@@ -5444,7 +5247,7 @@ static int jim_target_invoke_event(Jim_Interp *interp, int argc, Jim_Obj *const
 static const struct command_registration target_instance_command_handlers[] = {
 	{
 		.name = "configure",
-		.mode = COMMAND_CONFIG,
+		.mode = COMMAND_ANY,
 		.jim_handler = jim_target_configure,
 		.help  = "configure a new target for use",
 		.usage = "[target_attribute ...]",
@@ -5457,44 +5260,58 @@ static const struct command_registration target_instance_command_handlers[] = {
 		.usage = "target_attribute",
 	},
 	{
+		.name = "mwd",
+		.handler = handle_mw_command,
+		.mode = COMMAND_EXEC,
+		.help = "Write 64-bit word(s) to target memory",
+		.usage = "address data [count]",
+	},
+	{
 		.name = "mww",
+		.handler = handle_mw_command,
 		.mode = COMMAND_EXEC,
-		.jim_handler = jim_target_mw,
 		.help = "Write 32-bit word(s) to target memory",
 		.usage = "address data [count]",
 	},
 	{
 		.name = "mwh",
+		.handler = handle_mw_command,
 		.mode = COMMAND_EXEC,
-		.jim_handler = jim_target_mw,
 		.help = "Write 16-bit half-word(s) to target memory",
 		.usage = "address data [count]",
 	},
 	{
 		.name = "mwb",
+		.handler = handle_mw_command,
 		.mode = COMMAND_EXEC,
-		.jim_handler = jim_target_mw,
 		.help = "Write byte(s) to target memory",
 		.usage = "address data [count]",
 	},
 	{
+		.name = "mdd",
+		.handler = handle_md_command,
+		.mode = COMMAND_EXEC,
+		.help = "Display target memory as 64-bit words",
+		.usage = "address [count]",
+	},
+	{
 		.name = "mdw",
+		.handler = handle_md_command,
 		.mode = COMMAND_EXEC,
-		.jim_handler = jim_target_md,
 		.help = "Display target memory as 32-bit words",
 		.usage = "address [count]",
 	},
 	{
 		.name = "mdh",
+		.handler = handle_md_command,
 		.mode = COMMAND_EXEC,
-		.jim_handler = jim_target_md,
 		.help = "Display target memory as 16-bit half-words",
 		.usage = "address [count]",
 	},
 	{
 		.name = "mdb",
+		.handler = handle_md_command,
 		.mode = COMMAND_EXEC,
-		.jim_handler = jim_target_md,
 		.help = "Display target memory as 8-bit bytes",
 		.usage = "address [count]",
 	},
@@ -5516,9 +5333,10 @@ static const struct command_registration target_instance_command_handlers[] = {
 	},
 	{
 		.name = "eventlist",
+		.handler = handle_target_event_list,
 		.mode = COMMAND_EXEC,
-		.jim_handler = jim_target_event_list,
 		.help = "displays a table of events defined for this target",
+		.usage = "",
 	},
 	{
 		.name = "curstate",
@@ -5917,6 +5735,7 @@ static const struct command_registration target_subcommand_handlers[] = {
 		.mode = COMMAND_CONFIG,
 		.handler = handle_target_init_command,
 		.help = "initialize targets",
+		.usage = "",
 	},
 	{
 		.name = "create",
@@ -6006,7 +5825,7 @@ COMMAND_HANDLER(handle_fast_load_image_command)
 	fastload_num = image.num_sections;
 	fastload = malloc(sizeof(struct FastLoad)*image.num_sections);
 	if (fastload == NULL) {
-		command_print(CMD_CTX, "out of memory");
+		command_print(CMD, "out of memory");
 		image_close(&image);
 		return ERROR_FAIL;
 	}
@@ -6014,7 +5833,7 @@ COMMAND_HANDLER(handle_fast_load_image_command)
 	for (i = 0; i < image.num_sections; i++) {
 		buffer = malloc(image.sections[i].size);
 		if (buffer == NULL) {
-			command_print(CMD_CTX, "error allocating buffer for section (%d bytes)",
+			command_print(CMD, "error allocating buffer for section (%d bytes)",
 						  (int)(image.sections[i].size));
 			retval = ERROR_FAIL;
 			break;
@@ -6046,7 +5865,7 @@ COMMAND_HANDLER(handle_fast_load_image_command)
 			fastload[i].data = malloc(length);
 			if (fastload[i].data == NULL) {
 				free(buffer);
-				command_print(CMD_CTX, "error allocating buffer for section (%" PRIu32 " bytes)",
+				command_print(CMD, "error allocating buffer for section (%" PRIu32 " bytes)",
 							  length);
 				retval = ERROR_FAIL;
 				break;
@@ -6055,7 +5874,7 @@ COMMAND_HANDLER(handle_fast_load_image_command)
 			fastload[i].length = length;
 
 			image_size += length;
-			command_print(CMD_CTX, "%u bytes written at address 0x%8.8x",
+			command_print(CMD, "%u bytes written at address 0x%8.8x",
 						  (unsigned int)length,
 						  ((unsigned int)(image.sections[i].base_address + offset)));
 		}
@@ -6064,11 +5883,11 @@ COMMAND_HANDLER(handle_fast_load_image_command)
 	}
 
 	if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK)) {
-		command_print(CMD_CTX, "Loaded %" PRIu32 " bytes "
+		command_print(CMD, "Loaded %" PRIu32 " bytes "
 				"in %fs (%0.3f KiB/s)", image_size,
 				duration_elapsed(&bench), duration_kbps(&bench, image_size));
 
-		command_print(CMD_CTX,
+		command_print(CMD,
 				"WARNING: image has not been loaded to target!"
 				"You can issue a 'fast_load' to finish loading.");
 	}
@@ -6095,7 +5914,7 @@ COMMAND_HANDLER(handle_fast_load_command)
 	int retval = ERROR_OK;
 	for (i = 0; i < fastload_num; i++) {
 		struct target *target = get_current_target(CMD_CTX);
-		command_print(CMD_CTX, "Write to 0x%08x, length 0x%08x",
+		command_print(CMD, "Write to 0x%08x, length 0x%08x",
 					  (unsigned int)(fastload[i].address),
 					  (unsigned int)(fastload[i].length));
 		retval = target_write_buffer(target, fastload[i].address, fastload[i].length, fastload[i].data);
@@ -6105,7 +5924,7 @@ COMMAND_HANDLER(handle_fast_load_command)
 	}
 	if (retval == ERROR_OK) {
 		int64_t after = timeval_ms();
-		command_print(CMD_CTX, "Loaded image %f kBytes/s", (float)(size/1024.0)/((float)(after-ms)/1000.0));
+		command_print(CMD, "Loaded image %f kBytes/s", (float)(size/1024.0)/((float)(after-ms)/1000.0));
 	}
 	return retval;
 }
@@ -6123,8 +5942,8 @@ static const struct command_registration target_command_handlers[] = {
 		.name = "target",
 		.mode = COMMAND_CONFIG,
 		.help = "configure target",
-
 		.chain = target_subcommand_handlers,
+		.usage = "",
 	},
 	COMMAND_REGISTRATION_DONE
 };
@@ -6160,7 +5979,7 @@ COMMAND_HANDLER(handle_ps_command)
 	if ((target->rtos) && (target->rtos->type)
 			&& (target->rtos->type->ps_command)) {
 		display = target->rtos->type->ps_command(target);
-		command_print(CMD_CTX, "%s", display);
+		command_print(CMD, "%s", display);
 		free(display);
 		return ERROR_OK;
 	} else {
@@ -6169,13 +5988,13 @@ COMMAND_HANDLER(handle_ps_command)
 	}
 }
 
-static void binprint(struct command_context *cmd_ctx, const char *text, const uint8_t *buf, int size)
+static void binprint(struct command_invocation *cmd, const char *text, const uint8_t *buf, int size)
 {
 	if (text != NULL)
-		command_print_sameline(cmd_ctx, "%s", text);
+		command_print_sameline(cmd, "%s", text);
 	for (int i = 0; i < size; i++)
-		command_print_sameline(cmd_ctx, " %02x", buf[i]);
-	command_print(cmd_ctx, " ");
+		command_print_sameline(cmd, " %02x", buf[i]);
+	command_print(cmd, " ");
 }
 
 COMMAND_HANDLER(handle_test_mem_access_command)
@@ -6227,7 +6046,7 @@ COMMAND_HANDLER(handle_test_mem_access_command)
 					read_ref[i] = rand();
 					read_buf[i] = read_ref[i];
 				}
-				command_print_sameline(CMD_CTX,
+				command_print_sameline(CMD,
 						"Test read %" PRIu32 " x %d @ %d to %saligned buffer: ", count,
 						size, offset, host_offset ? "un" : "");
 
@@ -6240,10 +6059,10 @@ COMMAND_HANDLER(handle_test_mem_access_command)
 				duration_measure(&bench);
 
 				if (retval == ERROR_TARGET_UNALIGNED_ACCESS) {
-					command_print(CMD_CTX, "Unsupported alignment");
+					command_print(CMD, "Unsupported alignment");
 					goto next;
 				} else if (retval != ERROR_OK) {
-					command_print(CMD_CTX, "Memory read failed");
+					command_print(CMD, "Memory read failed");
 					goto next;
 				}
 
@@ -6253,13 +6072,13 @@ COMMAND_HANDLER(handle_test_mem_access_command)
 				/* check result */
 				int result = memcmp(read_ref, read_buf, host_bufsiz);
 				if (result == 0) {
-					command_print(CMD_CTX, "Pass in %fs (%0.3f KiB/s)",
+					command_print(CMD, "Pass in %fs (%0.3f KiB/s)",
 							duration_elapsed(&bench),
 							duration_kbps(&bench, count * size));
 				} else {
-					command_print(CMD_CTX, "Compare failed");
-					binprint(CMD_CTX, "ref:", read_ref, host_bufsiz);
-					binprint(CMD_CTX, "buf:", read_buf, host_bufsiz);
+					command_print(CMD, "Compare failed");
+					binprint(CMD, "ref:", read_ref, host_bufsiz);
+					binprint(CMD, "buf:", read_buf, host_bufsiz);
 				}
 next:
 				free(read_ref);
@@ -6299,13 +6118,13 @@ out:
 
 				for (size_t i = 0; i < host_bufsiz; i++)
 					write_buf[i] = rand();
-				command_print_sameline(CMD_CTX,
+				command_print_sameline(CMD,
 						"Test write %" PRIu32 " x %d @ %d from %saligned buffer: ", count,
 						size, offset, host_offset ? "un" : "");
 
 				retval = target_write_memory(target, wa->address, 1, num_bytes, test_pattern);
 				if (retval != ERROR_OK) {
-					command_print(CMD_CTX, "Test pattern write failed");
+					command_print(CMD, "Test pattern write failed");
 					goto nextw;
 				}
 
@@ -6322,30 +6141,30 @@ out:
 				duration_measure(&bench);
 
 				if (retval == ERROR_TARGET_UNALIGNED_ACCESS) {
-					command_print(CMD_CTX, "Unsupported alignment");
+					command_print(CMD, "Unsupported alignment");
 					goto nextw;
 				} else if (retval != ERROR_OK) {
-					command_print(CMD_CTX, "Memory write failed");
+					command_print(CMD, "Memory write failed");
 					goto nextw;
 				}
 
 				/* read back */
 				retval = target_read_memory(target, wa->address, 1, num_bytes, read_buf);
 				if (retval != ERROR_OK) {
-					command_print(CMD_CTX, "Test pattern write failed");
+					command_print(CMD, "Test pattern write failed");
 					goto nextw;
 				}
 
 				/* check result */
 				int result = memcmp(read_ref, read_buf, num_bytes);
 				if (result == 0) {
-					command_print(CMD_CTX, "Pass in %fs (%0.3f KiB/s)",
+					command_print(CMD, "Pass in %fs (%0.3f KiB/s)",
 							duration_elapsed(&bench),
 							duration_kbps(&bench, count * size));
 				} else {
-					command_print(CMD_CTX, "Compare failed");
-					binprint(CMD_CTX, "ref:", read_ref, num_bytes);
-					binprint(CMD_CTX, "buf:", read_buf, num_bytes);
+					command_print(CMD, "Compare failed");
+					binprint(CMD, "ref:", read_ref, num_bytes);
+					binprint(CMD, "buf:", read_buf, num_bytes);
 				}
 nextw:
 				free(read_ref);
@@ -6458,7 +6277,7 @@ static const struct command_registration target_exec_command_handlers[] = {
 		.name = "mdd",
 		.handler = handle_md_command,
 		.mode = COMMAND_EXEC,
-		.help = "display memory words",
+		.help = "display memory double-words",
 		.usage = "['phys'] address [count]",
 	},
 	{
@@ -6486,7 +6305,7 @@ static const struct command_registration target_exec_command_handlers[] = {
 		.name = "mwd",
 		.handler = handle_mw_command,
 		.mode = COMMAND_EXEC,
-		.help = "write memory word",
+		.help = "write memory double-word",
 		.usage = "['phys'] address value [count]",
 	},
 	{
@@ -6515,7 +6334,7 @@ static const struct command_registration target_exec_command_handlers[] = {
 		.handler = handle_bp_command,
 		.mode = COMMAND_EXEC,
 		.help = "list or set hardware or software breakpoint",
-		.usage = "<address> [<asid>] <length> ['hw'|'hw_ctx']",
+		.usage = "[<address> [<asid>] <length> ['hw'|'hw_ctx']]",
 	},
 	{
 		.name = "rbp",
diff --git a/src/target/target.h b/src/target/target.h
index 160ac4a..957a7d0 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -36,6 +36,7 @@
 struct reg;
 struct trace;
 struct command_context;
+struct command_invocation;
 struct breakpoint;
 struct watchpoint;
 struct mem_param;
@@ -739,6 +740,10 @@ int target_arch_state(struct target *target);
 
 void target_handle_event(struct target *t, enum target_event e);
 
+void target_handle_md_output(struct command_invocation *cmd,
+	struct target *target, target_addr_t address, unsigned size,
+	unsigned count, const uint8_t *buffer);
+
 #define ERROR_TARGET_INVALID	(-300)
 #define ERROR_TARGET_INIT_FAILED (-301)
 #define ERROR_TARGET_TIMEOUT	(-302)
diff --git a/src/target/target_request.c b/src/target/target_request.c
index 6ca204b..c1da1a2 100644
--- a/src/target/target_request.c
+++ b/src/target/target_request.c
@@ -56,7 +56,7 @@ static int target_asciimsg(struct target *target, uint32_t length)
 	LOG_DEBUG("%s", msg);
 
 	while (c) {
-		command_print(c->cmd_ctx, "%s", msg);
+		command_output_text(c->cmd_ctx, msg);
 		c = c->next;
 	}
 
@@ -100,7 +100,7 @@ static int target_hexmsg(struct target *target, int size, uint32_t length)
 			LOG_DEBUG("%s", line);
 
 			while (c) {
-				command_print(c->cmd_ctx, "%s", line);
+				command_output_text(c->cmd_ctx, line);
 				c = c->next;
 			}
 			c = target->dbgmsg;
@@ -283,7 +283,7 @@ COMMAND_HANDLER(handle_target_request_debugmsgs_command)
 			return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
-	command_print(CMD_CTX, "receiving debug messages from current target %s",
+	command_print(CMD, "receiving debug messages from current target %s",
 			(receiving) ? (charmsg_mode ? "charmsg" : "enabled") : "disabled");
 	return ERROR_OK;
 }
diff --git a/src/target/testee.c b/src/target/testee.c
index 5b6cced..236ac9a 100644
--- a/src/target/testee.c
+++ b/src/target/testee.c
@@ -30,8 +30,8 @@ static const struct command_registration testee_command_handlers[] = {
 		.name = "testee",
 		.mode = COMMAND_ANY,
 		.help = "testee target commands",
-
 		.chain = hello_command_handlers,
+		.usage = "",
 	},
 	COMMAND_REGISTRATION_DONE
 };
diff --git a/src/target/trace.c b/src/target/trace.c
index 63c477f..943bf1f 100644
--- a/src/target/trace.c
+++ b/src/target/trace.c
@@ -53,7 +53,7 @@ COMMAND_HANDLER(handle_trace_point_command)
 		uint32_t i;
 
 		for (i = 0; i < trace->num_trace_points; i++) {
-			command_print(CMD_CTX, "trace point 0x%8.8" PRIx32 " (%lld times hit)",
+			command_print(CMD, "trace point 0x%8.8" PRIx32 " (%lld times hit)",
 					trace->trace_points[i].address,
 					(long long)trace->trace_points[i].hit_counter);
 		}
@@ -108,14 +108,14 @@ COMMAND_HANDLER(handle_trace_history_command)
 		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], trace->trace_history_size);
 		trace->trace_history = malloc(sizeof(uint32_t) * trace->trace_history_size);
 
-		command_print(CMD_CTX, "new trace history size: %i", (int)(trace->trace_history_size));
+		command_print(CMD, "new trace history size: %i", (int)(trace->trace_history_size));
 	} else {
 		uint32_t i;
 		uint32_t first = 0;
 		uint32_t last = trace->trace_history_pos;
 
 		if (!trace->trace_history_size) {
-			command_print(CMD_CTX, "trace history buffer is not allocated");
+			command_print(CMD, "trace history buffer is not allocated");
 			return ERROR_OK;
 		}
 
@@ -128,11 +128,11 @@ COMMAND_HANDLER(handle_trace_history_command)
 			if (trace->trace_history[i % trace->trace_history_size] < trace->num_trace_points) {
 				uint32_t address;
 				address = trace->trace_points[trace->trace_history[i % trace->trace_history_size]].address;
-				command_print(CMD_CTX, "trace point %i: 0x%8.8" PRIx32 "",
+				command_print(CMD, "trace point %i: 0x%8.8" PRIx32 "",
 						(int)(trace->trace_history[i % trace->trace_history_size]),
 						address);
 			} else
-				command_print(CMD_CTX, "trace point %i: -not defined-",
+				command_print(CMD, "trace point %i: -not defined-",
 						(int)(trace->trace_history[i % trace->trace_history_size]));
 		}
 	}
diff --git a/src/target/x86_32_common.c b/src/target/x86_32_common.c
index 011e7d8..b85e451 100644
--- a/src/target/x86_32_common.c
+++ b/src/target/x86_32_common.c
@@ -1340,7 +1340,7 @@ static int write_hw_reg_from_cache(struct target *t, int num)
 }
 
 /* x86 32 commands */
-static void handle_iod_output(struct command_context *cmd_ctx,
+static void handle_iod_output(struct command_invocation *cmd,
 		struct target *target, uint32_t address, unsigned size,
 		unsigned count, const uint8_t *buffer)
 {
@@ -1392,7 +1392,7 @@ static void handle_iod_output(struct command_context *cmd_ctx,
 				value_fmt, value);
 
 		if ((i % line_modulo == line_modulo - 1) || (i == count - 1)) {
-			command_print(cmd_ctx, "%s", output);
+			command_print(cmd, "%s", output);
 			output_len = 0;
 		}
 	}
@@ -1429,7 +1429,7 @@ COMMAND_HANDLER(handle_iod_command)
 	struct target *target = get_current_target(CMD_CTX);
 	int retval = x86_32_common_read_io(target, address, size, buffer);
 	if (ERROR_OK == retval)
-		handle_iod_output(CMD_CTX, target, address, size, count, buffer);
+		handle_iod_output(CMD, target, address, size, count, buffer);
 	free(buffer);
 	return retval;
 }
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 09abd9e..1a099c9 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -138,11 +138,11 @@ static int xscale_set_reg_u32(struct reg *reg, uint32_t value)
 
 static const char xscale_not[] = "target is not an XScale";
 
-static int xscale_verify_pointer(struct command_context *cmd_ctx,
+static int xscale_verify_pointer(struct command_invocation *cmd,
 	struct xscale_common *xscale)
 {
 	if (xscale->common_magic != XSCALE_COMMON_MAGIC) {
-		command_print(cmd_ctx, xscale_not);
+		command_print(cmd, xscale_not);
 		return ERROR_TARGET_INVALID;
 	}
 	return ERROR_OK;
@@ -2654,16 +2654,16 @@ static inline void xscale_branch_address(struct xscale_trace_data *trace_data,
 
 static inline void xscale_display_instruction(struct target *target, uint32_t pc,
 	struct arm_instruction *instruction,
-	struct command_context *cmd_ctx)
+	struct command_invocation *cmd)
 {
 	int retval = xscale_read_instruction(target, pc, instruction);
 	if (retval == ERROR_OK)
-		command_print(cmd_ctx, "%s", instruction->text);
+		command_print(cmd, "%s", instruction->text);
 	else
-		command_print(cmd_ctx, "0x%8.8" PRIx32 "\t<not found in image>", pc);
+		command_print(cmd, "0x%8.8" PRIx32 "\t<not found in image>", pc);
 }
 
-static int xscale_analyze_trace(struct target *target, struct command_context *cmd_ctx)
+static int xscale_analyze_trace(struct target *target, struct command_invocation *cmd)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 	struct xscale_trace_data *trace_data = xscale->trace.data;
@@ -2771,7 +2771,7 @@ static int xscale_analyze_trace(struct target *target, struct command_context *c
 			count = trace_data->entries[i].data & 0x0f;
 			for (j = 0; j < count; j++) {
 				xscale_display_instruction(target, current_pc, &instruction,
-					cmd_ctx);
+					cmd);
 				current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
 			}
 
@@ -2779,7 +2779,7 @@ static int xscale_analyze_trace(struct target *target, struct command_context *c
 			 * rollover and some exceptions: undef, swi, prefetch abort. */
 			if ((trace_msg_type == 15) || (exception > 0 && exception < 4)) {
 				xscale_display_instruction(target, current_pc, &instruction,
-					cmd_ctx);
+					cmd);
 				current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
 			}
 
@@ -2787,13 +2787,13 @@ static int xscale_analyze_trace(struct target *target, struct command_context *c
 				continue;
 
 			if (exception) {
-				command_print(cmd_ctx, "--- exception %i ---", exception);
+				command_print(cmd, "--- exception %i ---", exception);
 				continue;
 			}
 
 			/* not exception or rollover; next instruction is a branch and is
 			 * not included in the count */
-			xscale_display_instruction(target, current_pc, &instruction, cmd_ctx);
+			xscale_display_instruction(target, current_pc, &instruction, cmd);
 
 			/* for direct branches, extract branch destination from instruction */
 			if ((trace_msg_type == 8) || (trace_msg_type == 12)) {
@@ -2813,7 +2813,7 @@ static int xscale_analyze_trace(struct target *target, struct command_context *c
 				}
 
 				if (current_pc == 0)
-					command_print(cmd_ctx, "address unknown");
+					command_print(cmd, "address unknown");
 
 				continue;
 			}
@@ -2855,7 +2855,7 @@ static int xscale_analyze_trace(struct target *target, struct command_context *c
 
 	/* display remaining instructions */
 	for (i = 0; i < gap_count; i++) {
-		xscale_display_instruction(target, current_pc, &instruction, cmd_ctx);
+		xscale_display_instruction(target, current_pc, &instruction, cmd);
 		current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
 	}
 
@@ -2895,6 +2895,7 @@ static void xscale_build_reg_cache(struct target *target)
 		(*cache_p)->reg_list[i].size = 32;
 		(*cache_p)->reg_list[i].arch_info = &arch_info[i];
 		(*cache_p)->reg_list[i].type = &xscale_reg_type;
+		(*cache_p)->reg_list[i].exist = true;
 		arch_info[i] = xscale_reg_arch_info[i];
 		arch_info[i].target = target;
 	}
@@ -3032,7 +3033,7 @@ COMMAND_HANDLER(xscale_handle_debug_handler_command)
 	}
 
 	xscale = target_to_xscale(target);
-	retval = xscale_verify_pointer(CMD_CTX, xscale);
+	retval = xscale_verify_pointer(CMD, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -3066,7 +3067,7 @@ COMMAND_HANDLER(xscale_handle_cache_clean_address_command)
 		return ERROR_FAIL;
 	}
 	xscale = target_to_xscale(target);
-	retval = xscale_verify_pointer(CMD_CTX, xscale);
+	retval = xscale_verify_pointer(CMD, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -3086,11 +3087,11 @@ COMMAND_HANDLER(xscale_handle_cache_info_command)
 	struct xscale_common *xscale = target_to_xscale(target);
 	int retval;
 
-	retval = xscale_verify_pointer(CMD_CTX, xscale);
+	retval = xscale_verify_pointer(CMD, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
-	return armv4_5_handle_cache_info_command(CMD_CTX, &xscale->armv4_5_mmu.armv4_5_cache);
+	return armv4_5_handle_cache_info_command(CMD, &xscale->armv4_5_mmu.armv4_5_cache);
 }
 
 static int xscale_virt2phys(struct target *target,
@@ -3131,12 +3132,12 @@ COMMAND_HANDLER(xscale_handle_mmu_command)
 	struct xscale_common *xscale = target_to_xscale(target);
 	int retval;
 
-	retval = xscale_verify_pointer(CMD_CTX, xscale);
+	retval = xscale_verify_pointer(CMD, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
 	if (target->state != TARGET_HALTED) {
-		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+		command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
 		return ERROR_OK;
 	}
 
@@ -3150,7 +3151,7 @@ COMMAND_HANDLER(xscale_handle_mmu_command)
 		xscale->armv4_5_mmu.mmu_enabled = enable;
 	}
 
-	command_print(CMD_CTX, "mmu %s",
+	command_print(CMD, "mmu %s",
 		(xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled");
 
 	return ERROR_OK;
@@ -3161,12 +3162,12 @@ COMMAND_HANDLER(xscale_handle_idcache_command)
 	struct target *target = get_current_target(CMD_CTX);
 	struct xscale_common *xscale = target_to_xscale(target);
 
-	int retval = xscale_verify_pointer(CMD_CTX, xscale);
+	int retval = xscale_verify_pointer(CMD, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
 	if (target->state != TARGET_HALTED) {
-		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+		command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
 		return ERROR_OK;
 	}
 
@@ -3195,7 +3196,7 @@ COMMAND_HANDLER(xscale_handle_idcache_command)
 		xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled :
 		xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled;
 	const char *msg = enabled ? "enabled" : "disabled";
-	command_print(CMD_CTX, "%s %s", CMD_NAME, msg);
+	command_print(CMD, "%s %s", CMD_NAME, msg);
 
 	return ERROR_OK;
 }
@@ -3222,7 +3223,7 @@ COMMAND_HANDLER(xscale_handle_vector_catch_command)
 	uint32_t catch = 0;
 	struct reg *dcsr_reg = &xscale->reg_cache->reg_list[XSCALE_DCSR];
 
-	retval = xscale_verify_pointer(CMD_CTX, xscale);
+	retval = xscale_verify_pointer(CMD, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -3257,7 +3258,7 @@ COMMAND_HANDLER(xscale_handle_vector_catch_command)
 
 	dcsr_value = buf_get_u32(dcsr_reg->value, 0, 32);
 	for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
-		command_print(CMD_CTX, "%15s: %s", vec_ids[i].name,
+		command_print(CMD, "%15s: %s", vec_ids[i].name,
 			(dcsr_value & vec_ids[i].mask) ? "catch" : "ignore");
 	}
 
@@ -3272,23 +3273,23 @@ COMMAND_HANDLER(xscale_handle_vector_table_command)
 	int err = 0;
 	int retval;
 
-	retval = xscale_verify_pointer(CMD_CTX, xscale);
+	retval = xscale_verify_pointer(CMD, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
 	if (CMD_ARGC == 0) {	/* print current settings */
 		int idx;
 
-		command_print(CMD_CTX, "active user-set static vectors:");
+		command_print(CMD, "active user-set static vectors:");
 		for (idx = 1; idx < 8; idx++)
 			if (xscale->static_low_vectors_set & (1 << idx))
-				command_print(CMD_CTX,
+				command_print(CMD,
 					"low  %d: 0x%" PRIx32,
 					idx,
 					xscale->static_low_vectors[idx]);
 		for (idx = 1; idx < 8; idx++)
 			if (xscale->static_high_vectors_set & (1 << idx))
-				command_print(CMD_CTX,
+				command_print(CMD,
 					"high %d: 0x%" PRIx32,
 					idx,
 					xscale->static_high_vectors[idx]);
@@ -3330,12 +3331,12 @@ COMMAND_HANDLER(xscale_handle_trace_buffer_command)
 	uint32_t dcsr_value;
 	int retval;
 
-	retval = xscale_verify_pointer(CMD_CTX, xscale);
+	retval = xscale_verify_pointer(CMD, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
 	if (target->state != TARGET_HALTED) {
-		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+		command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
 		return ERROR_OK;
 	}
 
@@ -3354,7 +3355,7 @@ COMMAND_HANDLER(xscale_handle_trace_buffer_command)
 			if (CMD_ARGC >= 3)
 				COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], buffcount);
 			if (buffcount < 1) {		/* invalid */
-				command_print(CMD_CTX, "fill buffer count must be > 0");
+				command_print(CMD, "fill buffer count must be > 0");
 				xscale->trace.mode = XSCALE_TRACE_DISABLED;
 				return ERROR_COMMAND_SYNTAX_ERROR;
 			}
@@ -3371,11 +3372,11 @@ COMMAND_HANDLER(xscale_handle_trace_buffer_command)
 	if (xscale->trace.mode != XSCALE_TRACE_DISABLED) {
 		char fill_string[12];
 		sprintf(fill_string, "fill %d", xscale->trace.buffer_fill);
-		command_print(CMD_CTX, "trace buffer enabled (%s)",
+		command_print(CMD, "trace buffer enabled (%s)",
 			(xscale->trace.mode == XSCALE_TRACE_FILL)
 			? fill_string : "wrap");
 	} else
-		command_print(CMD_CTX, "trace buffer disabled");
+		command_print(CMD, "trace buffer disabled");
 
 	dcsr_value = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32);
 	if (xscale->trace.mode == XSCALE_TRACE_FILL)
@@ -3395,14 +3396,14 @@ COMMAND_HANDLER(xscale_handle_trace_image_command)
 	if (CMD_ARGC < 1)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	retval = xscale_verify_pointer(CMD_CTX, xscale);
+	retval = xscale_verify_pointer(CMD, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
 	if (xscale->trace.image) {
 		image_close(xscale->trace.image);
 		free(xscale->trace.image);
-		command_print(CMD_CTX, "previously loaded image found and closed");
+		command_print(CMD, "previously loaded image found and closed");
 	}
 
 	xscale->trace.image = malloc(sizeof(struct image));
@@ -3434,12 +3435,12 @@ COMMAND_HANDLER(xscale_handle_dump_trace_command)
 	struct fileio *file;
 	int retval;
 
-	retval = xscale_verify_pointer(CMD_CTX, xscale);
+	retval = xscale_verify_pointer(CMD, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
 	if (target->state != TARGET_HALTED) {
-		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+		command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
 		return ERROR_OK;
 	}
 
@@ -3449,7 +3450,7 @@ COMMAND_HANDLER(xscale_handle_dump_trace_command)
 	trace_data = xscale->trace.data;
 
 	if (!trace_data) {
-		command_print(CMD_CTX, "no trace data collected");
+		command_print(CMD, "no trace data collected");
 		return ERROR_OK;
 	}
 
@@ -3482,11 +3483,11 @@ COMMAND_HANDLER(xscale_handle_analyze_trace_buffer_command)
 	struct xscale_common *xscale = target_to_xscale(target);
 	int retval;
 
-	retval = xscale_verify_pointer(CMD_CTX, xscale);
+	retval = xscale_verify_pointer(CMD, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
-	xscale_analyze_trace(target, CMD_CTX);
+	xscale_analyze_trace(target, CMD);
 
 	return ERROR_OK;
 }
@@ -3497,12 +3498,12 @@ COMMAND_HANDLER(xscale_handle_cp15)
 	struct xscale_common *xscale = target_to_xscale(target);
 	int retval;
 
-	retval = xscale_verify_pointer(CMD_CTX, xscale);
+	retval = xscale_verify_pointer(CMD, xscale);
 	if (retval != ERROR_OK)
 		return retval;
 
 	if (target->state != TARGET_HALTED) {
-		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+		command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
 		return ERROR_OK;
 	}
 	uint32_t reg_no = 0;
@@ -3536,7 +3537,7 @@ COMMAND_HANDLER(xscale_handle_cp15)
 				reg_no = XSCALE_CPACCESS;
 				break;
 			default:
-				command_print(CMD_CTX, "invalid register number");
+				command_print(CMD, "invalid register number");
 				return ERROR_COMMAND_SYNTAX_ERROR;
 		}
 		reg = &xscale->reg_cache->reg_list[reg_no];
@@ -3548,7 +3549,7 @@ COMMAND_HANDLER(xscale_handle_cp15)
 		/* read cp15 control register */
 		xscale_get_reg(reg);
 		value = buf_get_u32(reg->value, 0, 32);
-		command_print(CMD_CTX, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size),
+		command_print(CMD, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size),
 			value);
 	} else if (CMD_ARGC == 2) {
 		uint32_t value;
@@ -3577,6 +3578,7 @@ static const struct command_registration xscale_exec_command_handlers[] = {
 		.handler = xscale_handle_cache_info_command,
 		.mode = COMMAND_EXEC,
 		.help = "display information about CPU caches",
+		.usage = "",
 	},
 	{
 		.name = "mmu",