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authorDavid Brownell <dbrownell@users.sourceforge.net>2009-12-09 10:25:08 -0800
committerDavid Brownell <dbrownell@users.sourceforge.net>2009-12-09 10:25:52 -0800
commit910dd664ceb6faef5e9029e9b0848d7ccc63bf4b (patch)
treee94c456002048802ac86043a7ecaaf8ffb682697 /src/target
parent26d7ed08f9ff220be583179fdea76466739cf32d (diff)
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Comment and doxygen fixes
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target')
-rw-r--r--src/target/arm_opcodes.h15
-rw-r--r--src/target/embeddedice.c3
2 files changed, 14 insertions, 4 deletions
diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h
index b3b5143..58498ac 100644
--- a/src/target/arm_opcodes.h
+++ b/src/target/arm_opcodes.h
@@ -26,6 +26,11 @@
#ifndef __ARM_OPCODES_H
#define __ARM_OPCODES_H
+/**
+ * @file
+ * Macros used to generate various ARM or Thumb opcodes.
+ */
+
/* ARM mode instructions */
/* Store multiple increment after
@@ -145,9 +150,13 @@
/* Thumb mode instructions
*
- * FIXME there must be some reason all these opcodes are 32-bits
- * not 16-bits ... this should get either an explanatory comment,
- * or be changed not to duplicate the opcode.
+ * NOTE: these 16-bit opcodes fill both halves of a word with the same
+ * value. The reason for this is that when we need to execute Thumb
+ * opcodes on ARM7/ARM9 cores (to switch to ARM state on debug entry),
+ * we must shift 32 bits to the bus using scan chain 1 ... if we write
+ * both halves, we don't need to track which half matters. On ARMv6 and
+ * ARMv7 we don't execute Thumb instructions in debug mode; the ITR
+ * register does not accept Thumb (or Thumb2) opcodes.
*/
/* Store register (Thumb mode)
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index eb04bd1..a705d7d 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -35,7 +35,8 @@
*
* This provides lowlevel glue to the EmbeddedICE (or EmbeddedICE-RT)
* module found on scan chain 2 in ARM7, ARM9, and some other families
- * of ARM cores.
+ * of ARM cores. The module is called "EmbeddedICE-RT" if it has
+ * monitor mode support.
*
* EmbeddedICE provides basic watchpoint/breakpoint hardware and a Debug
* Communications Channel (DCC) used to read or write 32-bit words to