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author | Antonio Borneo <borneo.antonio@gmail.com> | 2021-08-08 13:51:33 +0200 |
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committer | Antonio Borneo <borneo.antonio@gmail.com> | 2021-08-22 20:26:06 +0000 |
commit | 7a61a006decf828f0f75e0602cc17d6efb897f57 (patch) | |
tree | 67feda4a4983cd9c04e92b82d7af95b0e7327450 /src/target | |
parent | 66175577e1f5b89470bafa1e613e10307996a3fb (diff) | |
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jep106: use packed jedec manufacturer code
JEP106 encodes JEDEC-assigned manufacture code as:
a) a sequence of zero or more escape codes 0x7f;
b) an odd-parity bit of the next 7 bits;
c) 7 bits.
The same code is often represented as a single value composed by
the logical OR between:
- the number of escape codes in a), shifted left by 7 positions;
- the 7 bits in c).
This is the preferred packed representation used by this change.
Currently there are only two uses of JEP106 in openocd to get the
manufacturer name:
- to decode the JTAG IDCODE of each TAP, where the JEP106 code is
already packed as in the preferred representation above in bits
IDCODE[11:1];
- to decode the ARM CoreSight PIDR register, where the JEP106 code
is split in 3 parts:
= PIDR3[3:0], corresponding to bits [10:7] of the packed code;
= PIDR2[2:0], corresponding to bits [6:4] of the packed code;
= PIDR1[7:4], corresponding to bits [3:0] of the packed code.
Wrap the existing JEP106 decode function in a simpler API using
the packed code.
Simplify the callers by skipping the bit unpacking.
Change the manufacturer code in CoreSight table dap_partnums[] to
match the packed representation, by removing the always-one bit 7
erroneously taken from PIDR bit JEDEC and included in the former
table.
Change-Id: I63eb4da9e6801fab25e330f1f6b792d2fd619493
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6418
Tested-by: jenkins
Diffstat (limited to 'src/target')
-rw-r--r-- | src/target/arm_adi_v5.c | 40 |
1 files changed, 20 insertions, 20 deletions
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 65a8bc4..c295542 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -1123,7 +1123,7 @@ static int dap_read_part_id(struct adiv5_ap *ap, target_addr_t component_base, u #define ANY_ID 0x1000 -#define ARM_ID 0x4BB +#define ARM_ID 0x23B static const struct { uint16_t designer_id; @@ -1216,22 +1216,22 @@ static const struct { { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", }, { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", }, { ARM_ID, 0xd0b, "Cortex-A76 Debug", "(Debug Unit)", }, - { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" }, - { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" }, - { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" }, - { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" }, - { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" }, - { 0x0E5, 0x000, "SHARC+/Blackfin+", "", }, - { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", }, - { 0x1bf, 0x100, "Brahma-B53 Debug", "(Debug Unit)", }, - { 0x1bf, 0x9d3, "Brahma-B53 PMU", "(Performance Monitor Unit)", }, - { 0x1bf, 0x4a1, "Brahma-B53 ROM", "(ROM Table)", }, - { 0x1bf, 0x721, "Brahma-B53 ROM", "(ROM Table)", }, - { 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", }, - { 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", }, - { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", }, - { 0x3eb, 0x302, "Denver Debug", "(Debug Unit)", }, - { 0x3eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", }, + { 0x017, 0x9af, "MSP432 ROM", "(ROM Table)" }, + { 0x01f, 0xcd0, "Atmel CPU with DSU", "(CPU)" }, + { 0x041, 0x1db, "XMC4500 ROM", "(ROM Table)" }, + { 0x041, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" }, + { 0x041, 0x1ed, "XMC1000 ROM", "(ROM Table)" }, + { 0x065, 0x000, "SHARC+/Blackfin+", "", }, + { 0x070, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", }, + { 0x0bf, 0x100, "Brahma-B53 Debug", "(Debug Unit)", }, + { 0x0bf, 0x9d3, "Brahma-B53 PMU", "(Performance Monitor Unit)", }, + { 0x0bf, 0x4a1, "Brahma-B53 ROM", "(ROM Table)", }, + { 0x0bf, 0x721, "Brahma-B53 ROM", "(ROM Table)", }, + { 0x1eb, 0x181, "Tegra 186 ROM", "(ROM Table)", }, + { 0x1eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", }, + { 0x1eb, 0x211, "Tegra 210 ROM", "(ROM Table)", }, + { 0x1eb, 0x302, "Denver Debug", "(Debug Unit)", }, + { 0x1eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", }, /* legacy comment: 0x113: what? */ { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */ { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */ @@ -1276,12 +1276,12 @@ static int dap_rom_display(struct command_invocation *cmd, uint8_t class = (cid >> 12) & 0xf; uint16_t part_num = pid & 0xfff; - uint16_t designer_id = ((pid >> 32) & 0xf) << 8 | ((pid >> 12) & 0xff); + uint16_t designer_id = ((pid >> 32) & 0xf) << 7 | ((pid >> 12) & 0x7f); - if (designer_id & 0x80) { + if (pid & 0x00080000) { /* JEP106 code */ command_print(cmd, "\t\tDesigner is 0x%03" PRIx16 ", %s", - designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f)); + designer_id, jep106_manufacturer(designer_id)); } else { /* Legacy ASCII ID, clear invalid bits */ designer_id &= 0x7f; |