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authorAntonio Borneo <borneo.antonio@gmail.com>2020-02-12 22:26:51 +0100
committerAntonio Borneo <borneo.antonio@gmail.com>2020-04-12 22:03:00 +0100
commit4873503ae44ff16dde170e3337945e99ad05e408 (patch)
tree97bbc6a4744d1fe4197c8a6d58ad21b1aa84d490 /src/target
parentcbbc56f7f7bef9e0e1cb8711576449c62fe31654 (diff)
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cortex_a: don't wait for target halted in deassert_reset()
The tcl script src/target/startup.tcl has already the proper centralized support to wait for all targets to halt after the command "reset halt". The extra wait in cortex_a_deassert_reset() is not required. This extra wait is also an issue for multi-core support, because waiting for one core to halt can delay the halt request to the other cores. Replace the indirect call to cortex_a_halt(), that embeds the wait for halt, with a low-level halt sequence. The on-going work on the reset framework is compatible with this change; in fact it keeps in startup.tcl the wait for targets to halt, even if current code proposal for cortex_a simply removes the function cortex_a_deassert_reset(). Change-Id: Ic661c3791a29ba7d520e31f85a61f939a646feb5 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5472 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Diffstat (limited to 'src/target')
-rw-r--r--src/target/cortex_a.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 729a173..f71b155 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -1703,6 +1703,7 @@ static int cortex_a_assert_reset(struct target *target)
static int cortex_a_deassert_reset(struct target *target)
{
+ struct armv7a_common *armv7a = target_to_armv7a(target);
int retval;
LOG_DEBUG(" ");
@@ -1721,7 +1722,8 @@ static int cortex_a_deassert_reset(struct target *target)
LOG_WARNING("%s: ran after reset and before halt ...",
target_name(target));
if (target_was_examined(target)) {
- retval = target_halt(target);
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DRCR, DRCR_HALT);
if (retval != ERROR_OK)
return retval;
} else