diff options
author | Antonio Borneo <borneo.antonio@gmail.com> | 2021-07-03 18:18:57 +0200 |
---|---|---|
committer | Antonio Borneo <borneo.antonio@gmail.com> | 2021-07-20 14:55:43 +0100 |
commit | 20b29b7767097f999fe2eb4f7fb6c2917e9f66a6 (patch) | |
tree | f6f060f100e0aae122b6e0fdbae2f342036bd7f7 /src/target | |
parent | 28c24a5c41c47a66e9310912f88148814f730a25 (diff) | |
download | riscv-openocd-20b29b7767097f999fe2eb4f7fb6c2917e9f66a6.zip riscv-openocd-20b29b7767097f999fe2eb4f7fb6c2917e9f66a6.tar.gz riscv-openocd-20b29b7767097f999fe2eb4f7fb6c2917e9f66a6.tar.bz2 |
openocd: manually fix Yoda conditions
Fix the remaining Yoda conditions, detected by checkpatch but not
fixed automatically.
While there, apply minor style changes.
Change-Id: I6e1978b89c4d56a20aceaeb2b52968eb6384432a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6356
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Xiang W <wxjstz@126.com>
Diffstat (limited to 'src/target')
-rw-r--r-- | src/target/arm_semihosting.c | 2 | ||||
-rw-r--r-- | src/target/nds32.c | 23 | ||||
-rw-r--r-- | src/target/nds32_cmd.c | 3 | ||||
-rw-r--r-- | src/target/nds32_disassembler.c | 2 | ||||
-rw-r--r-- | src/target/riscv/riscv-013.c | 12 | ||||
-rw-r--r-- | src/target/riscv/riscv_semihosting.c | 2 |
6 files changed, 20 insertions, 24 deletions
diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c index 9de7048..1e5b5e2 100644 --- a/src/target/arm_semihosting.c +++ b/src/target/arm_semihosting.c @@ -367,7 +367,7 @@ int arm_semihosting(struct target *target, int *retval) } /* Check for ARM operation numbers. */ - if (0 <= semihosting->op && semihosting->op <= 0x31) { + if (semihosting->op >= 0 && semihosting->op <= 0x31) { *retval = semihosting_common(target); if (*retval != ERROR_OK) { LOG_ERROR("Failed semihosting operation (0x%02X)", semihosting->op); diff --git a/src/target/nds32.c b/src/target/nds32.c index 184f2fe..4b1d117 100644 --- a/src/target/nds32.c +++ b/src/target/nds32.c @@ -422,7 +422,7 @@ static struct reg_cache *nds32_build_reg_cache(struct target *target, reg_list[i].reg_data_type = calloc(sizeof(struct reg_data_type), 1); - if (FD0 <= reg_arch_info[i].num && reg_arch_info[i].num <= FD31) { + if (reg_arch_info[i].num >= FD0 && reg_arch_info[i].num <= FD31) { reg_list[i].value = reg_arch_info[i].value; reg_list[i].type = &nds32_reg_access_type_64; @@ -456,20 +456,20 @@ static struct reg_cache *nds32_build_reg_cache(struct target *target, } } - if (R16 <= reg_arch_info[i].num && reg_arch_info[i].num <= R25) + if (reg_arch_info[i].num >= R16 && reg_arch_info[i].num <= R25) reg_list[i].caller_save = true; else reg_list[i].caller_save = false; reg_list[i].feature = malloc(sizeof(struct reg_feature)); - if (R0 <= reg_arch_info[i].num && reg_arch_info[i].num <= IFC_LP) + if (reg_arch_info[i].num >= R0 && reg_arch_info[i].num <= IFC_LP) reg_list[i].feature->name = "org.gnu.gdb.nds32.core"; - else if (CR0 <= reg_arch_info[i].num && reg_arch_info[i].num <= SECUR0) + else if (reg_arch_info[i].num >= CR0 && reg_arch_info[i].num <= SECUR0) reg_list[i].feature->name = "org.gnu.gdb.nds32.system"; - else if (D0L24 <= reg_arch_info[i].num && reg_arch_info[i].num <= CBE3) + else if (reg_arch_info[i].num >= D0L24 && reg_arch_info[i].num <= CBE3) reg_list[i].feature->name = "org.gnu.gdb.nds32.audio"; - else if (FPCSR <= reg_arch_info[i].num && reg_arch_info[i].num <= FD31) + else if (reg_arch_info[i].num >= FPCSR && reg_arch_info[i].num <= FD31) reg_list[i].feature->name = "org.gnu.gdb.nds32.fpu"; cache->num_regs++; @@ -1545,7 +1545,7 @@ int nds32_restore_context(struct target *target) i, buf_get_u32(reg->value, 0, 32)); reg_arch_info = reg->arch_info; - if (FD0 <= reg_arch_info->num && reg_arch_info->num <= FD31) { + if (reg_arch_info->num >= FD0 && reg_arch_info->num <= FD31) { uint64_t val = buf_get_u64(reg_arch_info->value, 0, 64); aice_write_reg_64(aice, reg_arch_info->num, val); } else { @@ -1735,8 +1735,7 @@ int nds32_cache_sync(struct target *target, target_addr_t address, uint32_t leng * be physical address. L1I_VA_INVALIDATE uses PSW.IT to decide * address translation or not. */ target_addr_t physical_addr; - if (ERROR_FAIL == target->type->virt2phys(target, cur_address, - &physical_addr)) + if (target->type->virt2phys(target, cur_address, &physical_addr) == ERROR_FAIL) return ERROR_FAIL; /* I$ invalidate */ @@ -1926,8 +1925,7 @@ int nds32_examine_debug_reason(struct nds32 *nds32) if (ERROR_OK != nds32_read_opcode(nds32, value_pc, &opcode)) return ERROR_FAIL; - if (ERROR_OK != nds32_evaluate_opcode(nds32, opcode, value_pc, - &instruction)) + if (nds32_evaluate_opcode(nds32, opcode, value_pc, &instruction) != ERROR_OK) return ERROR_FAIL; /* hit 'break 0x7FFF' */ @@ -1966,8 +1964,7 @@ int nds32_examine_debug_reason(struct nds32 *nds32) case NDS32_DEBUG_DATA_VALUE_WATCHPOINT_IMPRECISE: case NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE: case NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE: - if (ERROR_OK != nds32->get_watched_address(nds32, - &(nds32->watched_address), reason)) + if (nds32->get_watched_address(nds32, &(nds32->watched_address), reason) != ERROR_OK) return ERROR_FAIL; target->debug_reason = DBG_REASON_WATCHPOINT; diff --git a/src/target/nds32_cmd.c b/src/target/nds32_cmd.c index 3931707..af1f8b1 100644 --- a/src/target/nds32_cmd.c +++ b/src/target/nds32_cmd.c @@ -577,8 +577,7 @@ COMMAND_HANDLER(handle_nds32_decode_command) while (i < insn_count) { if (ERROR_OK != nds32_read_opcode(nds32, read_addr, &opcode)) return ERROR_FAIL; - if (ERROR_OK != nds32_evaluate_opcode(nds32, opcode, - read_addr, &instruction)) + if (nds32_evaluate_opcode(nds32, opcode, read_addr, &instruction) != ERROR_OK) return ERROR_FAIL; command_print(CMD, "%s", instruction.text); diff --git a/src/target/nds32_disassembler.c b/src/target/nds32_disassembler.c index 0cfd197..0bf74e1 100644 --- a/src/target/nds32_disassembler.c +++ b/src/target/nds32_disassembler.c @@ -2849,7 +2849,7 @@ static uint32_t field_mask[9] = { static uint8_t nds32_extract_field_8u(uint16_t opcode, uint32_t start, uint32_t length) { - if (0 < length && length < 9) + if (length > 0 && length < 9) return (opcode >> start) & field_mask[length]; return 0; diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index b70c259..b93e549 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -4653,10 +4653,10 @@ int riscv013_test_compliance(struct target *target) for (unsigned int i = 1; i < 32; i = i << 1) { riscv_reg_t testval = i | ((i + 1ULL) << 32); riscv_reg_t testval_read; - COMPLIANCE_TEST(ERROR_OK == register_write_direct(target, GDB_REGNO_ZERO + i, testval), + COMPLIANCE_TEST(register_write_direct(target, GDB_REGNO_ZERO + i, testval) == ERROR_OK, "GPR Writes should be supported."); COMPLIANCE_MUST_PASS(write_abstract_arg(target, 0, 0xDEADBEEFDEADBEEF, 64)); - COMPLIANCE_TEST(ERROR_OK == register_read_direct(target, &testval_read, GDB_REGNO_ZERO + i), + COMPLIANCE_TEST(register_read_direct(target, &testval_read, GDB_REGNO_ZERO + i) == ERROR_OK, "GPR Reads should be supported."); if (riscv_xlen(target) > 32) { /* Dummy comment to satisfy linter, since removing the branches here doesn't actually compile. */ @@ -4680,7 +4680,7 @@ int riscv013_test_compliance(struct target *target) if (info->progbufsize >= 3) { testvar = 0; - COMPLIANCE_TEST(ERROR_OK == register_write_direct(target, GDB_REGNO_S0, 0), + COMPLIANCE_TEST(register_write_direct(target, GDB_REGNO_S0, 0) == ERROR_OK, "Need to be able to write S0 to test ABSTRACTAUTO"); struct riscv_program program; COMPLIANCE_MUST_PASS(riscv_program_init(&program, target)); @@ -4721,7 +4721,7 @@ int riscv013_test_compliance(struct target *target) } COMPLIANCE_WRITE(target, DM_ABSTRACTAUTO, 0); - COMPLIANCE_TEST(ERROR_OK == register_read_direct(target, &value, GDB_REGNO_S0), + COMPLIANCE_TEST(register_read_direct(target, &value, GDB_REGNO_S0) == ERROR_OK, "Need to be able to read S0 to test ABSTRACTAUTO"); COMPLIANCE_TEST(testvar == value, @@ -4797,8 +4797,8 @@ int riscv013_test_compliance(struct target *target) /* Pulse reset. */ target->reset_halt = true; COMPLIANCE_MUST_PASS(riscv_set_current_hartid(target, 0)); - COMPLIANCE_TEST(ERROR_OK == assert_reset(target), "Must be able to assert NDMRESET"); - COMPLIANCE_TEST(ERROR_OK == deassert_reset(target), "Must be able to deassert NDMRESET"); + COMPLIANCE_TEST(assert_reset(target) == ERROR_OK, "Must be able to assert NDMRESET"); + COMPLIANCE_TEST(deassert_reset(target) == ERROR_OK, "Must be able to deassert NDMRESET"); /* Verify that most stuff is not affected by ndmreset. */ COMPLIANCE_READ(target, &testvar_read, DM_ABSTRACTCS); diff --git a/src/target/riscv/riscv_semihosting.c b/src/target/riscv/riscv_semihosting.c index c0e81ea..90b8ddb 100644 --- a/src/target/riscv/riscv_semihosting.c +++ b/src/target/riscv/riscv_semihosting.c @@ -137,7 +137,7 @@ semihosting_result_t riscv_semihosting(struct target *target, int *retval) semihosting->word_size_bytes = riscv_xlen(target) / 8; /* Check for ARM operation numbers. */ - if (0 <= semihosting->op && semihosting->op <= 0x31) { + if (semihosting->op >= 0 && semihosting->op <= 0x31) { *retval = semihosting_common(target); if (*retval != ERROR_OK) { LOG_ERROR("Failed semihosting operation (0x%02X)", semihosting->op); |