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author | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-19 19:02:10 -0800 |
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committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-11-19 19:02:10 -0800 |
commit | 71cde5e359f273585880ea8986709b950ba85b08 (patch) | |
tree | b04f841ddfe6c0900f48b676cbb6c84d12eea7a3 /src/target/xscale.c | |
parent | 31fb7788a605fe1c0c405444b5bab51a7e42d481 (diff) | |
download | riscv-openocd-71cde5e359f273585880ea8986709b950ba85b08.zip riscv-openocd-71cde5e359f273585880ea8986709b950ba85b08.tar.gz riscv-openocd-71cde5e359f273585880ea8986709b950ba85b08.tar.bz2 |
target: create/use register_cache_invalidate()
Create a generic register_cache_invalidate(), and use it to
replace three all-but-identical core-specific routines:
- armv4_5_invalidate_core_regs()
- armv7m_invalidate_core_regs
- mips32_invalidate_core_regs() too.
Make cache->num_regs be unsigned, avoiding various errors.
Net code shrink and simplification.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/xscale.c')
-rw-r--r-- | src/target/xscale.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/target/xscale.c b/src/target/xscale.c index 28f89f1..f13366a 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -1322,7 +1322,7 @@ static int xscale_resume(struct target *target, int current, if (!debug_execution) { /* registers are now invalid */ - armv4_5_invalidate_core_regs(target); + register_cache_invalidate(armv4_5->core_cache); target->state = TARGET_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_RESUMED); } @@ -1401,8 +1401,7 @@ static int xscale_step_inner(struct target *target, int current, target_call_event_callbacks(target, TARGET_EVENT_RESUMED); /* registers are now invalid */ - if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK) - return retval; + register_cache_invalidate(armv4_5->core_cache); /* wait for and process debug entry */ if ((retval = xscale_debug_entry(target)) != ERROR_OK) @@ -1538,7 +1537,7 @@ static int xscale_deassert_reset(struct target *target) breakpoint = breakpoint->next; } - armv4_5_invalidate_core_regs(target); + register_cache_invalidate(xscale->armv4_5_common.core_cache); /* FIXME mark hardware watchpoints got unset too. Also, * at least some of the XScale registers are invalid... |