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| author | Steven Stallion <stallion@squareup.com> | 2018-08-28 17:18:01 -0700 |
|---|---|---|
| committer | Matthias Welwarsky <matthias@welwarsky.de> | 2018-10-16 11:58:24 +0100 |
| commit | 4ab75a3634901c4e3897d771e2c75a64c7353c28 (patch) | |
| tree | 475731fa20dae25c39a88804e894b69c69900e2f /src/target/target.h | |
| parent | e72b2601e71f49af10f72c4bb6220ee2061ef173 (diff) | |
| download | riscv-openocd-4ab75a3634901c4e3897d771e2c75a64c7353c28.zip riscv-openocd-4ab75a3634901c4e3897d771e2c75a64c7353c28.tar.gz riscv-openocd-4ab75a3634901c4e3897d771e2c75a64c7353c28.tar.bz2 | |
esirisc: support eSi-RISC targets
eSi-RISC is a highly configurable microprocessor architecture for
embedded systems provided by EnSilica. This patch adds support for
32-bit targets and also includes an internal flash driver and
uC/OS-III RTOS support. This is a non-traditional target and required
a number of additional changes to support non-linear register numbers
and the 'p' packet in RTOS support for proper integration into
EnSilica's GDB port.
Change-Id: I59d5c40b3bb2ace1b1a01b2538bfab211adf113f
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/4660
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'src/target/target.h')
| -rw-r--r-- | src/target/target.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/target/target.h b/src/target/target.h index 5457f0a..d796131 100644 --- a/src/target/target.h +++ b/src/target/target.h @@ -225,6 +225,13 @@ struct gdb_fileio_info { uint64_t param_4; }; +/** Returns a description of the endianness for the specified target. */ +static inline const char *target_endianness(struct target *target) +{ + return (target->endianness == TARGET_ENDIAN_UNKNOWN) ? "unknown" : + (target->endianness == TARGET_BIG_ENDIAN) ? "big endian" : "little endian"; +} + /** Returns the instance-specific name of the specified target. */ static inline const char *target_name(struct target *target) { |