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| author | Tim Newsome <tim@sifive.com> | 2018-07-18 13:34:23 -0700 |
|---|---|---|
| committer | Matthias Welwarsky <matthias@welwarsky.de> | 2018-07-24 13:07:26 +0100 |
| commit | a51ab8ddf63a0d60eaaf3b8f3eedcada1e773c20 (patch) | |
| tree | 60cd18e3649cbc2700abfe7724954e97de640229 /src/target/target.c | |
| parent | 9363705820d9552bd24a4e876041a90a881ede55 (diff) | |
| download | riscv-openocd-a51ab8ddf63a0d60eaaf3b8f3eedcada1e773c20.zip riscv-openocd-a51ab8ddf63a0d60eaaf3b8f3eedcada1e773c20.tar.gz riscv-openocd-a51ab8ddf63a0d60eaaf3b8f3eedcada1e773c20.tar.bz2 | |
Add RISC-V support.
This supports both 0.11 and 0.13 versions of the debug spec.
Support for `-rtos riscv` will come in a separate commit since it was
easy to separate out, and is likely to be more controversial.
Flash support for the SiFive boards will also come in a later commit.
Change-Id: I1d38fe669c2041b4e21a5c54a091594aac3e2190
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4578
Tested-by: jenkins
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'src/target/target.c')
| -rw-r--r-- | src/target/target.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/target/target.c b/src/target/target.c index 591b9ea..68f9321 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -107,6 +107,7 @@ extern struct target_type or1k_target; extern struct target_type quark_x10xx_target; extern struct target_type quark_d20xx_target; extern struct target_type stm8_target; +extern struct target_type riscv_target; static struct target_type *target_types[] = { &arm7tdmi_target, @@ -139,6 +140,7 @@ static struct target_type *target_types[] = { &quark_x10xx_target, &quark_d20xx_target, &stm8_target, + &riscv_target, #if BUILD_TARGET64 &aarch64_target, #endif |