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| author | Antonio Borneo <borneo.antonio@gmail.com> | 2020-07-12 20:25:00 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2020-07-26 23:09:45 +0100 |
| commit | 480ba8ca88e3f12bb60498b35de5fc4b74d0511d (patch) | |
| tree | 0c9c94ca50a5e8861596acead9acdf53b1adf04d /src/target/startup.tcl | |
| parent | 3e6f4f8b213ce2c61b052b16606cfc81ba6d7cc4 (diff) | |
| download | riscv-openocd-480ba8ca88e3f12bb60498b35de5fc4b74d0511d.zip riscv-openocd-480ba8ca88e3f12bb60498b35de5fc4b74d0511d.tar.gz riscv-openocd-480ba8ca88e3f12bb60498b35de5fc4b74d0511d.tar.bz2 | |
target: fix minor typos and duplicated words
Change-Id: I8deb0017dc66a243e3dd51e285aa086db500decd
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5766
Tested-by: jenkins
Diffstat (limited to 'src/target/startup.tcl')
| -rw-r--r-- | src/target/startup.tcl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/target/startup.tcl b/src/target/startup.tcl index 976cd2a..93e46b5 100644 --- a/src/target/startup.tcl +++ b/src/target/startup.tcl @@ -119,7 +119,7 @@ proc ocd_process_reset_inner { MODE } { continue } - # Wait upto 1 second for target to halt. Why 1sec? Cause + # Wait up to 1 second for target to halt. Why 1sec? Cause # the JTAG tap reset signal might be hooked to a slow # resistor/capacitor circuit - and it might take a while # to charge |