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| author | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2016-09-19 17:04:03 +0200 |
|---|---|---|
| committer | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2017-02-10 14:01:39 +0100 |
| commit | b430d0a1520903213e0796e9fcbc5ab180f1fbe8 (patch) | |
| tree | 5c693e006af6000afc4a87872d6e82c13d5aff66 /src/target/oocd_trace.h | |
| parent | 4246fac240eb28e5a28112b71fc0b5f911e6c922 (diff) | |
| download | riscv-openocd-b430d0a1520903213e0796e9fcbc5ab180f1fbe8.zip riscv-openocd-b430d0a1520903213e0796e9fcbc5ab180f1fbe8.tar.gz riscv-openocd-b430d0a1520903213e0796e9fcbc5ab180f1fbe8.tar.bz2 | |
aarch64: disable interrupts when stepping [WIP]
On live hardware, interrupts will happen while the core is
held for stepping. The next step will most of the time execute an
interrupt service instead of the next line of code, which is not
what you expect. Disable interrupts through DSCR before resuming
for a step, and re-enable them again after the step happened.
This should be made configurable, like on cortex_a target.
Change-Id: I94d8ffb58cf7579dedb66bc756b7eb6828b6e8e4
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Diffstat (limited to 'src/target/oocd_trace.h')
0 files changed, 0 insertions, 0 deletions