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| author | Hsiangkai Wang <hsiangkai@gmail.com> | 2013-02-05 11:55:37 +0800 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2013-06-05 19:27:35 +0000 |
| commit | cf8a3c3d7075abad3c88cd604f8add4d06898abc (patch) | |
| tree | 56f8b5794fd385ba7ba4a6617c214a9516a443b5 /src/target/nds32_reg.h | |
| parent | ceb402dc9e903d2f3f6bc8125dfed9d82b83d2d1 (diff) | |
| download | riscv-openocd-cf8a3c3d7075abad3c88cd604f8add4d06898abc.zip riscv-openocd-cf8a3c3d7075abad3c88cd604f8add4d06898abc.tar.gz riscv-openocd-cf8a3c3d7075abad3c88cd604f8add4d06898abc.tar.bz2 | |
nds32: add new target type nds32_v2, nds32_v3, nds32_v3m
Add target code for Andes targets.
Change-Id: Ibf0e1b61b06127ca7d9ed502d98d7e2aeebbbe82
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1259
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'src/target/nds32_reg.h')
| -rw-r--r-- | src/target/nds32_reg.h | 30 |
1 files changed, 18 insertions, 12 deletions
diff --git a/src/target/nds32_reg.h b/src/target/nds32_reg.h index a941941..1c61b61 100644 --- a/src/target/nds32_reg.h +++ b/src/target/nds32_reg.h @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2013 by Andes Technology * + * Copyright (C) 2013 Andes Technology * * Hsiangkai Wang <hkwang@andestech.com> * * * * This program is free software; you can redistribute it and/or modify * @@ -24,8 +24,7 @@ #define NDS32_REGISTER_DISABLE (0x0) enum nds32_reg_number_s { - /* general registers */ - R0 = 0, + R0 = 0, /* general registers */ R1, R2, R3, @@ -64,9 +63,7 @@ enum nds32_reg_number_s { D1HI, ITB, IFC_LP, - - /* system registers */ - CR0, + CR0, /* system registers */ CR1, CR2, CR3, @@ -99,6 +96,11 @@ enum nds32_reg_number_s { IR23, IR24, IR25, + IR26, + IR27, + IR28, + IR29, + IR30, MR0, MR1, MR2, @@ -180,9 +182,7 @@ enum nds32_reg_number_s { IDR0, IDR1, SECUR0, - - /* audio registers */ - D0L24, + D0L24, /* audio registers */ D1L24, I0, I1, @@ -214,9 +214,7 @@ enum nds32_reg_number_s { CBE1, CBE2, CBE3, - - /* fpu */ - FPCSR, + FPCSR, /* fpu */ FPCFG, FS0, FS1, @@ -310,11 +308,19 @@ struct nds32_reg_s { uint8_t size; }; +struct nds32_reg_exception_s { + uint32_t reg_num; + uint32_t ex_value_bit_pos; + uint32_t ex_value_mask; + uint32_t ex_value; +}; + void nds32_reg_init(void); uint32_t nds32_reg_sr_index(uint32_t number); enum nds32_reg_type_s nds32_reg_type(uint32_t number); uint8_t nds32_reg_size(uint32_t number); const char *nds32_reg_simple_name(uint32_t number); const char *nds32_reg_symbolic_name(uint32_t number); +bool nds32_reg_exception(uint32_t number, uint32_t value); #endif |